用VHDL语言描述一个24进制的计数器电路,
1)要求输出计数值用二进制数
表
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示;
2)要求输出计数值用8421BCD码表示。输出计数值用二进制数表示:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ersijinzhi IS
PORT (CLK,RST,EN:IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END ersijinzhi;
ARCHITECTURE ERJINZHI OF ersijinzhi IS
BEGIN
PROCESS(CLK,RST)
V ARIABLE CQI:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
IF RST='1' THEN CQI:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF EN='1' THEN
IF CQI<23 THEN CQI:=CQI+1;
ELSE CQI:=(OTHERS=>'0');
END IF;
END IF;
END IF;
CQ<=CQI;
END PROCESS;
END ERJINZHI;
输出计数值用8421BCD码表示:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ersijinzhibcd IS
PORT(
CLK,RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOW : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ersijinzhibcd;
ARCHITECTURE rtl of ersijinzhibcd IS
SIGNAL LOW_REG : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL HIGH_REG : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CLR : STD_LOGIC:='0';
BEGIN
--个位计数
LOW_PROC:PROCESS(CLK,EN,CLR)
BEGIN
IF RST='1' THEN LOW_REG<=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF EN = '1' THEN
IF LOW_REG = 9 OR CLR = '1' THEN
LOW_REG <=(OTHERS=>'0');
ELSE LOW_REG <= LOW_REG + 1;
END IF;
END IF;
END IF;
END PROCESS;
LOW <= LOW_REG;
--十位计数
HIGH_PROC:PROCESS(CLK,EN,CLR)
BEGIN
IF RST='1' THEN HIGH_REG<=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF EN = '1' THEN
IF CLR = '1' THEN
HIGH_REG <=(OTHERS=>'0');
ELSIF LOW_REG = 9 THEN
HIGH_REG <= HIGH_REG + 1;
END IF;
END IF;
END IF;
END PROCESS;
HIGH <= HIGH_REG;
CLR <= '1' WHEN LOW_REG = 3 AND HIGH_REG = 2 ELSE '0'; END rtl;
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