74HC4046 pll 锁相环芯片技术手册 英文

DATA SHEET Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1997 Nov 25 INTEGRATED CIRCUITS 74HC/HCT4046A Phase-locked-loop with VCO For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 1997 Nov 25 2 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC = 4.5 V • Choice of three phase comparators: EXCLUSIVE-OR; edge-triggered JK flip-flop; edge-triggered RS flip-flop • Excellent VCO frequency linearity • VCO-inhibit control for ON/OFF keying and for low standby power consumption • Minimal frequency drift • Operating power supply voltage range: VCO section 3.0 to 6.0 V digital section 2.0 to 6.0 V • Zero voltage offset due to op-amp buffering • Output capability: standard • ICC category: MSI. GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4046A are phase-locked-loop circuits that comprise a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3) with a common signal input amplifier and a common comparator input. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the “4046A” forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required. The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input (COMPIN), or connected via a frequency-divider. The VCO output signal has a duty factor of 50% (maximum expected deviation 1%), if the VCO input is held at a constant DC level. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption. The only difference between the HC and HCT versions is the input level specification of the INH input. This input disables the VCO section. The sections of the comparator are identical, so that there is no difference in the SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC and HCT versions. Phase comparators The signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings. Phase comparator 1 (PC1) This is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter). The phase comparator gain is: The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN) as shown in Fig.6. The average of VDEMOUT is equal to 1⁄2VCC when there is no signal or noise at SIGIN and with this input the VCO oscillates at the centre frequency (fo). Typical waveforms for the PC1 loop locked at fo are shown in Fig.7. VDEMOUT VCC pi ----------- φSIGIN φCOMPIN–( )= Kp VCC pi ----------- V r⁄( )˙ .= 1997 Nov 25 3 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A The frequency capture range (2fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration retains lock even with very noisy input signals. Typical behaviour of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO centre frequency. Phase comparator 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, control-gating and a 3-state output stage. The circuit functions as an up-down counter (Fig.5) where SIGIN causes an up-count and COMPIN a down-count. The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is: where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter). The phase comparator gain is: VDEMOUT is the resultant of the initial phase differences of SIGIN and COMPIN as shown in Fig.8. Typical waveforms for the PC2 loop locked at fo are shown in Fig.9. When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). When the phase of SIGIN lags that of COMPIN, the n-type driver is held “ON”. When the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the input signal cycle time, and for the remainder of the cycle both n and p- type drivers are ”OFF” (3-state). If the SIGIN frequency is lower than the COMPIN frequency, then it is the n-type driver that is held “ON” for most of the cycle. Subsequently, the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal VDEMOUT VCC 4pi----------- φSIGIN φCOMPIN–( )= Kp VCC 4pi----------- V r⁄( ) .= and comparator inputs are equal in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high impedance. Also in this condition, the signal at the phase comparator pulse output (PCPOUT) is a HIGH level and so can be used for indicating a locked condition. Thus, for PC2, no phase difference exists between SIGIN and COMPIN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both p and n-type drivers are “OFF” for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIGIN the VCO adjusts, via PC2, to its lowest frequency. Phase comparator 3 (PC3) This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. The transfer characteristic of PC3, assuming ripple (fr = fi) is suppressed, is: where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC3OUT (via low-pass filter). The phase comparator gain is: The average output from PC3, fed to the VCO via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN as shown in Fig.10. Typical waveforms for the PC3 loop locked at fo are shown in Fig.11. The phase-to-output response characteristic of PC3 (Fig.10) differs from that of PC2 in that the phase angle between SIGIN and COMPIN varies between 0° and 360° and is 180° at the centre frequency. Also PC3 gives a greater voltage swing than PC2 for input phase differences but as a consequence the ripple content of the VCO input signal is higher. The PLL lock range for this type of phase comparator and the capture range are dependent on the low-pass filter. With no signal present at SIGIN the VCO adjusts, via PC3, to its lowest frequency. VDEMOUT VCC 2pi----------- φSIGIN φCOMPIN–( )= Kp VCC 2pi----------- V r⁄( ) .= 1997 Nov 25 4 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz. fo = output frequency in MHz. CL = output load capacitance in pF. VCC = supply voltage in V. ∑ (CL × VCC2 × fo) = sum of outputs. 2. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator sections see Figs 22, 23 and 24. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. APPLICATIONS • FM modulation and demodulation • Frequency synthesis and multiplication • Frequency discrimination • Tone decoding • Data synchronization and conditioning • Voltage-to-frequency conversion • Motor-speed control. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT fo VCO centre frequency C1 = 40 pF; R1 = 3 kΩ; VCC = 5 V 19 19 MHz CI input capacitance (pin 5) 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 24 24 pF 1997 Nov 25 5 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 PCPOUT phase comparator pulse output 2 PC1OUT phase comparator 1 output 3 COMPIN comparator input 4 VCOOUT VCO output 5 INH inhibit input 6 C1A capacitor C1 connection A 7 C1B capacitor C1 connection B 8 GND ground (0 V) 9 VCOIN VCO input 10 DEMOUT demodulator output 11 R1 resistor R1 connection 12 R2 resistor R2 connection 13 PC2OUT phase comparator 2 output 14 SIGIN signal input 15 PC3OUT phase comparator 3 output 16 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. 1997 Nov 25 6 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A MGA847 PHASE COMPARATOR 2 LOCK DETECTOR PC2OUT LD 13 1 identical to 4046A CLD CCLD 15 7046A PHASE COMPARATOR 2 PC2OUT 13 PHASE COMPARATOR 3 PC3OUT 15 PHASE COMPARATOR 1 PC1OUT 2 PCPOUT 1 SIG INCOMP INVCO OUTC1A C1B DEMOUTINH VCO IN R2 R1 R2 12 11 3 14476 5 10 9 (a) (b) C1 4046A VCO R S R1 R4 R3 C2 Fig.4 Functional diagram. (a) (b) Fig.5 Logic diagram. 1997 Nov 25 7 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A Fig.6 Phase comparator 1: average output voltage versus input phase difference. VDEMOUT = VPC2OUT = φDEMOUT = (φSIGIN − φCOMPIN). VCC pi ----------- φSIGIN φCOMPIN–( ) Fig.7 Typical waveforms for PLL using phase comparator 1, loop locked at fo. Fig.8 Phase comparator 2: average output voltage versus input phase difference. VDEMOUT = VPC2OUT = φDEMOUT = (φSIGIN − φCOMPIN). VCC 4pi----------- φSIGIN φCOMPIN–( ) 1997 Nov 25 8 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A Fig.9 Typical waveforms for PLL using phase comparator 2, loop locked at fo. Fig.10 Phase comparator 3: average output voltage versus input phase difference: VDEMOUT = VPC3OUT = φDEMOUT = (φSIGIN − φCOMPIN). VCC 2pi----------- φSIGIN φCOMPIN–( ) Fig.11 Typical waveforms for PLL using phase comparator 3, loop locked at fo. 1997 Nov 25 9 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER 74HC 74HCT UNIT CONDITIONS min. typ. max. min. typ. max. VCC DC supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 V VCC DC supply voltage if VCO section is not used 2.0 5.0 6.0 4.5 5.0 5.5 V VI DC input voltage range 0 VCC 0 VCC V VO DC output voltage range 0 VCC 0 VCC V Tamb operating ambient temperature range −40 +85 −40 +85 °C see DC and AC CHARACTERISTICS Tamb operating ambient temperature range −40 +125 −40 +125 °C tr, tf input rise and fall times (pin 5) 6.0 1000 6.0 500 ns VCC = 2.0 V 6.0 500 6.0 500 ns VCC = 4.5 V 6.0 400 6.0 500 ns VCC = 6.0 V SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS VCC DC supply voltage −0.5 +7 V ±IIK DC input diode current 20 mA for VI < −0.5 V or VI > VCC + 0.5 V ±IOK DC output diode current 20 mA for VO < −0.5 V or VO > VCC + 0.5 V ±IO DC output source or sink current 25 mA for −0.5 V < VO < VCC + 0.5 V ±ICC; ±IGND DC VCC or GND current 50 mA Tstg storage temperature range −65 +150 °C Ptot power dissipation per package plastic DIL 750 mW for temperature range: − 40 to +125 °C 74HC/HCT above + 70 °C: derate linearly with 12 mW/K plastic mini-pack (SO) 500 mW above + 70 °C: derate linearly with 8 mW/K 1997 Nov 25 10 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A DC CHARACTERISTICS FOR 74HC Quiescent supply current Voltages are referenced to GND (ground = 0 V) Phase comparator section Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) OTHER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. ICC quiescent supply current (VCO disabled) 8.0 80.0 160.0 µA 6.0 pins 3, 5, and 14 at VCC; pin 9 at GND; II at pins 3 and 14 to be excluded SYM- BOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) VI OTHER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. VIH DC coupled HIGH level input voltage SIGIN, COMPIN 1.5 1.2 1.5 1.5 V 2.0 3.15 2.4 3.15 3.15 4.5 4.2 3.2 4.2 4.2 6.0 VIL DC coupled LOW level input voltage SIGIN, COMPIN 0.8 0.5 0.5 0.5 V 2.0 2.1 1.35 1.35 1.35 4.5 2.8 1.8 1.8 1.8 6.0 VOH HIGH level output voltage PCPOUT, PCnOUT 1.9 2.0 1.9 1.9 V 2.0 VIH or VIL −IO = 20 µA 4.4 4.5 4.4 4.4 4.5 −IO = 20 µA 5.9 6.0 5.9 5.9 6.0 −IO = 20 µA VOH HIGH level output voltage PCPOUT, PCnOUT 3.98 4.32 3.84 3.7 V 4.5 VIH or VIL −IO = 4.0 mA 5.48 5.81 5.34 5.2 6.0 −IO = 5.2 mA VOL LOW level output voltage PCPOUT, PCnOUT 0 0.1 0.1 0.1 V 2.0 VIH or VIL IO = 20 µA 0 0.1 0.1 0.1 4.5 IO = 20 µA 0 0.1 0.1 0.1 6.0 IO = 20 µA VOL LOW level output voltage PCPOUT, PCnOUT 0.15 0.26 0.33 0.4 V 4.5 VIH or VIL IO = 4.0 mA 0.16 0.26 0.33 0.4 6.0 IO = 5.2 mA ±II input leakage current SIGIN, COMPIN 3.0 4.0 5.0 µA 2.0 VCC or GND 7.0 9.0 11.0 3.0 18.0 23.0 27.0 4.5 30.0 38.0 45.0 6.0 ±IOZ 3-state OFF-state current PC2OUT 0.5 5.0 10.0 µA 6.0 VIH or VIL VO = VCC or GND 1997 Nov 25 11 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A VCO section Voltages are referenced to GND (ground = 0 V) RI input resistance SIGIN, COMPIN 800 kΩ 3.0 VI at self-bias operating point; ∆ VI = 0.5 V; see Figs 12, 13 and 14 250 kΩ 4.5 150 kΩ 6.0 SYM- BOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) VI OTHER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. VIH HIGH level input voltage INH 2.1 1.7 2.1 2.1 V 3.0 3.15 2.4 3.15 3.15 4.5 4.2 3.2 4.2 4.2 6.0 VIL LOW level input voltage INH 1.3 0.9 0.9 0.9 V 3.0 2.1 1.35 1.35 1.35 4.5 2.8 1.8 1.8 1.8 6.0 VOH HIGH level output voltage VCOOUT 2.9 3.0 2.9 2.9 V 3.0 VIH or VIL −IO = 20 µA 4.4 4.5 4.4 4.4 4.5 −IO = 20 µA 5.9 6.0 5.9 5.9 6.0 −IO = 20 µA VOH HIGH level output voltage VCOOUT 3.98 4.32 3.84 3.7 V 4.5 VIH or VIL −IO = 4.0 mA 5.48 5.81 5.34 5.2 6.0 −IO = 5.2 mA VOL LOW level output voltage VCOOUT 0 0.1 0.1 0.1 V 3.0 VIH or VIL IO = 20 µA 0 0.1 0.1 0.1 4.5 IO = 20 µA 0 0.1 0.1 0.1 6.0 IO = 20 µA VOL LOW level output voltage VCOOUT 0.15 0.26 0.33 0.4 V 4.5 VIH or VIL IO = 4.0 mA 0.16 0.26 0.33 0.4 6.0 IO = 5.2 mA VOL LOW level output voltage C1A, C1B 0.40 0.47 0.54 V 4.5 VIH or VIL IO = 4.0 mA 0.40 0.47 0.54 6.0 IO = 5.2 mA ±II input leakage current INH, VCOIN 0.1 1.0 1.0 µA 6.0 VCC or GND R1 resistor range 3.0 300 kΩ 3.0 note 1 3.0 300 4.5 3.0 300 6.0 SYM- BOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) VI OTHER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. 1997 Nov 25 12 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A Note 1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/ or R2 are/is > 10 kΩ. Demodulator section Voltages are referenced to GND (ground = 0 V) R2 resistor range 3.0 300 kΩ 3.0 note 1 3.0 300 4.5 3.0 300 6.0 C1 capacitor range 40 no limit pF 3.0 40 4.5 40 6.0 VVCOIN operating voltage range at VCOIN 1.1 1.9 V 3.0 over the range specified for R1; for linearity see Figs 20 and 21 1.1 3.4 4.5 1.1 4.9 6.0 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC V OTHER +25 −40 to+85 −40 to +125 min. typ. max. min. max. min. max. RS resistor range 50 300 kΩ 3.0 at RS > 300 kΩ the leakage current can influence VDEMOUT 50 300 4.5 50 300 6.0 VOFF offset voltage VCOIN to VDEMOUT ±30 mV 3.0 VI = VVCOIN = 1/2 VCC; values taken over RS range; see Fig.15 ±20 4.5 ±10 6.0 RD dynamic output resistance at DEMOUT 25 Ω 3.0 VDEMOUT = 1/2 VCC 25 4.5 25 6.0 SYM- BOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) VI OTHER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. 1997 Nov 25 13 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A AC CHARACTERISTICS FOR 74HC Phase comparator section GND = 0 V; tr = tf = 6 ns; CL = 50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) OTHER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay SIGIN, COMPIN to PC1OUT 63 200 250 300 ns 2.0 Fig.16 23 40 50 60 4.5 18 34 43 51 6.0 tPHL/ tPLH propagation delay SIGIN, COMPIN to PCPOUT 96 340 425 510 ns 2.0 Fig.16 35 68 85 102 4.5 28 58 72 87 6.0 tPHL/ tPLH propagation delay SIGIN, COMPIN to PC3OUT 77 270 340 405 ns 2.0 Fig.16 28 54 68 81 4.5 22 46 58 69 6.0 tPZH/ tPZL 3-state output enable time SIGIN, COMPIN to PC2OUT 83 280 350 420 ns 2.0 Fig.17 30 56 70 84 4.5 24 48 60 71 6.0 tPHZ/ tPLZ 3-state output disable time SIGIN, COMPIN to PC2OUT 99 325 405 490 ns 2.0 Fig.17 36 65 81 98 4.5 29 55 69 83 6.0 tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Fig.16 7 15 19 22 4.5 6 13 16 19 6.0 VI(p-p) AC coupled input sensitivity (peak-to-peak value) at SIGIN or COMPIN 9 mV 2.0 fi = 1 MHz 11 3.0 15 4.5 33 6.0 1997 Nov 25 14 Philips Semiconductors Product specification Phase-locked-loop with VCO 74HC/HCT4046A VCO section GND = 0 V; tr = tf = 6 ns; CL = 50 pF DC CHARACTERISTICS FOR 74HCT Quiescent supply current Voltages are referenced to GND (ground = 0 V) Note 1. The value of additional quiescent supply