ADC0804英文版

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters General Description The ADC0801, ADC0802, ADC0803, ADC0804 and ADC0805 are CMOS 8-bit successive approximation A/D converters that use a differential potentiometric ladder — similar to the 256R products. These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI-STATE output latches directly driving the data bus. These A/Ds appear like memory loca- tions or I/O ports to the microprocessor and no interfacing logic is needed. Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Features n Compatible with 8080 µP derivatives — no interfacing logic needed - access time - 135 ns n Easy interface to all microprocessors, or operates “stand alone” n Differential analog voltage inputs n Logic inputs and outputs meet both MOS and TTL voltage level specifications n Works with 2.5V (LM336) voltage reference n On-chip clock generator n 0V to 5V analog input voltage range with single 5V supply n No zero adjust required n 0.3" standard width 20-pin DIP package n 20-pin molded chip carrier or small outline package n Operates ratiometrically or with 5 VDC, 2.5 VDC, or analog span adjusted voltage reference Key Specifications n Resolution 8 bits n Total error ±1⁄4 LSB, ±1⁄2 LSB and ±1 LSB n Conversion time 100 µs Connection Diagram Ordering Information TEMP RANGE 0˚C TO 70˚C 0˚C TO 70˚C −40˚C TO +85˚C ±1⁄4 Bit Adjusted ADC0801LCN ERROR ±1⁄2 Bit Unadjusted ADC0802LCWM ADC0802LCN ±1⁄2 Bit Adjusted ADC0803LCN ±1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ PACKAGE OUTLINE M20B — Small Outline N20A — Molded DIP Z-80® is a registered trademark of Zilog Corp. ADC080X Dual-In-Line and Small Outline (SO) Packages DS005671-30 See Ordering Information November 1999 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-BitµP Com patible A/D Converters © 2001 National Semiconductor Corporation DS005671 www.national.com Typical Applications Error Specification (Includes Full-Scale, Zero Error, and Non-Linearity) Part Full- VREF/2=2.500 VDC VREF/2=No Connection Number Scale (No Adjustments) (No Adjustments) Adjusted ADC0801 ±1⁄4 LSB ADC0802 ±1⁄2 LSB ADC0803 ±1⁄2 LSB ADC0804 ±1 LSB ADC0805 ±1 LSB DS005671-1 8080 Interface DS005671-31 AD C0 80 1/ AD C0 80 2/ AD C0 80 3/ AD C0 80 4/ AD C0 80 5 www.national.com 2 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) (Note 3) 6.5V Voltage Logic Control Inputs −0.3V to +18V At Other Input and Outputs −0.3V to (VCC+0.3V) Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260˚C Dual-In-Line Package (ceramic) 300˚C Surface Mount Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C Storage Temperature Range −65˚C to +150˚C Package Dissipation at TA=25˚C 875 mW ESD Susceptibility (Note 10) 800V Operating Ratings (Notes 1, 2) Temperature Range TMIN≤TA≤TMAX ADC0804LCJ −40˚C≤TA≤+85˚C ADC0801/02/03/05LCN −40˚C≤TA≤+85˚C ADC0804LCN 0˚C≤TA≤+70˚C ADC0802/04LCWM 0˚C≤TA≤+70˚C Range of VCC 4.5 VDC to 6.3 VDC Electrical Characteristics The following specifications apply for VCC=5 VDC, TMIN≤TA≤TMAX and fCLK=640 kHz unless otherwise specified. Parameter Conditions Min Typ Max Units ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj. ±1⁄4 LSB (See Section 2.5.2) ADC0802: Total Unadjusted Error (Note 8) VREF/2=2.500 VDC ±1⁄2 LSB ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj. ±1⁄2 LSB (See Section 2.5.2) ADC0804: Total Unadjusted Error (Note 8) VREF/2=2.500 VDC ±1 LSB ADC0805: Total Unadjusted Error (Note 8) VREF/2-No Connection ±1 LSB VREF/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kΩ ADC0804 (Note 9) 0.75 1.1 kΩ Analog Input Voltage Range (Note 4) V(+) or V(−) Gnd–0.05 VCC+0.05 VDC DC Common-Mode Error Over Analog Input Voltage ±1/16 ±1⁄8 LSB Range Power Supply Sensitivity VCC=5 VDC ±10% Over ±1/16 ±1⁄8 LSB Allowed VIN(+) and VIN(−) Voltage Range (Note 4) AC Electrical Characteristics The following specifications apply for VCC=5 VDC and TMIN≤TA≤TMAX unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units TC Conversion Time fCLK=640 kHz (Note 6) 103 114 µs TC Conversion Time (Notes 5, 6) 66 73 1/fCLK fCLK Clock Frequency VCC=5V, (Note 5) 100 640 1460 kHz Clock Duty Cycle 40 60 % CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s Mode CS =0 VDC, fCLK=640 kHz tW(WR)L Width of WR Input (Start Pulse Width) CS =0 VDC (Note 7) 100 ns tACC Access Time (Delay from Falling CL=100 pF 135 200 ns Edge of RD to Output Data Valid) t1H, t0H TRI-STATE Control (Delay CL=10 pF, RL=10k 125 200 ns from Rising Edge of RD to (See TRI-STATE Test Hi-Z State) Circuits) tWI, tRI Delay from Falling Edge 300 450 ns of WR or RD to Reset of INTR CIN Input Capacitance of Logic 5 7.5 pF Control Inputs ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com3 AC Electrical Characteristics (Continued) The following specifications apply for VCC=5 VDC and TMIN≤TA≤TMAX unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units COUT TRI-STATE Output 5 7.5 pF Capacitance (Data Buffers) CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) Logical “1” Input Voltage VCC=5.25 VDC 2.0 15 VDC (Except Pin 4 CLK IN) VIN (0) Logical “0” Input Voltage VCC=4.75 VDC 0.8 VDC (Except Pin 4 CLK IN) IIN (1) Logical “1” Input Current VIN=5 VDC 0.005 1 µADC (All Inputs) IIN (0) Logical “0” Input Current VIN=0 VDC −1 −0.005 µADC (All Inputs) CLOCK IN AND CLOCK R VT+ CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 VDC Threshold Voltage VT− CLK IN (Pin 4) Negative 1.5 1.8 2.1 VDC Going Threshold Voltage VH CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 VDC (VT+)−(VT−) VOUT (0) Logical “0” CLK R Output IO=360 µA 0.4 VDC Voltage VCC=4.75 VDC VOUT (1) Logical “1” CLK R Output IO=−360 µA 2.4 VDC Voltage VCC=4.75 VDC DATA OUTPUTS AND INTR VOUT (0) Logical “0” Output Voltage Data Outputs IOUT=1.6 mA, VCC=4.75 VDC 0.4 VDC INTR Output IOUT=1.0 mA, VCC=4.75 VDC 0.4 VDC VOUT (1) Logical “1” Output Voltage IO=−360 µA, VCC=4.75 VDC 2.4 VDC VOUT (1) Logical “1” Output Voltage IO=−10 µA, VCC=4.75 VDC 4.5 VDC IOUT TRI-STATE Disabled Output VOUT=0 VDC −3 µADC Leakage (All Data Buffers) VOUT=5 VDC 3 µADC ISOURCE VOUT Short to Gnd, TA=25˚C 4.5 6 mADC ISINK VOUT Short to VCC, TA=25˚C 9.0 16 mADC POWER SUPPLY ICC Supply Current (Includes fCLK=640 kHz, Ladder Current) VREF/2=NC, TA=25˚C and CS =5V ADC0801/02/03/04LCJ/05 1.1 1.8 mA ADC0804LCN/LCWM 1.9 2.5 mA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd. Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC. Note 4: For VIN(−)≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns. Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see Figure 4 and section 2.0. AD C0 80 1/ AD C0 80 2/ AD C0 80 3/ AD C0 80 4/ AD C0 80 5 www.national.com 4 AC Electrical Characteristics (Continued) Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams). Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7. Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kΩ. Note 10: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Typical Performance Characteristics Logic Input Threshold Voltage vs. Supply Voltage DS005671-38 Delay From Falling Edge of RD to Output Data Valid vs. Load Capacitance DS005671-39 CLK IN Schmitt Trip Levels vs. Supply Voltage DS005671-40 fCLK vs. Clock Capacitor DS005671-41 Full-Scale Error vs Conversion Time DS005671-42 Effect of Unadjusted Offset Error vs. VREF/2 Voltage DS005671-43 Output Current vs Temperature DS005671-44 Power Supply Current vs Temperature (Note 9) DS005671-45 Linearity Error at Low VREF/2 Voltages DS005671-46 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com5 TRI-STATE Test Circuits and Waveforms Timing Diagrams (All timing is measured from the 50% voltage points) t1H DS005671-47 t1H, CL=10 pF DS005671-48 tr=20 ns t0H DS005671-49 t0H, CL=10 pF DS005671-50 tr=20 ns DS005671-51 AD C0 80 1/ AD C0 80 2/ AD C0 80 3/ AD C0 80 4/ AD C0 80 5 www.national.com 6 Timing Diagrams (All timing is measured from the 50% voltage points) (Continued) Typical Applications Output Enable and Reset with INTR DS005671-52 Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR . 6800 Interface DS005671-53 Ratiometeric with Full-Scale Adjust DS005671-54 Note: before using caps at VIN or VREF/2, see section 2.3.2 Input Bypass Capacitors. ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com7 Typical Applications (Continued) Absolute with a 2.500V Reference DS005671-55 *For low power, see also LM385–2.5 Absolute with a 5V Reference DS005671-56 Zero-Shift and Span Adjust: 2V ≤ VIN ≤ 5V DS005671-57 Span Adjust: 0V ≤ VIN ≤ 3V DS005671-58 AD C0 80 1/ AD C0 80 2/ AD C0 80 3/ AD C0 80 4/ AD C0 80 5 www.national.com 8 Typical Applications (Continued) Directly Converting a Low-Level Signal DS005671-59 VREF/2=256 mV A µP Interfaced Comparator DS005671-60 For: VIN(+)>VIN(−) Output=FFHEX For: VIN(+)VIN(−)+(VREF/2) Omit circuitry within the dotted area if hysteresis is not needed ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com11 Typical Applications (Continued) Handling ±10V Analog Inputs DS005671-70 *Beckman Instruments #694-3-R10K resistor array Low-Cost, µP Interfaced, Temperature-to-Digital Converter DS005671-71 µP Interfaced Temperature-to-Digital Converter DS005671-72 *Circuit values shown are for 0˚C≤TA≤+128˚C ***Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage. AD C0 80 1/ AD C0 80 2/ AD C0 80 3/ AD C0 80 4/ AD C0 80 5 www.national.com 12 Typical Applications (Continued) Handling ±5V Analog Inputs DS005671-33 *Beckman Instruments #694-3-R10K resistor array Read-Only Interface DS005671-34 µP Interfaced Comparator with Hysteresis DS005671-35 Protecting the Input DS005671-9 Diodes are 1N914 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com13 Typical Applications (Continued) Analog Self-Test for a System DS005671-36 A Low-Cost, 3-Decade Logarithmic Converter DS005671-37 *LM389 transistors A, B, C, D = LM324A quad op amp AD C0 80 1/ AD C0 80 2/ AD C0 80 3/ AD C0 80 4/ AD C0 80 5 www.national.com 14 Typical Applications (Continued) 3-Decade Logarithmic A/D Converter DS005671-73 Noise Filtering the Analog Input DS005671-74 fC=20 Hz Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order, low-pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Multiplexing Differential Inputs DS005671-75 Output Buffers with A/D Data Enabled DS005671-76 *A/D output data is updated 1 CLK period prior to assertion of INTR Increasing Bus Drive and/or Reducing Time on Bus DS005671-77 *Allows output data to set-up at falling edge of CS ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com15 Typical Applications (Continued) Functional Description 1.0 UNDERSTANDING A/D ERROR SPECS A perfect A/D transfer characteristic (staircase waveform) is shown in Figure 1. The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53 mV with 2.5V tied to the VREF/2 pin). The digital output codes that correspond to these inputs are shown as D−1, D, and D+1. For the perfect A/D, not only will center-value (A−1, A, A+1, . . . . ) analog inputs produce the correct output digital codes, but also each riser (the transitions between adjacent output codes) will be located ±1⁄2 LSB away from each center-value. As shown, the risers are ideal and have no width. Correct digital output codes will be provided for a range of analog input voltages that extend Sampling an AC Input Signal DS005671-78 Note 11: Oversample whenever possible [keep fs > 2f(−60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter. Note 12: Consider the amplitude errors which are introduced within the passband of the filter. 70% Power Savings by Clock Gating DS005671-79 (Complete shutdown takes ≈ 30 seconds.) Power Savings by A/D and VREF Shutdown DS005671-80 *Use ADC0801, 02, 03 or 05 for lowest power consumption. Note: Logic inputs can be driven to VCC with A/D supply at zero volts. Buffer prevents data bus from overdriving output of A/D when in shutdown mode. AD C0 80 1/ AD C0 80 2/ AD C0 80 3/ AD C0 80 4/ AD C0 80 5 www.national.com 16 Functional Description (Continued) ±1⁄2 LSB from the ideal center-values. Each tread (the range of analog input voltage that provides the same digital output code) is therefore 1 LSB wide. Figure 2 shows a worst case error plot for the ADC0801. All center-valued inputs are guaranteed to produce the correct output codes and the adjacent risers are guaranteed to be no closer to the center-value points than ±1⁄4 LSB. In other words, if we apply an analog input equal to the center-value ±1⁄4 LSB, we guarantee that the A/D will produce the correct digital code. The maximum range of the position of the code transition is indicated by the horizontal arrow and it is guar- anteed to be no more than 1⁄2 LSB. The error curve of Figure 3 shows a worst case error plot for the ADC0802. Here we guarantee that if we apply an analog input equal to the LSB analog voltage center-value the A/D will produce the correct digital code. Next to each transfer function is shown the corresponding error plot. Many people may be more familiar with error plots than transfer functions. The analog input voltage to the A/D is provided by either a linear ramp or by the discrete output steps of a high resolution DAC. Notice that the error is continuously displayed and includes the quantization uncer- tainty of the A/D. For example the error at point 1 of Figure 1 is +1⁄2 LSB because the digital code appeared 1⁄2 LSB in advance of the center-value of the tread. The error plots always have a constant negative slope and the abrupt up- side steps are always 1 LSB in magnitude. Transfer Function DS005671-81 Error Plot DS005671-82 FIGURE 1. Clarifying the Error Specs of an A/D Converter Accuracy=±0 LSB: A Perfect A/D Transfer Function DS005671-83 Error Plot DS005671-84 FIGURE 2. Clarifying the Error Specs of an A/D Converter Accuracy=±1⁄4 LSB ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 www.national.com17 Functional Description (Continued) 2.0 FUNCTIONAL DESCRIPTION The ADC0801 series contains a circuit equivalent of the 256R network. Analog switches are sequenced by succes- sive approximation logic to match the analog difference input voltage [VIN(+) − VIN(−)] to a corresponding tap on the R network. The most significant bit is tested first and after 8 comparisons (64 clock cycles) a digital 8-bit binary code (1111 1111 = full-scale) is transferred to an output latch and then an interrupt is asserted (INTR makes a high-to-low transition). A conversion in process can be interrupted by issuing a second start command. The device may be oper- ated in the free-running mode by connecting INTR to the WR input with CS =0. To ensure start-up under all possible conditions, an external WR pulse is required during the first power-up cycle. On the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset. As long as the CS input and WR input remain low, the A/D will remain in a reset state. Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low-to-high transition. A functional diagram of the A/D converter is shown in Figure 4. All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines. The converter is started by having CS and WR simulta- neously low. This sets the start flip-flop (F/F) and the result- ing “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this “1” to the Q output of F/F1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or