ADC0804英文资料

1 ® ADC0803, ADC0804 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved FN3094.4 8-Bit, Microprocessor-Compatible, A/D Converters The ADC080X family are CMOS 8-Bit, successive- approximation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required. The differential analog voltage input has good common- mode-rejection and permits offsetting the analog zero-input- voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Typical Application Schematic Features • 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required • Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . <100µs • Easy Interface to Most Microprocessors • Will Operate in a “Stand Alone” Mode • Differential Analog Voltage Inputs • Works with Bandgap Voltage References • TTL Compatible Inputs and Outputs • On-Chip Clock Generator • Analog Voltage Input Range (Single + 5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0V to 5V • No Zero-Adjust Required • 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required Pinout ADC0803, ADC0804 (PDIP) TOP VIEW 3 2 1 12 11 5 15 14 13 18 17 16 7 6 10 9 8 4 19 20 WR RD CS DB6 DB7 INTR DB3 DB4 DB5 DB0 DB1 DB2 CLK IN CLK R V+ VIN (-) VIN (+) DGND VREF/2 AGND ANY µPROCESSOR 8-BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE DIFF INPUTS 10K 150pF VREF/2 µP B U S +5V 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 WR RD CS CLK IN INTR VIN (-) VIN (+) DGND VREF/2 AGND V+ OR VREF CLK R DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) Ordering Information PART NUMBER ERROR EXTERNAL CONDITIONS TEMP. RANGE (oC) PACKAGE PKG. NO ADC0803LCN ±1/2 LSB VREF/2 Adjusted for Correct Full Scale Reading 0 to 70 20 Ld PDIP E20.3 ADC0804LCN ±1 LSB VREF/2 = 2.500VDC (No Adjustments) 0 to 70 20 Ld PDIP E20.3 Data Sheet August 2002 ADC0803, ADC0804 Functional Diagram 1211 151413 181716 WR RD CS INTR CLK OSC CLK R V+ VIN (-) VIN (+) DGND VREF/2 AGND (VREF) DAC VOUT COMP CLK GEN CLKS CLK A RESET START F/F LADDER AND DECODER SUCCESSIVE APPROX. REGISTER AND LATCH 8-BIT SHIFT REGISTER D RESET SET CONV. COMPL. THREE-STATE OUTPUT LATCHES DIGITAL OUTPUTS THREE-STATE CONTROL “1” = OUTPUT ENABLE DFF2 CLK A XFER G2 Q 8 X 1/f R Q INTR F/F IF RESET = “0” D DFF1 Q D Q CLK B STARTCONVERSION MSB LSB Q “1” = RESET SHIFT REGISTER “0” = BUSY AND RESET STATE RESET READ SET3 2 1 5 7 6 10 9 8 4 19 20 CLK IN MSB G1 CLK - + LSB INPUT PROTECTION FOR ALL LOGIC INPUTS INPUT TO INTERNAL BV = 30V CIRCUITS ∑ V+ + - 2 Absolute Maximum Ratings Thermal Information ADC0803, ADC0804 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Voltage at Any Input. . . . . . . . . . . . . . . . . . . . . . -0.3V to (V+ +0.3V) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Notes 2, 8) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CONVERTER SPECIFICATIONS V+ = 5V, TA = 25oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0803 VREF/2 Adjusted for Correct Full Scale Reading - - ±1/2 LSB ADC0804 VREF/2 = 2.500V - - ±1 LSB VREF/2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - kΩ Analog Input Voltage Range (Note 3) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/16 ±1/8 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/16 ±1/8 LSB CONVERTER SPECIFICATIONS V+ = 5V, 0oC to 70oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0803 VREF/2 Adjusted for Correct Full Scale Reading - - ±1/2 LSB ADC0804 VREF/2 = 2.500V - - ±1 LSB VREF/2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - kΩ Analog Input Voltage Range (Note 3) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/8 ±1/4 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/16 ±1/8 LSB AC TIMING SPECIFICATIONS V+ = 5V, and TA = 25oC, Unless Otherwise Specified Clock Frequency, fCLK V+ = 6V (Note 4) 100 640 1280 kHz V+ = 5V 100 640 800 kHz Clock Periods per Conversion (Note 5), tCONV 62 - 73 Clocks/Conv Conversion Rate In Free-Running Mode, CR INTR tied to WR with CS = 0V, fCLK = 640kHz - - 8888 Conv/s Width of WR Input (Start Pulse Width), tW(WR)I CS = 0V (Note 6) 100 - - ns Access Time (Delay from Falling Edge of RD to Output Data Valid), tACC CL = 100pF (Use Bus Driver IC for Larger CL) - 135 200 ns Three-State Control (Delay from Rising Edge of RD to Hl-Z State), t1H, t0H CL = 10pF, RL= 10K (See Three-State Test Circuits) - 125 250 ns Delay from Falling Edge of WR to Reset of INTR, tWI, tRI - 300 450 ns Input Capacitance of Logic Control Inputs, CIN - 5 - pF Three-State Output Capacitance (Data Buffers), COUT - 5 - pF 3 ADC0803, ADC0804 DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX, Unless Otherwise Specified CONTROL INPUTS (Note 7) Logic “1“ Input Voltage (Except Pin 4 CLK IN), VINH V+ = 5.25V 2.0 - V+ V Logic “0“ Input Voltage (Except Pin 4 CLK IN), VINL V+ = 4.75V - - 0.8 V CLK IN (Pin 4) Positive Going Threshold Voltage, V+CLK 2.7 3.1 3.5 V CLK IN (Pin 4) Negative Going Threshold Voltage, V-CLK 1.5 1.8 2.1 V CLK IN (Pin 4) Hysteresis, VH 0.6 1.3 2.0 V Logic “1” Input Current (All Inputs), IINHI VlN = 5V - 0.005 1 µΑ Logic “0” Input Current (All Inputs), IINLO VlN = 0V -1 -0.005 - µA Supply Current (Includes Ladder Current), I+ fCLK = 640kHz, TA = 25oC and CS = Hl - 1.3 2.5 mA DATA OUTPUTS AND INTR Logic “0” Output Voltage, VOL lO = 1.6mA, V+ = 4.75V - - 0.4 V Logic “1” Output Voltage, VOH lO = -360µA, V+ = 4.75V 2.4 - - V Three-State Disabled Output Leakage (All Data Buffers), ILO VOUT = 0V -3 - - µA VOUT = 5V - - 3 µA Output Short Circuit Current, ISOURCE VOUT Short to GND, TA = 25oC 4.5 6 - mA Output Short Circuit Current, ISINK VOUT Short to V+, TA = 25oC 9.0 16 - mA NOTES: 2. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the DGND, being careful to avoid ground loops. 3. For VIN(-) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature variations, initial tolerance and loading. 4. With V+ = 6V, the digital logic interfaces are no longer TTL compatible. 5. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. 6. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams). 7. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately. 8. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span exists (for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet. Electrical Specifications (Notes 2, 8) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Timing Waveforms FIGURE 1A. t1H FIGURE 1B. t1H, CL = 10pF 10K V+ RD CS CL DATA OUTPUT RD 2.4V tr 90% 50% 10% t1H 0.8V DATA OUTPUTS GND tr = 20ns VOH 90% 4 ADC0803, ADC0804 FIGURE 1C. t0H FIGURE 1D. t0H, CL = 10pF FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS Timing Waveforms (Continued) 10K V+ RD CS CL DATA OUTPUT V+ RD 2.4V tr 90% 50% 10% t0H 0.8V DATA OUTPUTS VOI tr = 20ns V+ 10% Typical Performance Curves FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT DATA VALID vs LOAD CAPACITANCE FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY VOLTAGE FIGURE 5. fCLK vs CLOCK CAPACITOR -55oC TO 125oC 1.8 1.7 1.6 1.5 1.4 1.3 4.754.50 5.00 5.25 5.50 V+ SUPPLY VOLTAGE (V) LO G IC IN PU T TH R ES H O LD V O LT A G E (V ) D EL AY (n s) 500 400 300 200 100 0 LOAD CAPACITANCE (pF) 200 400 600 800 1000 C LK IN T H R ES H O LD V O LT A G E (V ) 3.5 3.1 2.7 2.3 1.9 1.5 4.50 V+ SUPPLY VOLTAGE (V) -55oC TO 125oC VT(-) VT(+) 4.75 5.00 5.25 5.50 1000 CLOCK CAPACITOR (pF) f C LK (k H z) 100 10010 1000 R = 10K R = 50K R = 20K 5 ADC0803, ADC0804 FIGURE 6. FULL SCALE ERROR vs fCLK FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR FIGURE 8. OUTPUT CURRENT vs TEMPERATURE FIGURE 9. POWER SUPPLY CURRENT vs TEMPERATURE Typical Performance Curves (Continued) FU LL S C A LE E R R O R (L SB s) 7 6 5 4 3 2 1 0 fCLK (kHz) 0 400 800 1200 1600 2000 V+ = 4.5V V+ = 5V V+ = 6V VIN(+) = VIN(-) = 0V ASSUMES VOS = 2mV THIS SHOWS THE NEED FOR A ZERO ADJUSTMENT IF THE SPAN IS REDUCED O FF SE T ER R O R (L SB s) 16 14 12 10 8 6 4 2 VREF/2 (V) 0 0.01 0.1 1.0 5 O U TP U T C U R R EN T (m A ) 8 7 6 5 4 3 2 -50 TA AMBIENT TEMPERATURE (oC) -ISINK VOUT = 0.4V ISOURCE VOUT = 2.4V DATA OUTPUT BUFFERS V+ = 5V -25 0 25 50 75 100 125 PO W ER S U PP LY C U R R EN T (m A ) TA AMBIENT TEMPERATURE (oC) -50 -25 0 25 50 75 100 125 1.6 1.5 1.4 1.3 1.2 1.1 1.0 fCLK = 640kHz V+ = 5.5V V+ = 5.0V V+ = 4.5V Timing Diagrams FIGURE 10A. START CONVERSION tWI tW(WR)I 1 TO 8 x 1/fCLK INTERNAL TC CS WR ACTUAL INTERNAL STATUS OF THE CONVERTER INTR (LAST DATA READ) (LAST DATA NOT READ) “NOT BUSY” “BUSY” DATA IS VALID IN OUTPUT LATCHES INTR ASSERTED tVI 1/2 fCLK 6 ADC0803, ADC0804 FIGURE 10B. OUTPUT ENABLE AND RESET INTR Timing Diagrams (Continued) VALID DATA VALID DATA INTR RESET INTR CS RD DATA OUTPUTS THREE-STATE (HI-Z) tRI tACC t1H , t0H TRANSFER FUNCTION ERROR PLOT FIGURE 11A. ACCURACY = ±0 LSB; PERFECT A/D TRANSFER FUNCTION ERROR PLOT FIGURE 11B. ACCURACY = ±1/2 LSB FIGURE 11. CLARIFYING THE ERROR SPECS OF AN A/D CONVERTER ANALOG INPUT (VIN) D IG IT A L O U TP U T C O D E D + 1 D D - 1 A + 1AA - 1 3 21 5 6 4 3 2 1 5 64 ER R O R 0 +1 LSB -1 LSB -1/2 LSB +1/2 LSB * QUANTIZATION ERROR A ANALOG INPUT (VIN) A + 1A - 1 ANALOG INPUT (VIN) D IG IT A L O U TP U T C O D E D + 1 D D - 1 A + 1AA - 1 3 2 1 5 6 4 *0 +1 LSB -1 LSB QUANTIZATION ER R O R 3 2 1 6 4 ANALOG INPUT (VIN) A + 1AA - 1 ERROR 7 ADC0803, ADC0804 Understanding A/D Error Specs A perfect A/D transfer characteristic (staircase wave-form) is shown in Figure 11A. The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53mV with 2.5V tied to the VREF/2 pin). The digital output codes which correspond to these inputs are shown as D-1, D, and D+1. For the perfect A/D, not only will center- value (A - 1, A, A + 1, . . .) analog inputs produce the correct output digital codes, but also each riser (the transitions between adjacent output codes) will be located ±1/2 LSB away from each center-value. As shown, the risers are ideal and have no width. Correct digital output codes will be provided for a range of analog input voltages which extend ±1/2 LSB from the ideal center-values. Each tread (the range of analog input voltage which provides the same digital output code) is therefore 1 LSB wide. The error curve of Figure 11B shows the worst case transfer function for the ADC080X. Here the specification guarantees that if we apply an analog input equal to the LSB analog voltage center-value, the A/D will produce the correct digital code. Next to each transfer function is shown the corresponding error plot. Notice that the error includes the quantization uncertainty of the A/D. For example, the error at point 1 of Figure 11A is +1/2 LSB because the digital code appeared 1/2 LSB in advance of the center-value of the tread. The error plots always have a constant negative slope and the abrupt upside steps are always 1 LSB in magnitude, unless the device has missing codes. Detailed Description The functional diagram of the ADC080X series of A/D converters operates on the successive approximation principle (see Application Notes AN016 and AN020 for a more detailed description of this principle). Analog switches are closed sequentially by successive-approximation logic until the analog differential input voltage [VlN(+) - VlN(-)] matches a voltage derived from a tapped resistor string across the reference voltage. The most significant bit is tested first and after 8 comparisons (64 clock cycles), an 8- bit binary code (1111 1111 = full scale) is transferred to an output latch. The normal operation proceeds as follows. On the high-to-low transition of the WR input, the internal SAR latches and the shift-register stages are reset, and the INTR output will be set high. As long as the CS input and WR input remain low, the A/D will remain in a reset state. Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low- to-high transition. After the requisite number of clock pulses to complete the conversion, the INTR pin will make a high-to-low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion. A RD operation (with CS low) will clear the INTR line high again. The device may be operated in the free-running mode by connecting INTR to the WR input with CS = 0. To ensure start- up under all possible conditions, an external WR pulse is required during the first power-up cycle. A conversion-in- process can be interrupted by issuing a second start command. Digital Operation The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flip-flop, DFF1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this “1” to the Q output of DFF1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”), the start F/F is reset and the 8-bit shift register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would be at a “1” level) and the 8-bit shift register would continue to be held in the reset mode. This allows for asynchronous or wide CS and WR signals. After the “1” is clocked through the 8-bit shift register (which completes the SAR operation) it appears as the input to DFF2. As soon as this “1” is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the Three-State output latches. When DFF2 is subsequently clocked, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR output signal. When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the three- state output latches will be enabled to provide the 8-bit digital outputs. Digital Control Inputs The digital control inputs (CS, RD, and WR) meet standard TTL logic voltage levels. These signals are essentially equivalent to the standard A/D Start and Output Enable control signals, and are active low to allow an easy interface to microprocessor control busses. For non-microprocessor based applications, the CS input (pin 1) can be grounded and the standard A/D Start function obtained by an active low pulse at the WR input (pin 3). The Output Enable function is achieved by an active low pulse at the RD input (pin 2). Analog Operation The analog comparisons are performed by a capacitive charge summing circuit. Three capacitors (with precise ratioed values) share a common node with the input to an auto- zeroed comparator. The input capacitor is switched between VlN(+) and VlN(-), while two ratioed reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the current total value set by the 8 ADC0803, ADC0804 successive approximation register. A correction is made to offset the comparison by 1/2 LSB (see Figure 11A). Analog Differential Voltage Inputs and Common- Mode Rejection This A/D gains considerable applications flexibility from the analog differential voltage input. The VlN(-) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also useful in 4mA - 20mA current loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling VIN(+) and VlN(-) is 41/2 clock periods. The maximum error voltage due to this slight time difference between the input voltage samples is given by: where: ∆VE is the error voltage due to sampling delay, VPEAK is the peak value of the common-mode voltage, fCM is the common-mode frequency. For example, with a 60Hz common-mode frequency, fCM, and a 640kHz A/D clock, fCLK, keeping this error to 1/4 LSB (~5mV) would allow a common-mode voltage, VPEAK, given by: , or . The allowed range of analog input voltage usually places more severe restrictions on input common-mode voltage levels than this. An analog input voltage with a reduced span and a relatively large zero offset can be easily handled by making use of the differential input (see Reference Voltage Span Adjust). Analog Input Current The internal switching action causes displacement currents