EDA数字时钟设计

------------------------------------------作者xxxx------------------------------------------日期xxxxEDA数字时钟 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 【精品文档】【精品文档】【精品文档】【精品文档】【精品文档】【精品文档】Quartus数字时钟设计设计功能可以快速设置时钟起始值；在59分50秒时开始报时，七声低音，一声高音，报完刚好整点。1.顶层设计（采用BDF文件图形设计，文件名：timer.bdf）秒计时器模块设计libraryieee;useieee.std_logic_1164.all;ith.all;useieee.std_logic_unsigned.all;entitysecond1isport(clk1s:instd_logic;reset:instd_logic;sec2,sec1:bufferstd_logic_vector(3downto0);--秒的十位和个位seco:outstd_logic);--秒计时器的进位输出end;architectureAofsecond1isbeginprocess(clk1s,reset)beginifreset='0'thensec2<="0000";sec1<="0000";--清零秒计时器seco<='0';elsifclk1s'eventandclk1s='1'thenif(sec1="1001"andsec2="0101")thensec2<="0000";sec1<="0000";--在59秒时回零seco<='1';--进位elsif(sec1="1001")thensec1<="0000";sec2<=sec2+1;seco<='0';elsesec1<=sec1+1;seco<='0';endif;endif;endprocess;end;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityminute1isport(clkm,clk1s,setm:instd_logic;--秒进位输入，1HZ校分时钟输入信号，校分控制信号min2,min1:bufferstd_logic_vector(3downto0);--分计时器的十位和个位minco:outstd_logic);end;architectureAofminute1issignalclkx:std_logic;beginPclkm:process(clkm,clk1s,setm)begin--根据是否校分选择计时时钟ifsetm='1'thenclkx<=clk1s;--利用clk1s信号对分的初值进行快速设置elseclkx<=clkm;--利用秒的进位信号正常计时endif;endprocess;Pcontm:process(clkx)beginifclkx'eventandclkx='1'thenif(min1="1001"andmin2="0101")thenmin1<="0000";min2<="0000";minco<='1';--59分时回零并进位elsif(min1="1001")thenmin1<="0000";min2<=min2+1;minco<='0';elsemin1<=min1+1;minco<='0';endif;endif;endprocess;end;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityhour1isport(clkh,clk1s,seth:instd_logic;hou2,hou1:bufferstd_logic_vector(3downto0));--时的十位和个位end;architectureAofhour1issignalclky:std_logic;beginPclkh:process(clkh,clk1s,seth)Begin--根据是否校时选择计时时钟ifseth='1'thenclky<=clk1s;--利用clk1s信号对时的初值进行快速设置elseclky<=clkh;--利用分的进位信号正常计时endif;endprocess;Pconth:process(clky)beginifclky'eventandclky='1'thenif(hou1="0011"andhou2="0010")thenhou1<="0000";hou2<="0000";--23时回零elsif(hou1="1001")thenhou1<="0000";hou2<=hou2+1;elsehou1<=hou1+1;endif;endif;endprocess;end;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityalarm1isport(clk1s,clk500,clk1k:instd_logic;sec2,sec1,min2,min1:instd_logic_vector(3downto0);alarm:outstd_logic);end;architectureAofalarm1isbeginprocess(clk1s)variableflag500:std_logic;variableflag1k:std_logic;beginifclk1s'eventandclk1s='1'thenif(min1="1001"andmin2="0101"andsec2="0101")then--59分50秒时开始报时casesec1iswhen"0000"=>flag500:='1';when"0010"=>flag500:='1';when"0100"=>flag500:='1';when"0110"=>flag500:='1';when"0111"=>flag500:='1';when"1000"=>flag500:='1';when"1001"=>flag500:='1';--50,52,54,56,58,59秒时低频率报时whenothers=>flag500:='0';flag1k:='0';endcase;elseflag500:='0';flag1k:='0';endif;if(min1="0000"andmin2="0000"andsec1="0000"andsec2="0000")thenflag1k:='1';--整点时高频率报时endif;endif;ifflag500='1'thenalarm<=clk500;elsifflag1k='1'thenalarm<=clk1k;elsealarm<='0';endif;endprocess;end;秒计时器仿真结果分计时器仿真结果时计时器仿真结果报时模块仿真结果1.仿真结果中，由于输出信号向量（比如sec1(0),sec1(1),sec1(2),sec1(3)）变化的不同时，使得组合后的sec1，sec2，min1，min2均出现毛刺，尝试了引入中间变量，中间信号的方法，都不能解决问题。怎么办才好？