上升沿触发的D触发器有一个数据输入端D，时钟输入端CLK，数据输出端Q,
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1是它的真值表。表1D触发器真值表数据输入D时钟输入CLK［数据输出QX0:不变X1不变0上升沿「°1上升沿1libraryieee;useieee.std」ogic_1164.AII;entitydailinisport(clk,d:instd_logic;q:outstd」ogic);end;architecturebhvofdailinissignalqq:std_logic;beginprocess(clk)beginifclk'eventandclk='1thenqq<=d;endif;endprocess;q<=qq;end;JK触发器的种类很多，可以从不同的真值表，写出不同的JK触发器的设计程序。在此设计一个通用的JK触发器，表2是它的真值表。表2JK触发器真值表输入端输出端PSETCLRCLKJKQ/Q°1XXX1°1°XXX°1°°XXXXX11上升沿°1°111上升沿11翻转翻转11上升沿:°°不变不变11上升沿1°1°libraryieee;useieee.std_logic_1164.all;entitydaiisport(j,k,clk:instd_logic;q,qn:outstd」ogic);enddai;architecturebehavofdaiissignalq_temp:instd_logic;signaljk:std_logic_vector(1downto0);beginjk<=j&k;process(jk,clk)beginifclk'eventandclk='0'thencasejkiswhen"00"=>q_temp<=q_temp;when"01"=>q_temp<='0';when"10"=>q_temp<='1';when"11"=>q_temp<=notq_temp;whenothers=>q_temp<=null;endcase;q<=q_temp;qn<=notq_temp;endif;endprocess;endbehav;在D触发器和JK触发器的基础上设计其他类型的触发器，如T触发器，带异步复位、置位的D触发器。T触发器的条件为：T=1时，q<=notq，在时钟上升沿赋值。T=0时，q<=q,在时钟上升沿赋值。libraryieee;useieee.std_logic_1164.all;entitydaiisport(t,clk:instd_logic;q,qn:outstd_logic);enddai;architecturebehavofdaiissignalq_temp:std_logic;--signaljk:std_logic_vector(1downto0);beginprocess(t,clk)beginifclk'eventandclk='1'thencasetiswhen'0'=>q_temp<=q_temp;when'1'=>q_temp<=notq_temp;whenothers=>q_temp<=null;endcase;q<=q_temp;qn<=notq_temp;endif;endprocess;endbehav;带异步复位/置位的D触发器真值表如表3所示。CLRPSETDCLKQ0XXX010XX1110上升沿0111上升沿1111X0不变11X1不变libraryieee;useieee.std_logic_1164.AII;entitydaiisport(clc,pset,clk,d:instd_logic;q:outstd」ogic);end;architecturebhvofdaiissignalqq:std_logic;beginprocess(clc,pset,clk)beginifclc='0'thenqq<='0：elsifpset='0'thenqq<='1：elsifclk'eventandclk='1'thenqq<=d;endif;--endif;--endif;endprocess;q<=qq;endbhv;
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