ADC0804(1)

ADC0804(1) November 1999 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters n Differential analog voltage inputs General Description supply n Logic inputs and outputs meet both MOS and TTL The ADC0801, ADC0802, ADC0803, ADC0804 and voltage level specifications ADC0805 are CMOS 8-bit successive approximation A/D n Works with 2.5V (LM336) voltage reference converters that use a differential potentiometric n On-chip clock generator ladder — similar to the 256R products. These converters are n 0V to 5V analog input voltage range with single 5V designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI-STATE ? output latches di- n No zero adjust required rectly driving the data bus. These A/Ds appear like memory locations or I/O ports to the microprocessor and no interfac- n 0.3" standard width 20-pin DIP package ing logic is needed. n 20-pin molded chip carrier or small outline package 8 bits Differential analog voltage inputs allow increasing the n Operates ratiometrically or with 5 VDC, 2.5 VDC, or common-mode rejection and offsetting the analog zero input analog span adjusted voltage reference voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span Key Specifications to the full 8 bits of resolution. n Resolution ? 1⁄4 LSB, ? 1⁄2 LSB and ?1 LSB n Total error Features 100 µs n Conversion time n Compatible with 8080 µP derivatives — no interfacing logic needed - access time - 135 ns n Easy interface to all microprocessors, or operates ―stand alone‖ Connection Diagram ADC080X Dual-In-Line and Small Outline (SO) Packages A DS005671-30 See Ordering Information Ordering Information TEMP RANGE 0?C TO 70?C 0?C TO 70?C ?40?C TO +85?C ? 1⁄4 Bit Adjusted ADC0801LCN ERROR ? 1⁄2 Bit Unadjusted ADC0802LCWM ADC0802LCN ? 1⁄2 Bit Adjusted ADC0803LCN ?1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ PACKAGE OUTLINE M20B — Small N20A — Molded DIP Outline TRI-STATE? is a registered trademark of National Semiconductor Corp. Z-80? is a registered trademark of Zilog Corp. ? 1999 National Semiconductor Corporation DS005671 www.national.com D Typical Applications A DS005671-1 8080 Interface DS005671-31 D Error Specification (Includes Full-Scale, Zero Error, and Non-Linearity) Part Full- VREF/2=2.500 VDC REF/2=No Connection V Number Scale (No Adjustments) (No Adjustments) Adjusted ADC0801 ? 1⁄4 LSB ADC0802 ? 1⁄2 LSB ADC0803 ? 1⁄2 LSB ?1 LSB ADC0804 ADC0805 ?1 LSB C0 2 www.national.com 80 800V 6.5V Infrared (15 seconds) 220?C Absolute Maximum Ratings (Notes 1, 2) Storage Temperature Range ?65?C to +150?C If Military/Aerospace specified devices are required, 875 mW Package Dissipation at TA=25?C please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Susceptibility (Note 10) Supply Voltage (VCC) (Note 3) Operating Ratings (Notes 1, 2) Voltage Logic Control Inputs ?0.3V to +18V Temperature Range TMIN,,A,,MAX At Other Input and Outputs ?0.3V to (VCC+0.3V) ADC0804LCJ ?40?C?TA,，,,,, Lead Temp. (Soldering, 10 seconds) ADC0801/02/03/05LCN ?40?C?TA,，,,,, Dual-In-Line Package (plastic) 260?C ADC0804LCN 0?C?TA,，,,,, A300?C Dual-In-Line Package (ceramic) ADC0802/04LCWM 0?C?TA,，,,,, Surface Mount Package CC Range of V 4.5 VDC to 6.3 VDC 215?C Vapor Phase (60 seconds) Electrical Characteristics The following specifications apply for VCC=5 VDC, TMIN,,A,,MAX and fCLK=640 kHz unless otherwise specified. Parameter Conditions Min Typ Max Units ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj. ? 1⁄4 LSB (See Section 2.5.2) ADC0802: Total Unadjusted Error (Note 8) ?? 11⁄2 LSB VREF/2=2.500 VDC ADC0803: Total Adjusted Error (Note 8) LSB ? 1⁄2 With Full-Scale Adj. (See Section 2.5.2) ADC0804: Total Unadjusted Error (Note 8) ?1 LSB VREF/2=2.500 VDC ADC0805: Total Unadjusted Error (Note 8) LSB VREF/2-No Connection ADC0801/02/03/05 2.5 8.0 k? VREF/2 Input Resistance (Pin 9) ADC0804 (Note 9) 0.75 1.1 k? DAnalog Input Voltage Range (Note 4) V(+) or V(?) Gnd–0.05 CC+0.05 VDC V DC Common-Mode Error Over Analog Input Voltage ?1/16 ? 1⁄8 LSB Range Power Supply Sensitivity ?1/16 ? 1⁄8 LSB VCC=5 VDC ?10% Over Allowed VIN(+) and VIN(?) Voltage Range (Note 4) AC Electrical Characteristics The following specifications apply for VCC=5 VDC and TMIN,,A,,MAX unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units Conversion Time 103 114 µs TC fCLK=640 kHz (Note 6) Conversion Time 66 73 (Notes 5, 6) CLK 1/fTC Clock Frequency 100 1460 kHz 640 VCC=5V, (Note 5) fCLK Clock Duty Cycle 40 60 % CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s C0Mode CS =0 VDC, fCLK=640 kHz Width of WR Input (Start Pulse Width) 100 ns tW(WR)L CS =0 VDC (Note 7) Access Time (Delay from Falling 135 200 ns tACC CL=100 pF Edge of RD to Output Data Valid) TRI-STATE Control (Delay 125 200 ns t1H, t0H CL=10 pF, RL=10k from Rising Edge of RD to (See TRI-STATE Test Hi-Z State) Circuits) Delay from Falling Edge 300 450 ns tWI, tRI of WR or RD to Reset of INTR 3 Input Capacitance of Logic 5 7.5 pF CIN Control Inputs www.national.com 80 (Continued) AC Electrical Characteristics The following specifications apply for VCC=5 VDC and TMIN,,A,,MAX unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units TRI-STATE Output 5 7.5 pF COUT Capacitance (Data Buffers) CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] 1 Logical ―1‖ Input Voltage 2.0 15 VIN (1) VCC=5.25 VDC VDC (Except Pin 4 CLK IN) Logical ―0‖ Input Voltage 0.8 VIN (0) VCC=4.75 VDC VDC A(Except Pin 4 CLK IN) Logical ―1‖ Input Current 0.005 IIN (1) VIN=5 VDC µADC (All Inputs) Logical ―0‖ Input Current ?1 ?0.005 IIN (0) VIN=0 VDC µADC (All Inputs) CLOCK IN AND CLOCK R CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 VT+ VDC Threshold Voltage CLK IN (Pin 4) Negative 1.5 1.8 2.1 VT? VDC Going Threshold Voltage CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 VH VDC (VT+)?(VT?) Logical ―0‖ CLK R Output 0.4 VOUT (0) IO=360 µA VDC Voltage VCC=4.75 VDC Logical ―1‖ CLK R Output 2.4 VOUT (1) IO=?360 µA VDC Voltage DVCC=4.75 VDC DATA OUTPUTS AND INTR Logical ―0‖ Output Voltage VOUT (0) Data Outputs 0.4 IOUT=1.6 mA, VCC=4.75 VDC VDC 3 INTR Output 0.4 IOUT=1.0 mA, VCC=4.75 VDC VDC Logical ―1‖ Output Voltage 2.4 VOUT (1) IO=?360 µA, VCC=4.75 VDC VDC Logical ―1‖ Output Voltage 4.5 VOUT (1) IO=?10 µA, VCC=4.75 VDC VDC TRI-STATE Disabled Output ?3 IOUT VOUT=0 VDC µADC Leakage (All Data Buffers) ICC VOUT=5 VDC µADC 4.5 6 ISOURCE VOUT Short to Gnd, TA=25?C mADC 9.0 16 ISINK VOUT Short to VCC, TA=25?C mADC POWER SUPPLY Supply Current (Includes fCLK=640 kHz, Ladder Current) VREF/2=NC, TA=25?C and CS =5V ADC0801/02/03/04LCJ/05 1.1 1.8 mA C0ADC0804LCN/LCWM 1.9 2.5 mA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd. Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC. Note 4: For VIN(?)? VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex- 4 tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns. Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see Figure 4 and section 2.0. www.national.com 80 (Continued) AC Electrical Characteristics Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams). Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7. Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 k?. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 k?. Note 10: Human body model, 100 pF discharged through a 1.5 k? resistor. Typical Performance Characteristics ALogic Input Threshold Voltage Delay From Falling Edge of CLK IN Schmitt Trip Levels vs. Supply Voltage RD to Output Data Valid vs. Supply Voltage vs. Load Capacitance DS005671-38 DS005671-40 DS005671-39 Effect of Unadjusted Offset Error Full-Scale Error vs fCLK vs. Clock Capacitor Conversion Time vs. VREF/2 Voltage D DS005671-41 DS005671-43 DS005671-42 Output Current vs Linearity Error at Low Power Supply Current Temperature vs Temperature (Note 9) VREF/2 Voltages C0 DS005671-46 DS005671-44 DS005671-45 5 www.national.com 80 TRI-STATE Test Circuits and Waveforms t1H, CL=10 pF t1H ADS005671-48 DS005671-47 tr = 20 ns t0H t0HL, C=10 pF DS005671-50 DS005671-49 tr = 20 ns Timing Diagrams (All timing is measured from the 50% voltage points) D DS005671-51 C0 6 www.national.com 80 (All timing is measured from the 50% voltage points) (Continued) Timing Diagrams Output Enable and Reset with INTR A DS005671-52 Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR . Typical Applications 6800 Interface Ratiometeric with Full-Scale Adjust D DS005671-53 DS005671-54 Note: before using caps at VIN or VREF/2, see section 2.3.2 Input Bypass Capacitors. C0 7 www.national.com 80 (Continued) Typical Applications Absolute with a 2.500V Reference Absolute with a 5V Reference A DS005671-56 DS005671-55 *For low power, see also LM385–2.5 Zero-Shift and Span Adjust: 2V , VIN , 5V Span Adjust: 0V , VIN , 3V D DS005671-58 DS005671-57 C0 8 www.national.com 80 (Continued) Typical Applications Directly Converting a Low-Level Signal A µP Interfaced Comparator A DS005671-60 For: VIN(+)> VIN(?) Output = FFHEX For: VIN(+)< VIN(?) Output = 00HEX DS005671-59 VREF/2 = 256 mV 1 mV Resolution with µP Controlled Range D DS005671-61 VREF/2 = 128 mV 1 LSB = 1 mV VDAC,,IN,，,DAC+256 mV) 0 , VDAC < 2.5V C0 9 www.national.com 80 (Continued) Typical Applications Digitizing a Current Flow A DS005671-62 Self-Clocking Multiple A/Ds External Clocking D DS005671-64 100 kHz?fCLK,,,,, kHz DS005671-63 * Use a large R value to reduce loading at CLK R output. C0 www.national.com 10 80 (Continued) Typical Applications Self-Clocking in Free-Running Mode µP Interface for Free-Running A/D A DS005671-65 *After power-up, a momentary grounding of the WR input is needed to guarantee operation. DS005671-66 Operating with “Automotive” Ratiometric Transducers Ratiometric with VREF/2 Forced D DS005671-68 DS005671-67 *VIN(?) = 0.15 VCC 15% of VCC,,XDR,,,, of VCC µP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis) C0 DS005671-69 *See Figure 5 to select R value DB7 = ―1‖ for VIN(+)> VIN(?)+(VREF/2) Omit circuitry within the dotted area if hysteresis is not needed 11 www.national.com 80 (Continued) Typical Applications Handling ?10V Analog Inputs Low-Cost, µP Interfaced, Temperature-to-Digital Converter A DS005671-70 DS005671-71 *Beckman Instruments #694-3-R10K resistor array µP Interfaced Temperature-to-Digital Converter D DS005671-72 *Circuit values shown are for 0?C?TA,，,,,,, ***Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage. C0 www.national.com 12 80 (Continued) Typical Applications Handling ?5V Analog Inputs Read-Only Interface A DS005671-34 DS005671-33 *Beckman Instruments #694-3-R10K resistor array µP Interfaced Comparator with Hysteresis Protecting the Input D DS005671-9 Diodes are 1N914 C0DS005671-35 13 www.national.com 80 (Continued) Typical Applications Analog Self-Test for a System A DS005671-36 A Low-Cost, 3-Decade Logarithmic Converter D C0 DS005671-37 *LM389 transistors A, B, C, D = LM324A quad op amp www.national.com 14 80 (Continued) Typical Applications 3-Decade Logarithmic A/D Converter A DS005671-73 Noise Filtering the Analog Input Multiplexing Differential Inputs D DS005671-74 DS005671-75 fC = 20 Hz Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order, low-pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Increasing Bus Drive and/or Reducing Time on Bus Output Buffers with A/D Data Enabled C0 DS005671-77 DS005671-76 *Allows output data to set-up at falling edge of CS *A/D output data is updated 1 CLK period prior to assertion of INTR 15 www.national.com 80 (Continued) Typical Applications Sampling an AC Input Signal A DS005671-78 Note 11: Oversample whenever possible [keep fs > 2f(?60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter. Note 12: Consider the amplitude errors which are introduced within the passband of the filter. 70% Power Savings by Clock Gating DS005671-79 D(Complete shutdown takes , 30 seconds.) Power Savings by A/D and VREF Shutdown C0 DS005671-80 *Use ADC0801, 02, 03 or 05 for lowest power consumption. Note: Logic inputs can be driven to VCC with A/D supply at zero volts. Buffer prevents data bus from overdriving output of A/D when in shutdown mode. (A?1, A, A+1, . . . . ) analog inputs produce the correct out- Functional Description put digital codes, but also each riser (the transitions between adjacent output codes) will be located ? 1⁄2 LSB away from 1.0 UNDERSTANDING A/D ERROR SPECS each center-value. As shown, the risers are ideal and have A perfect A/D transfer characteristic (staircase waveform) is no width. Correct digital output codes will be provided for a shown in Figure 1. The horizontal scale is analog input volt- range of analog input voltages that extend ? 1⁄2 LSB from the age and the particular points labeled are in steps of 1 LSB ideal center-values. Each tread (the range of analog input (19.53 mV with 2.5V tied to the VREF/2 pin). The digital out- voltage that provides the same digital output code) is there- put codes that correspond to these inputs are shown as D?1, fore 1 LSB wide.D, and D+1. For the perfect A/D, not only will center-value www.national.com 16 80 Next to each transfer function is shown the corresponding (Continued) Functional Description error plot. Many people may be more familiar with error plots Figure 2 shows a worst case error plot for the ADC0801. All than transfer functions. The analog input voltage to the A/D center-valued inputs are guaranteed to produce the correct is provided by either a linear ramp or by the discrete output output codes and the adjacent risers are guaranteed to be steps of a high resolution DAC. Notice that the error is con- no closer to the center-value points than ? 1⁄4 LSB. In other tinuously displayed and includes the quantization uncertainty words, if we apply an analog input equal to the center-value Figure 1 is +1⁄2 of the A/D. For example the error at point 1 of? 1⁄4 LSB, we guarantee that the A/D will produce the correct LSB because the digital code appeared 1⁄2 LSB in advance digital code. The maximum range of the position of the code of the center-value of the tread. The error plots always have transition is indicated by the horizontal arrow and it is guar- a constant negative slope and the abrupt upside steps are anteed to be no more than 1⁄2 LSB. always 1 LSB in magnitude. The error curve of Figure 3 shows a worst case error plot for Athe ADC0802. Here we guarantee that if we apply an analog input equal to the LSB analog voltage center-value the A/D will produce the correct digital code. Transfer Function Error Plot DS005671-81 DS005671-82 DFIGURE 1. Clarifying the Error Specs of an A/D Converter Accuracy= ?0 LSB: A Perfect A/D Transfer Function Error Plot DS005671-83 DS005671-84 FIGURE 2. Clarifying the Error Specs of an A/D Converter Accuracy= ? 1⁄4 LSB C0 17 www.national.com 80 (Continued) Functional Description Error Plot Transfer Function A DS005671-85 DS005671-86 FIGURE 3. Clarifying the Error Specs of an A/D Converter Accuracy= ? 1⁄2 LSB 2.0 FUNCTIONAL DESCRIPTION A functional diagram of the A/D converter is shown in Figure 4. All of the package pinouts are shown and the major logic The ADC0801 series contains a circuit equivalent of the control paths are drawn in heavier weight lines. 256R network. Analog switches are sequenced by succes- The converter is started by having CS and WR simulta- sive approximation logic to match the analog difference input neously low. This sets the start flip-flop (F/F) and the result- voltage [VIN(+) ? VIN(?)] to a corresponding tap on the R net- ing ―1‖ level resets the 8-bit shift register, resets the Interrupt work. The most significant bit is tested first and after 8 com- parisons (64 clock cycles) a digital 8-bit binary code (1111 (INTR) F/F and inputs a ―1‖ to the D flop, F/F1, which is at the 1111 = full-scale) is transferred to an output latch and then input end of the 8-bit shift register. Internal clock signals then an interrupt is asserted (INTR makes a high-to-low transi- transfer this ―1‖ to the Q output of F/F1. The AND gate, G1, cycle. combines this ―1‖ output with a clock signal to provide a reset tion). A conversion in process can be interrupted by issuing a second start command. The device may be operated in the signal to the start F/F. If the set signal is no longer present free-running mode by connecting INTR to the WR input with (either WR or CS is a ―1‖) the start F/F is reset and the 8-bit D CS =0. To ensure start-up under all possible conditions, an shift register then can have the ―1‖ clocked in, which starts external WR pulse is required during the first power-up the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would momentarily be at a ―1‖ level) and the On the high-to-low transition of the WR input the internal 8-bit shift register would continue to be held in the reset SAR latches and the shift register stages are reset. As long mode. This logic therefore allows for wide CS and WR sig- as the CS input and WR input remain low, the A/D will remain nals and the converter will start after at least one of these in a reset state. Conversion will start from 1 to 8 clock peri- signals returns high and the internal clocks again provide a ods after at least one of these inputs makes a low-to-high transition. reset signal for the start F/F. C0 www.national.com 18 80 (Continued) Functional Description A D DS005671-13 Note 13: CS shown twice for clarity. Note 14: SAR = Successive Approximation Register. FIGURE 4. Block Diagram After the ―1‖ is clocked through the 8-bit shift register (which which causes the input to the D-type latch, LATCH 1, to go completes the SAR search) it appears as the input to the low. As the latch enable input is still present, the Q output will D-type latch, LATCH 1. As soon as this ―1‖ is output from the go high, which then allows the INTR F/F to be RESET. This shift register, the AND gate, G2, causes the new digital word reduces the width of the resulting INTR output pulse to only to transfer to the TRI-STATE output latches. When LATCH 1 a few propagation delays (approximately 300 ns). is subsequently enabled, the Q output makes a high-to-low When data is to be read, the combination of both CS and RD transition which causes the INTR F/F to set. An inverting being low will cause the INTR F/F to be reset and the buffer then supplies the INTR input signal. TRI-STATE output latches will be enabled to provide the 8-bit Note that this SET control of the INTR F/F remains low for 8 digital outputs. C0 of the external clock periods (as the internal clocks run at 1⁄8 of the frequency of the external clock). If the data output is 2.1 Digital Control Inputs continuously enabled (CS and RD both held low), the INTR The digital control inputs (CS, RD, and WR) meet standard output will still signal the end of conversion (by a high-to-low T2L logic voltage levels. These signals have been renamed transition), because the SET input can control the Q output when compared to the standard A/D Start and Output Enable of the INTR F/F even though the RESET input is constantly labels. In addition, these inputs are active low to allow an at a ―1‖ level in this operating mode. This INTR output will easy interface to microprocessor control busses. For therefore stay low for the duration of the SET signal, which is non-microprocessor based applications, the CS input (pin 1) 8 periods of the external clock frequency (assuming the A/D can be grounded and the standard A/D Start function is ob- is not started during this interval). tained by an active low pulse applied at the WR input (pin 3) When operating in the free-running or continuous conversion and the Output Enable function is caused by an active low pulse at the RD input (pin 2). mode (INTR pin tied to WR and CS wired low — see also section 2.8), the START F/F is SET by the high-to-low tran- sition of the INTR signal. This resets the SHIFT REGISTER www.national.com19 80 (Continued) Functional Description 2.2 Analog Differential Voltage Inputs and Common-Mode Rejection This A/D has additional applications flexibility due to the ana- log differential voltage input. The VIN(?) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also useful in 4 mA–20 mA current loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling VININ1⁄2 (+) and V(?) is 4-Aclock periods. The maximum error voltage due to this slight time difference between the input voltage samples is given DS005671-14 by: rON of SW 1 and SW 2 , 5 k? r = rON CSTRAY , 5 k? x 12 pF = 60 ns FIGURE 5. Analog Input Impedance The voltage on this capacitance is switched and will result in where: currents entering the VIN(+) input pin and leaving the VIN(?) ?,e is the error voltage due to sampling delay input which will depend on the analog differential input volt- VP is the peak value of the common-mode voltage age levels. These current transients occur at the leading fcm is the common-mode frequency edge of the internal clocks. They rapidly decay and do not cause errorsAs an example, to keep this error to 1⁄4 LSB (?5 mV) when as the on-chip comparator is strobed at the end of the clock period. operating with a 60 Hz common-mode frequency, fcm, and using a 640 kHz A/D clock, fCLK, would allow a peak value of or Fault Mode the common-mode voltage, VP, which is given by: If the voltage source applied to the VIN(+) or VIN(?) pin ex- ceeds the allowed operating range of VCC+50 mV, large in- put currents can flow through a parasitic diode to the VCC pin. If these currents can exceed the 1 mA max allowed spec, an external diode (1N914) should be added to bypass D this current to the VCC pin (with the current bypassed with this diode, the voltage at the VIN(+) pin can exceed the VCC voltage by the forward voltage of this diode). els. which gives 2.3.2 Input Bypass Capacitors VP,1.9V. Bypass capacitors at the inputs will average these charges The allowed range of analog input voltages usually places and cause a DC current to flow through the output resis- more severe restrictions on input common-mode noise lev- tances of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) in- An analog input voltage with a reduced span and a relatively put voltage at full-scale. For continuous conversions with a large zero offset can be handled easily by making use of the 640 kHz clock frequency with the VIN(+) input at 5V, this DC differential input (see section 2.4 Reference Voltage). current is at a maximum of approximately 5 µA. Therefore, bypass capacitors should not be used at the analog inputs or the V2.3 Analog Inputs REF/2 pin for high resistance sources (> 1 k?). If input bypass capacitors are necessary for noise filtering and high 2.3 1 Input Current source resistance is desirable to minimize capacitor size, the detrimental effects of the voltage drop across this input resis- Normal Mode tance, which is due to the average value of the input current, can be eliminated with a full-scale adjustment while the Due to the internal switching action, displacement currents given source resistor and input bypass capacitor are both in will flow at the analog inputs. This is due to on-chip stray ca- C0place. This is possible because the average value of the in- pacitance to ground as shown in Figure 5. put current is a precise linear function of the differential input voltage. 2.3.3 Input Source Resistance Large values of source resistance where an input bypass ca- pacitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued series resistor (? 1 k?) for a passive RC section or add an op amp RC ac- tive low pass filter. For low source resistance applications, (? 1 k?), a 0.1 µF bypass capacitor at the inputs will prevent noise pickup due to series lead inductance of a long wire. A www.national.com 20 80 (Continued) Notice that the reference voltage for the IC is either 1⁄2 of the Functional Description voltage applied to the VCC supply pin, or is equal to the volt- 100? series resistor can be used to isolate this age that is externally forced at the VREF/2 pin. This allows for capacitor — both the R and C are placed outside the feed- a ratiometric voltage reference using the VCC supply, a 5 back loop — from the output of an op amp, if used. VDCCC reference voltage can be used for the V supply or a voltage less than 2.5 VDCREF can be applied to the V/2 input 2.3.4 Noise for increased application flexibility. The internal gain to the The leads to the analog inputs (pins 6 and 7) should be kept VREF/2 input is 2, making the full-scale differential input volt- as short as possible to minimize input noise coupling. Both age twice the voltage at pin 9. noise and undesired digital clock coupling to these inputs An example of the use of an adjusted reference voltage is to can cause system errors. The source resistance for these in- accommodate a reduced span — or dynamic voltage range puts should, in general, be kept below 5 k?. Larger values of Aof the analog input voltage. If the analog input voltage were source resistance can cause undesired system noise to range from 0.5 VDC to 3.5 VDC, instead of 0V to 5 VDC, the pickup. Input bypass capacitors, placed from the analog in- span would be 3V as shown in Figure 7. With 0.5 VDC ap- puts to ground, will eliminate system noise pickup but can plied to the VIN(?) pin to absorb the offset, the reference volt- create analog scale errors as these capacitors will average age can be made equal to 1⁄2 of the 3V span or 1.5 VDC. The the transient input switching currents of the A/D (see section A/D now will encode the VIN(+) signal from 0.5V to 3.5 V with 2.3.1.). This scale error depends on both a large source re- the 0.5V input corresponding to zero and the 3.5 VDC input sistance and the use of an input bypass capacitor. This error corresponding to full-scale. The full 8 bits of resolution are can be eliminated by doing a full-scale adjustment of the A/D therefore applied over this reduced analog input voltage (adjust VREF/2 for a proper full-scale reading — see section range. 2.5.2 on Full-Scale Adjustment) with the source resistance and input bypass capacitor in place. 2.4.2 Reference Accuracy Requirements The converter can be operated in a ratiometric mode or an 2.4 Reference Voltage absolute mode. In ratiometric converter applications, the magnitude of the reference voltage is a factor in both the out- 2.4.1 Span Adjust put of the source transducer and the output of the A/D con- For maximum applications flexibility, these A/Ds have been verter and therefore cancels out in the final digital output designed to accommodate a 5 VDC, 2.5 VDC or an adjusted code. The ADC0805 is specified particularly for use in ratio- voltage reference. This has been achieved in the design of metric applications with no adjustments required. In absolute the IC as shown in Figure 6. conversion applications, both the initial value and the tem- perature stability of the reference voltage are important fac- D tors in the accuracy of the A/D converter. For VREF/2 volt- ages of 2.4 VDC nominal value, initial errors of ?10 mVDC will cause conversion errors of ?1 LSB due to the gain of 2 of the VREF/2 input. In reduced span applications, the initial value and the stability of the VREF/2 input voltage become even more important. For example, if the span is reduced to 2.5V, the analog input LSB voltage value is correspondingly re- duced from 20 mV (5V span) to 10 mV and 1 LSB at the VREF/2 input becomes 5 mV. As can be seen, this reduces the allowed initial tolerance of the reference voltage and re- quires correspondingly less absolute change with tempera- ture variations. Note that spans smaller than 2.5V place even tighter requirements on the initial accuracy and stability of the reference source. In general, the magnitude of the reference voltage will re- quire an initial adjustment. Errors due to an improper value of reference voltage appear as full-scale errors in the A/D transfer function. IC voltage regulators may be used for ref- erences if the ambient temperature changes are not exces- sive. The LM336B 2.5V IC reference diode (from National C0 Semiconductor) has a temperature stability of 1.8 mV typ DS005671-15 (6 mV max) over 0?C?TA,，,,,,, Other temperature range FIGURE 6. The VREFERENCE Design on the IC parts are also available. www.national.com21 80 (Continued) Functional Description DS005671-87 a) Analog Input Signal Example A DS005671-88 *Add if VREF/2 , 1 VDC with LM358 to draw 3 mA to ground. b) Accommodating an Analog Input from 0.5V (Digital Out = 00HEX) to 3.5V (Digital Out=FFHEX) FIGURE 7. Adapting the A/D Analog Input Voltages to Match an Arbitrary Input Signal Range 2.5 Errors and Reference Voltage Adjustments is applied to pin 6 and the zero reference voltage at pin 7 Dshould then be adjusted to just obtain the 00HEX to 01HEX 2.5.1 Zero Error code transition. The zero of the A/D does not require adjustment. If the mini- The full-scale adjustment should then be made (with the mum analog input voltage value, VIN(MIN), is not ground, a proper VIN(?) voltage applied) by forcing a voltage to the zero offset can be done. The converter can be made to out- VIN(+) input which is given by: put 0000 0000 digital code for this minimum input voltage by biasing the A/D VIN(?) input at this VIN(MIN) value (see Appli- and cations section). This utilizes the differential mode operation of the A/D. where: The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by VMAX=The high end of the analog input range grounding the VIN (?) input and applying a small magnitude positive voltage to the VIN (+) input. Zero error is the differ- VMIN=the low end (the offset zero) of the analog range. ence between the actual DC input voltage that is necessary (Both are ground referenced.) to just cause an output digital code transition from 0000 0000 The VREF/2 (or VCC) voltage is then adjusted to provide a to 0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 9.8 mV code change from FEHEX to FFHEX. This completes the ad- for VREF/2=2.500 VDC). justment procedure. 2.5.2 Full-Scale 2.6 Clocking Option The full-scale adjustment can be made by applying a differ- The clock for the A/D can be derived from the CPU clock or C0ential input voltage that is 11⁄2 LSB less than the desired ana- an external RC can be added to provide self-clocking. The log full-scale voltage range and then adjusting the magni- CLK IN (pin 4) makes use of a Schmitt trigger as shown in tude of the VREF/2 input (pin 9 or the VCC supply if pin 9 is Figure 8. not used) for a digital output code that is just changing from 1111 1110 to 1111 1111. 2.5.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal that does not go to ground) this new zero reference should be properly adjusted first. A VIN(+) voltage that equals this desired zero reference plus 1⁄2 LSB (where the LSB is calcu- lated for the desired analog span, 1 LSB=analog span/256) www.national.com 22 80 (low power Schottky such as the DM74LS240 series is rec- (Continued) Functional Description ommended) or special higher drive current products which are designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended. 2.10 Power Supplies Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A low in- ductance tantalum filter capacitor should be used close to the converter VCC pin and values of 1 µF or greater are rec- ommended. If an unregulated voltage is available in the sys- tem, a separate LM340LAZ-5.0, TO-92, 5V voltage regulator Afor the converter (and other analog circuitry) will greatly re- DS005671-17 duce digital noise on the VCC supply. 2.11 Wiring and Hook-Up Precautions Standard digital wire wrap sockets are not satisfactory for breadboarding this A/D converter. Sockets on PC boards can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the analog FIGURE 8. Self-Clocking the A/D signal leads. Exposed leads to the analog inputs can cause Heavy capacitive or DC loading of the clock R pin should be undesired digital noise and hum pickup, therefore shielded avoided as this will disturb normal converter operation. leads may be necessary in many applications. Loads less than 50 pF, such as driving up to 7 A/D converter A single point analog ground that is separate from the logic clock inputs from a single clock R pin of 1 converter, are al- ground points should be used. The power supply bypass ca- lowed. For larger clock line loading, a CMOS or low power pacitor and the self-clocking capacitor (if used) should both TTL buffer or PNP input logic should be used to minimize the be returned to digital ground. Any VREF/2 bypass capacitors, loading on the clock R pin (do not use a standard TTL analog input filter capacitors, or input signal shielding should buffer). be returned to the analog ground point. A test for proper grounding is to measure the zero error of the A/D converter. 2.7 Restart During a Conversion Zero errors in excess of 1⁄4 LSB can usually be traced to im- If the A/D is restarted (CS and WR go low and return high) proper board layout and wiring (see section 2.5.1 for mea- Dduring a conversion, the converter is reset and a new con- suring the zero error). version is started. The output data latch is not updated if the conversion in process is not allowed to be completed, there- 3.0 TESTING THE A/D CONVERTER fore the data of the previous conversion remains in this latch. There are many degrees of complexity associated with test- The INTR output simply remains at the ―1‖ level. ing an A/D converter. One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to 2.8 Continuous Conversions display the resulting digital output code as shown in Figure 9. For operation in the free-running mode an initializing pulse For ease of testing, the VREF/2 (pin 9) should be supplied should be used, following power-up, to ensure circuit opera- with 2.560 VDC and a VCC supply voltage of 5.12 VDC should tion. In this application, the CS input is grounded and the WR be used. This provides an LSB value of 20 mV. input is tied to the INTR output. This WR and INTR node If a full-scale adjustment is to be made, an analog input volt- should be momentarily forced to logic low following a age of 5.090 VDC (5.120–11⁄2 LSB) should be applied to the power-up cycle to guarantee operation. VIN(+) pin with the VIN(?) pin grounded. The value of the VREF/2 input voltage should then be adjusted until the digital 2.9 Driving the Data Bus output code is just changing from 1111 1110 to 1111 1111. This MOS A/D, like MOS microprocessors and memories, This value of VREF/2 should then be used for all the tests. will require a bus driver when the total capacitance of the The digital output LED display can be decoded by dividing data bus gets large. Other circuitry, which is tied to the data the 8 bits into 2 hex characters, the 4 most significant (MS) bus, will add to the total capacitive loading, even in and the 4 least significant (LS). Table 1 shows the fractional TRI-STATE (high impedance mode). Backplane bussing C0binary equivalent of these two 4-bit groups. By adding the also greatly adds to the stray capacitance of the data bus. voltages obtained from the ―VMS‖ and ―VLS‖ columns in There are some alternatives available to the designer to Table 1, the nominal value of the digital display (when handle this problem. Basically, the capacitive loading of the VREF/2 = 2.560V) can be determined. For example, for an data bus slows down the response time, even though DC output LED display of 1011 0110 or B6 (in hex), the voltage specifications are still met. For systems operating with a values from the table are 3.520 + 0.120 or 3.640 VDC. These relatively slow CPU clock frequency, more time is available voltage values represent the center-values of a perfect A/D in which to establish proper logic levels on the bus and there- converter. The effects of quantization error have to be ac- fore higher capacitive loads can be driven (see typical char- counted for in the interpretation of the test results. acteristics curves). At higher CPU clock frequencies time can be extended for I/O reads (and/or writes) by inserting wait states (8080) or using clock extending circuits (6800). Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be TRI-STATE buffers www.national.com23 80 For a higher speed test system, or to obtain plotted data, a (Continued) Functional Description digital-to-analog converter is needed for the test set-up. An accurate 10-bit DAC can serve as the precision voltage source for the A/D. Errors of the A/D under test can be ex- pressed as either analog voltages or differences in 2 digital words. A basic A/D tester that uses a DAC and provides the error as an analog output voltage is shown in Figure 8. The 2 op amps can be eliminated if a lab DVM with a numerical sub- traction feature is available to read the difference voltage, ―A–C‖, directly. The analog input voltage can be supplied by a low frequency ramp generator and an X-Y plotter can be Aused to provide analog error (Y axis) versus analog input (X axis). For operation with a microprocessor or a computer-based test system, it is more convenient to present the errors digi- tally. This can be done with the circuit of Figure 11, where the output code transitions can be detected as the 10-bit DAC is incremented. This provides 1⁄4 LSB steps for the 8-bit A/D un- der test. If the results of this test are automatically plotted with the analog input on the X axis and the error (in LSB’s) as the Y axis, a useful transfer function of the A/D under test results. For acceptance testing, the plot is not necessary and the testing speed can be increased by establishing internal DS005671-18 limits on the allowed error for each code. FIGURE 9. Basic A/D Tester 4.0 MICROPROCESSOR INTERFACING To dicuss the interface with 8080A and 6800 microproces- sors, a common sample subroutine structure is used. The microprocessor starts the A/D, reads and stores the results of 16 successive conversions, then returns to the user’s pro- gram. The 16 data bytes are stored in 16 successive Dmemory locations. All Data and Addresses will be given in hexadecimal form. Software and hardware details are pro- vided separately for each type of microprocessor. 4.1 Interfacing 8080 Microprocessor Derivatives (8048, 8085) This converter has been designed to directly interface with derivatives of the 8080 microprocessor. The A/D can be mapped into memory space (using standard memory ad- dress decoding for CS and the MEMR and MEMW strobes) or it can be controlled as an I/O device by using the I/O R and I/O W strobes and decoding the address bits A0 ? A7 (or address bits A8 ? A15 as they will contain the same 8-bit address information) to obtain the CS input. Using the I/O space provides 256 additional addresses and may allow a simpler 8-bit address decoder but the data can only be input to the accumulator. To make use of the additional memory reference instructions, the A/D should be mapped into memory space. An example of an A/D in I/O space is shown in Figure 12.C0 www.national.com 24 80 (Continued) Functional Description A DS005671-89 FIGURE 10. A/D Tester with Analog Error Output DS005671-90 FIGURE 11. Basic “Digital” A/D Tester TABLE 1. DECODING THE DIGITAL OUTPUT LEDs DOUTPUT VOLTAGE FRACTIONAL BINARY VALUE FOR CENTER VALUES HEX BINARY WITH VREF/2=2.560 VDC MS GROUP LS GROUP VMS VLS GROUP GROUP (Note 15) (Note 15) F 1 1 1 1 4.800 0.300 15/16 15/256 E 1 1 1 0 4.480 0.280 7/8 7/128 D 1 1 0 1 4.160 0.260 13/16 13/256 C 1 1 0 0 3.840 0.240 3/4 3/64 B 1 0 1 1 11/16 11/256 3.520 0.220 A 1 0 1 0 5/8 5/128 3.200 0.200 9/16 9/256 9 1 0 0 1 2.880 0.180 8 1 0 0 0 2.560 0.160 1/2 1/32 7/16 7/256 7 0 1 1 1 2.240 0.140 C03/8 3/128 6 0 1 1 0 1.920 0.120 5/16 2/256 5 0 1 0 1 1.600 0.100 4 0 1 0 0 1.280 0.080 1/4 1/64 3/16 3/256 3 0 0 1 1 0.960 0.060 1/8 1/128 2 0 0 1 0 0.640 0.040 1/16 1/256 1 0 0 0 1 0.320 0.020 0 0 0 0 0 0 0 Note 15: Display Output = VMS Group + VLS Group 25 www.national.com 80 (Continued) Functional Description A D DS005671-20 Note 16:*Pin numbers for the DP8228 system controller, others are INS8080A. Note 17: Pin 23 of the INS8228 must be tied to +12V through a 1 k? resistor to generate the RST 7 instruction when an interrupt is acknowledged as required by the accompanying sample program. FIGURE 12. ADC0801_INS8080A CPU Interface C0 www.national.com 26 80 (Continued) Functional Description SAMPLE PROGRAM FOR Figure 12 ADC0801–INS8080A CPU INTERFACE A DS005671-99 Note 18: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack. DNote 19: All address used were arbitrarily chosen. The standard control bus signals of the 8080 CS, RD and It is important to note that in systems where the A/D con- WR) can be directly wired to the digital control inputs of the verter is 1-of-8 or less I/O mapped devices, no address de- A/D and the bus timing requirements are met to allow both coding circuitry is necessary. Each of the 8 address bits (A0 starting the converter and outputting the data onto the data to A7) can be directly used as CS inputs — one for each I/O bus. A bus driver should be used for larger microprocessor device. systems where the data bus leaves the PC board and/or must drive capacitive loads larger than 100 pF. 4.1.2 INS8048 Interface The INS8048 interface technique with the ADC0801 series 4.1.1 Sample 8080A CPU Interfacing Circuitry and (see Figure 13) is simpler than the 8080A CPU interface. Program There are 24 I/O lines and three test input lines in the 8048. The following sample program and associated hardware With these extra I/O lines available, one of the I/O lines (bit shown in Figure 12 may be used to input data from the con- 0 of port 1) is used as the chip select signal to the A/D, thus verter to the INS8080A CPU chip set (comprised of the eliminating the use of an external address decoder. Bus con- below. INS8080A microprocessor, the INS8228 system controller trol signals RD, WR and INT of the 8048 are tied directly to and the INS8224 clock generator). For simplicity, the A/D is the A/D. The 16 converted data words are stored at on-chip controlled as an I/O device, specifically an 8-bit bi-directional RAM locations from 20 to 2F (Hex). The RD and WR signals port located at an arbitrarily chosen port address, E0. The are generated by reading from and writing into a dummy ad- TRI-STATE output capability of the A/D eliminates the need dress, respectively. A sample interface program is shown C0for a peripheral interface device, however address decoding is still required to generate the appropriate CS for the con- verter. www.national.com27 80 (Continued) Functional Description A DS005671-21 FIGURE 13. INS8048 Interface SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE D DS005671-A0 4.2 Interfacing the Z-80 C0 The Z-80 control bus is slightly different from that of the 8080. General RD and WR strobes are provided and sepa- rate memory request, MREQ, and I/O request, IORQ, sig- nals are used which have to be combined with the general- ized strobes to provide the equivalent 8080 signals. An advantage of operating the A/D in I/O space with the Z-80 is DS005671-23 that the CPU will automatically insert one wait state (the RD FIGURE 14. Mapping the A/D as an I/O Device and WR strobes are extended one clock period) to allow for Use with the Z-80 CPU more time for the I/O devices to respond. Logic to map the A/D in I/O space is shown in Figure 14. Additional I/O advantages exist as software DMA routines are available and use can be made of the output data trans- fer which exists on the upper 8 address lines (A8 to A15) dur- 28 www.national.com 80 ready memory mapped in the M6800 system and no CS de- (Continued) Functional Description coding is necessary. Also notice that the A/D output data ing I/O input instructions. For example, MUX channel selec- lines are connected to the microprocessor bus under pro- tion for the A/D can be accomplished with this operating gram control through the PIA and therefore the A/D RD pin mode. can be grounded. A sample interface program equivalent to the previous one is 4.3 Interfacing 6800 Microprocessor Derivatives Figure 16. The PIA Data and Control Registers shown below(6502, etc.) of Port B are located at HEX addresses 8006 and 8007, re- The control bus for the 6800 microprocessor derivatives spectively. does not use the RD and WR strobe signals. Instead it em- ploys a single R/W line and additional timing, if needed, can 5.0 GENERAL APPLICATIONS be derived fom the ,, clock. All I/O devices are memory The following applications show some interesting uses for Amapped in the 6800 system, and a special signal, VMA, indi- the A/D. The fact that one particular microprocessor is used cates that the current address is valid. Figure 15 shows an is not meant to be restrictive. Each of these application cir- interface schematic where the A/D is memory mapped in the cuits would have its counterpart using any microprocessor 6800 system. For simplicity, the CS decoding is shown using that is desired. 1⁄2 DM8092. Note that in many 6800 systems, an already de- coded 4/5 line is brought out to the common bus at pin 21. 5.1 Multiple ADC0801 Series to MC6800 CPU Interface This can be tied directly to the CS pin of the A/D, provided To transfer analog data from several channels to a single mi- that no other devices are addressed at HX ADDR: 4XXX or croprocessor system, a multiple converter scheme presents 5XXX. several advantages over the conventional multiplexer The following subroutine performs essentially the same func- single-converter approach. With the ADC0801 series, the dif- tion as in the case of the 8080A interface and it can be called ferential inputs allow individual span adjustment for each from anywhere in the user’s program. channel. Furthermore, all analog input channels are sensed In Figure 16 the ADC0801 series is interfaced to the M6800 simultaneously, which essentially divides the microproces- microprocessor through (the arbitrarily chosen) Port B of the sor’s total system servicing time by the number of channels, since all conversions occur simultaneously. This scheme is MC6820 or MC6821 Peripheral Interface Adapter, (PIA). shown in Figure 17. Here the CS pin of the A/D is grounded since the PIA is al- D C0 DS005671-24 Note 20: Numbers in parentheses refer to MC6800 CPU pin out. Note 21: Number or letters in brackets refer to standard M6800 system common bus code. FIGURE 15. ADC0801-MC6800 CPU Interface 29 www.national.com 80 (Continued) Functional Description SAMPLE PROGRAM FOR Figure 15 ADC0801-MC6800 CPU INTERFACE A DS005671-A1 DNote 22: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program. C0 DS005671-25 FIGURE 16. ADC0801–MC6820 PIA Interface www.national.com 30 80 (Continued) Functional Description SAMPLE PROGRAM FOR Figure 16 ADC0801–MC6820 PIA INTERFACE A D DS005671-A2 The following schematic and sample subroutine (DATA IN) CPU, starts all the converters simultaneously and waits for the interrupt signal. Upon receiving the interrupt, it reads the may be used to interface (up to) 8 ADC0801’s directly to the MC6800 CPU. This scheme can easily be extended to allow converters (from HEX addresses 5000 through 5007) and the interface of more converters. In this configuration the stores the data successively at (arbitrarily chosen) HEX ad- converters are (arbitrarily) located at HEX address 5000 in dresses 0200 to 0207, before returning to the user’s pro- the MC6800 memory space. To save components, the clock gram. All CPU registers then recover the original data they had before servicing DATA IN. signal is derived from just one RC pair on the first converter. This output drives the other A/Ds. 5.2 Auto-Zeroed Differential Transducer Amplifier All the converters are started simultaneously with a STORE and A/D Converter instruction at HEX address 5000. Note that any other HEX The differential inputs of the ADC0801 series eliminate the address of the form 5XXX will be decoded by the circuit, pull- need to perform a differential to single ended conversion for ing all the CS inputs low. This can easily be avoided by using a differential transducer. Thus, one op amp can be elimi- a more definitive address decoding scheme. All the inter- nated since the differential to single ended conversion is pro- rupts are ORed together to insure that all A/Ds have com- C0 vided by the differential input of the ADC0801 series. In gen- pleted their conversion before the microprocessor is inter- eral, a transducer preamp is required to take advantage of rupted. the full A/D converter input dynamic range. The subroutine, DATA IN, may be called from anywhere in the user’s program. Once called, this routine initializes the www.national.com31 80 (Continued) Functional Description A D DS005671-26 Note 23: Numbers in parentheses refer to MC6800 CPU pin out. Note 24: Numbers of letters in brackets refer to standard M6800 system common bus code. FIGURE 17. Interfacing Multiple A/Ds in an MC6800 System C0 www.national.com 32 80 (Continued) Functional Description SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM A DS005671-A3 SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM D DS005671-A4 Note 25: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program. For amplification of DC input signals, a major system error is where IX is the current through resistor RX. All of the offset the input offset voltage of the amplifiers used for the preamp. error terms can be cancelled by making ?IXRX= VOS1 + Figure 18 is a gain of 100 differential preamp whose offset VOS3 ? VOS2. This is the principle of this auto-zeroing voltage errors will be cancelled by a zeroing subroutine scheme. which is performed by the INS8080A microprocessor sys- The INS8080A uses the 3 I/O ports of an INS8255 Program- tem. The total allowable input offset voltage error for this able Peripheral Interface (PPI) to control the auto zeroing preamp is only 50 µV for 1⁄4 LSB error. This would obviously and input data from the ADC0801 as shown in Figure 19. require very precise amplifiers. The expression for the differ- The PPI is programmed for basic I/O operation (mode 0) with ential output voltage of the preamp is: Port A being an input port and Ports B and C being output ports. Two bits of Port C are used to alternately open or close C0the 2 switches at the input of the preamp. Switch SW1 is closed to force the preamp’s differential input to be zero dur- ing the zeroing subroutine and then opened and SW2 is then closed for conversion of the actual differential input signal. Using 2 switches in this manner eliminates concern for the ON resistance of the switches as they must conduct only the input bias current of the input amplifiers. Output Port B is used as a successive approximation regis- ter by the 8080 and the binary scaled resistors in series with each output bit create a D/A converter. During the zeroing subroutine, the voltage at Vx increases or decreases as re- quired to make the differential output voltage equal to zero. This is accomplished by ensuring that the voltage at the out- put of A1 is approximately 2.5V so that a logic ―1‖ (5V) on www.national.com33 80 the ADC0801. It is important that the voltage levels that drive (Continued) Functional Description the auto-zero resistors be constant. Also, for symmetry, a logic swing of 0V to 5V is convenient. To achieve this, a any output of Port B will source current into node VX thus CMOS buffer is used for the logic output signals of Port B raising the voltage at VX and making the output differential and this CMOS package is powered with a stable 5V source. more negative. Conversely, a logic ―0‖ (0V) will pull current Buffer amplifier A1 is necessary so that it can source or sink out of node VX and decrease the voltage, causing the differ- ential output to become more positive. For the resistor val- the D/A output current. ues shown, VX can move ?12 mV with a resolution of 50 µV, which will null the offset error term to 1⁄4 LSB of full-scale for A D DS005671-91 Note 26: R2 = 49.5 R1 Note 27: Switches are LMC13334 CMOS analog switches. Note 28: The 9 resistors used in the auto-zero section can be ?5% tolerance. FIGURE 18. Gain of 100 Differential Transducer Preamp C0 www.national.com 34 80 (Continued) Functional Description A DS005671-92 FIGURE 19. Microprocessor Interface Circuitry for Differential Preamp D need for the CPU to determine which device requires servic- A flow chart for the zeroing subroutine is shown in Figure 20. It must be noted that the ADC0801 series will output an all ing. Figure 22 and the accompanying software is a method of determining which of 7 ADC0801 converters has com- zero code when it converts a negative input [VIN(?) , VIN(+)]. pleted a conversion (INTR asserted) and is requesting an in- Also, a logic inversion exists as all of the I/O ports are buff- ered with inverting gates. terrupt. This circuit allows starting the A/D converters in any sequence, but will input and store valid data from the con- Basically, if the data read is zero, the differential output volt- verters with a priority sequence of A/D 1 being read first, A/D age is negative, so a bit in Port B is cleared to pull VX more 2 second, etc., through A/D 7 which would have the lowest negative which will make the output more positive for the priority for data being read. Only the converters whose INT is next conversion. If the data read is not zero, the output volt- asserted will be read. age is positive so a bit in Port B is set to make VX more posi- The key to decoding circuitry is the DM74LS373, 8-bit D type tive and the output more negative. This continues for 8 ap- proximations and the differential output eventually flip-flop. When the Z-80 acknowledges the interrupt, the pro- converges to within 5 mV of zero. gram is vectored to a data input Z-80 subroutine. This sub- routine will read a peripheral status word from the The actual program is given in Figure 21. All addresses used DM74LS373 which contains the logic state of the INTR out- are compatible with the BLC 80/10 microcomputer system. puts of all the converters. Each converter which initiates an In particular: interrupt will place a logic ―0‖ in a unique bit position in the Port A and the ADC0801 are at port address E4 status word and the subroutine will determine the identity of Port B is at port address E5 the converter and execute a data read. An identifier word Port C is at port address E6 (which indicates which A/D the data came from) is stored in C0the next sequential memory location above the location of PPI control word port is at port address E7 the data so the program can keep track of the identity of the Program Counter automatically goes to ADDR:3C3D upon data entered. acknowledgement of an interrupt from the ADC0801 5.3 Multiple A/D Converters in a Z-80 Interrupt Driven Mode In data acquisition systems where more than one A/D con- verter (or other peripheral device) will be interrupting pro- gram execution of a microprocessor, there is obviously a www.national.com35 80 (Continued) Functional Description A D C0 DS005671-28 FIGURE 20. Flow Chart for Auto-Zero Routine www.national.com 36 80 (Continued) Functional Description A D ? DS005671-A5 Note 29: All numerical values are hexadecimal representations. ? FIGURE 21. Software for Auto-Zeroed Differential A/D C0 5.3 Multiple A/D Converters in a Z-80 Interrupt Driven The stack pointer must be dimensioned in the main pro- Mode (Continued) gram as the RST 7 instruction automatically pushes the ? PC onto the stack and the subroutine uses an additional The following notes apply: 6 stack addresses. ? ? It is assumed that the CPU automatically performs a RST The peripherals of concern are mapped into I/O space 7 instruction when a valid interrupt is acknowledged with the following port assignments: (CPU is in interrupt mode 1). Hence, the subroutine start- ing address of X0038. The address bus from the Z-80 and the data bus to the Z-80 are assumed to be inverted by bus drivers. A/D data and identifying words will be stored in sequen- tial memory locations starting at the arbitrarily chosen ad- dress X 3E00. www.national.com37 80 (Continued) HEX PORT ADDRESS PERIPHERAL Functional Description 04 A/D 4 HEX PORT ADDRESS PERIPHERAL 05 A/D 5 00 MM74C374 8-bit flip-flop 06 A/D 6 01 A/D 1 07 A/D 7 02 A/D 2 This port address also serves as the A/D identifying word in 03 A/D 3 the program. A D DS005671-29 FIGURE 22. Multiple A/Ds with Z-80 Type Microprocessor C0 www.national.com 38 80 (Continued) Functional Description A DDS005671-A6 C0 39 www.national.com 80 inches (millimeters) unless otherwise noted Physical Dimensions A DSO Package (M) Order Number ADC0802LCWM or ADC0804LCWM NS Package Number M20B C0 Molded Dual-In-Line Package (N) Order Number ADC0801LCN, ADC0802LCN, ADC0803LCN, ADC0804LCN or ADC0805LCN NS Package Number N20A 40www.national.com 80 Notes A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant support device or system whose failure to perform into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system, or to affect its safety or effectiveness. accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd. 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