VerilogHDL代码_AHB总线_master部分

------------------------------------------作者xxxx------------------------------------------日期xxxxVerilogHDL代码_AHB总线_master部分【精品文档】【精品文档】【精品文档】【精品文档】【精品文档】【精品文档】moduleahb_master(HBUSREQ,HLOCK,HTRANS,HADDR,HWRITE,HSIZE,HBURST,HWDATA,HSEL,hcount,HRESETn,HCLK,HGRANT,HREADY,HRESP,HRDATA,BUSREQ,ADDREQ,WRITE,ADDR,SIZE,BURST,SEL,TRANS,WDATA);outputHBUSREQ,HLOCK,HWRITE;output[1:0]HTRANS,HSEL;output[31:0]HADDR,HWDATA;output[2:0]HSIZE,HBURST;inputHGRANT,HREADY,HCLK,HRESETn,BUSREQ,ADDREQ,WRITE;input[31:0]ADDE,WDATA;input[2:0]SIZE,BURST;input[1:0]HRESP,SEL,TRANS;input[31:0]HRDATA;regHBUSRREQ,HLOCK,HWRITE,hcount;reg[1:0]HTRANS,HSEL;reg[31:0]HADDR,HWDATA;reg[2:0]HSIZE,HBURST;wireHGRANT,HREADY,HCLK,HRESETn,WRITE;wire[31:0]ADDR,WDATA;wire[2:0]SIZE,BURST;wire[1:0]HRESP,SEL,TRANS;wire[31:0]HRDATA;regbus_reg,adde_reg,new_hready,old_hready;reg[31:0]RDATA;reg[31:0]h_addr;parameterOKAY=2'b00ERROR=2'b01RETRY=2'b10SPLIT=2'b11;always@(posedgeHCLK)beginif(!HRESETn)beginHBUSREQ=0;HLOCK=0;HWRITE=0;HTRANS=2'b00;HSEL=2'b00;HADDR=32'h000000000;HWDATA=32'h000000000;HSIZE=2'b00;HBURST=2'b00;bus_reg=0;addr_reg=0;new_hready=0;old_hready=0;hcount=0;endendalways@(posedgeHCLK)beginif(HRESETn)beginif(!addr_reg)beginif(ADDREQ)beginHADDR=ADDR;h_addr=ADDR;HWRITE=WRITE;HSIZE=SIZE;HBURST=BURST;HSEL=SEL;HTRANS=TRANS;addr_reg=1'b1;HWDATA=32'h000000000;endendelseif(addr_reg)beginHADDR=32'h000000000;HWRITE=1'b0;HSIZE=3'b000;HBURST=3'b000;HTRANS=2'b00;addr_reg=1'b0;endif(!ADDREQ)beginif(WRITE)beginhcount=0;case({TRANS})2'b00:beginHWDATA=WDATA;if(HREADY&&!new_hready&&HRESP==ERROR)new_hready=1;elseif(new_hready!=old_hready)HWDATA=32'h00000000;end2'b01:beginhcount=hcount+1;new_hready=0;HWDATA=WDATA;if(HREADY&&!new_hready&&HRESP)new_hready=1;elseif(new_hready!=oldhready)hWDATA=32'h00000000;end2'b10:beginHWDATA=32'h00000000;end2'b11:beginhcount=hcount+1;HWDATA=WDATA;if(HREADY&&HRESP==OKAY)beginif(!new_hready)new_hready=1;endelseif(new_hready!=old_hready)beginHWDATA=WDATA;new_hready=0;endelseif(HREADY&&HRESP==ERROR)beginHWDATA=32'h00000000;endendendcaseendelseif(!WRITE)begincase({TRANS})2'b00:beginif(!HREADY)RDATA=HRDATA;elseif(HREADY)RDATA=32'h00000000;end2'b01:beginif(!HREADY)beginRDATA=HRDATA;if(HBURST==000)h_addr=h_addr+1;elseh_addr=h_addr-1;endelseif(HREADY)RDATA=32'h00000000;end2'b10:beginRDATA=32'h00000000;end2'b11:beginif(!HREADY)beginRDATA=HRDATA;if(HBURST==000)h_addr=h_addr+1;elseh_addr=h_addr-1;endendcaseendendendendmodulemoduleram_top(HCLK,HRESETn,HSEL_s,HADDR_s,HBURST_s,HTRANS_s,HRDATA_s,HWDATA_s,HWRITE_s,HREADY_s,HRESP_s);inputHCLK;inputHRESETn;inputHSEL_s;input[19:0]HADDR_s;input[2:0]HBURST_s;input[1:0]HTRANS_s;input[31:0]HWDATA_s;inputHWRITE_s;output[1:0]HRESP_s;output[31:0]HRDATA_s;outputHREADY_s;wire[31:0]ram_RDATA;wire[17:0]ram_ADDR;wire[31:0]ram_WDATA;wireram_WRITE;ram_ahbifU_ram_ahbif(.HCLK(HCLK),.HRESETn(HRESETn),.HSEL_s(HSEL_s),.HADDR_s(HADDR_s),.HBURST_s(HBURST_s),.HTRANS_s(HTRANS_s),.HRDATA_s(HRDATA_s),.HWDATA_s(HWDATA_s),.HWRITE_s(HWRITE_s),.HREADY_s(HREADY_s),.HRESP_s(HRESP_s),.ram_RDATA(ram_RDATA),.ram_ADDR(ram_ADDR),.ram_WDATA(ram_WDATA),.ram_WRITE(ram_WRITE));ram_inferU_ram_infer(.q(ram_RDATA),.a(ram_ADDR),.d(ram_WDATA),.we(ram_WRITE),.clk(HCLK));endmodulemoduleram_infer(q,a,d,we,clk);output[31:0]q;input[31:0]d;input[17:0]a;inputwe;inputclk;reg[31:0]mem[262143:0];always@(posedgeclk)beginif(we)beginmem[a]<=d;endendassignq=mem[a];endmodulemoduleram_ahbif(HCLK,HRESETn,HSEL_s,HADDR_s,HBURST_s,HTRANS_s,HRDATA_s,HWDATA_s,HWRITE_s,HREADY_s,HRESP_s,ram_RDATA,ram_ADDR,ram_WDATA,ram_WRITE);/////////////////////////////////////////declarationofinput&output///////////////////////////////////////inputHCLK;inputHRESETn;inputHSEL_s;input[19:0]HADDR_s;input[2:0]HBURST_s;input[1:0]HTRANS_s;input[31:0]HWDATA_s;inputHWRITE_s;output[1:0]HRESP_s;output[31:0]HRDATA_s;outputHREADY_s;input[31:0]ram_RDATA;output[17:0]ram_ADDR;output[31:0]ram_WDATA;outputram_WRITE;/////////////////////////////////////////declarationofregisters&wires///////////////////////////////////////wire[1:0]HRESP_s;wire[31:0]HRDATA_s;regHREADY_s;wire[31:0]ram_WDATA;reg[17:0]ram_ADDR;regram_WRITE;wirewr_en;wirerd_en;wireready_en;/////////////////////////////////////////program&function///////////////////////////////////////assignHRESP_s=2'b00;always@(posedgeHCLKornegedgeHRESETn)begin//HSIZE=3'b010--32bitsif(!HRESETn)beginram_ADDR<=18'b000000000000000000;endelseif(HSEL_s==1'b1)beginram_ADDR<=HADDR_s[19:2];endendassignwr_en=HSEL_s&HTRANS_s[1]&HWRITE_s;always@(posedgeHCLKornegedgeHRESETn)beginif(!HRESETn)beginram_WRITE<=1'b0;endelseif(wr_en)beginram_WRITE<=1'b1;endelsebeginram_WRITE<=1'b0;endendassignram_WDATA=HWDATA_s;assignHRDATA_s=ram_RDATA;assignready_en=HSEL_s&HTRANS_s[1];always@(posedgeHCLKornegedgeHRESETn)beginif(!HRESETn)beginHREADY_s<=1'b0;endelseif(ready_en)beginHREADY_s<=1'b1;endelsebeginHREADY_s<=1'b0;endendendmodule