四位全加器的VHDL与VerilogHDL实现

四位全加器的VHDL与VerilogHDL实现四位全加器的VHDL/VerilogHDL实现加法器的分类（一）半加器能对两个1位二进制数进行相加而求得和及进位的逻辑电路称为半加器。或：只考虑两个一位二进制数的相加，而不考虑来自低位进位数的运算电路，称为半加器。图1为半加器的方框图。图2为半加器原理图。其中：AB分别为被加数与加数，作为电路的输入端；S为两数相加产生的本位和，它和两数相加产生的向高位的进位C一起作为电路的输出。根据二进制数相加的原则，得到半加器的真值表如表1所列。辑函数表达式为：(1)C=AB(2)由此可见，式(1)是一个异或逻辑关系，可用一个异或门来实现；式(2)可用一个与门实现。仿真结果如图3所示：图3半加器仿真图(二)全加器除本位两个数相加外，还要加上从低位来的进位数，称为全加器。图4为全加器的方框图。图5全加器原理图。被加数A、加数B从低位向本位进位C-1作为电路的输入，全加和S与向高位的进位C作为电路的输出。能实现全加运算功能的电路称为全加电路。全加器的逻辑功能真值表如表2中所列。00110010100110110010101011100111111表2全加器逻辑功能真值表多位全加器连接可以是逐位进位，也可以是超前进位。逐位进位也称串行进位，其逻辑电路简单，但速度也较低。五、加法器的VHDL实现(一)半加器VHDL语言描述语句为：so<=axorb；co<=aandb程序 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 ：libraryieee;useieee.std」ogic_1164.all;entityh_adderisport(a,b:instd_logic;so,co:outstd_logic);定义输入、输出端口endh_adder;architecturebhofh_adderisbeginso<=axorb;“异或”运算co<=aandb;“与”运算endbh;（二）全加器1位全加器可由两个半加器组成，在半加器的基础上，采用元件调用和例化语句，将件连接起来,而实现全加器的VHDL编程和整体功能。全加器包含了两个半加器和一个或门。在此基础上可设计出四位全加器。六、四位全加器四位全加器VHDL程序代码如下：libraryieee;useieee.std」ogic_1164.all;useieee.std_logic_unsigned.all;entityaddisport(cin:instd_logic;a,b:instd_logic_vector(3downto0);s:outstd_logic_vector(3downto0);cout:outstd_logic);endadd4;architecturebehofadd4issignalsint:std_logic_vector(4downto0);signalaa,bb:std」ogic_vector(4downto0);beginaa<='0'&a(3downto0);--4位加数矢量扩为5位，提供进位空间bb<='0'&b(3downto0);sint<=aa+bb+cin;s(3downto0)<=sint(3downto0);cout<=sint(4);endbeh;四位全加器VerilogHDL程序代码如下：moduleadd(A,B,CI,CO,S);parameterN=4;input[N:1]A,B;inputCl;outputCO;output[N:1]S;assign{CO,S}=A+B+CI;endmodule四位全加器常用三种编程方法:/*moduleadd(s,co,a,b,ci);〃output[3:0]s;outputco;input[3:0]a,b;inputci;regco;reg[3:0]s;always@(*)begin{co,s}=a+b+ci;endendmodule*/moduleadd(s,co,a,b,ci);〃行为描述法结构描述法output[3:0]s;outputco;input[3:0]a,b;inputci;full_add1f0(a[0],b[0],ci,s[0],ci1);full_add1f1(a[1],b[1],ci1,s[1],ci2);full_add1f2(a[2],b[2],ci2,s[2],ci3);full_add1f3(a[3],b[3],ci3,s[3],co);endmodulemodulefull_add1(a,b,cin,sum,cout);inputa,b,cin;outputsum,cout;wires1,m1,m2,m3;and(m1,a,b),(m2,b,cin),(m3,a,cin);xor(s1,a,b),(sum,s1,cin);or(cout,m1,m2,m3);endmodule/*moduleadd(co,s,a,b,ci);〃数据流法output[3:0]s;outputco;input[3:0]a,b;inputci;assign{co,s}=a+b+ci;endmodule*/libraryIEEE;useIEEE.Std_logic_1164.ALL;entitypro1isport(A1,B1,G1BAR,A0,B0,G0BAR:instd」ogic;Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:outstd」ogic);endpro1;architecturepro1_archofpro1isbeginY10<='0'when(BO='O')and((AO='O')and(G0BAR='0'))else'1';Y11<='0'when(BO='O')and((A0='1')and(G0BAR='0'))else'1';Y12<='0'when(B0='1')and((A0='0')and(G0BAR='0'))else'1';Y13<='0'when(B0='1')and((A0='1')and(G0BAR='0'))else'1';Y20<='0'when(B仁'0')and((A仁'0')and(G1BAR='0'))else'1';Y21<='0'when(B仁'0')and((A仁'1')and(G1BAR='0'))else'1';Y22<='0'when(B仁'1')and((A1='0')and(G1BAR='0'))else'1';Y23<='0'when(B1='1')and((A1='1')and(G1BAR='0'))else'1';endpro1_arch;一、1位全加器ENTITYfull_addISPORT(a,b,cin:INBIT;cout,sum:OUTBIT);ENDfull_add;ARCHITECTUREadderOFfull_addIS--逻辑表达式实现BEGINcout<=((axorb)andcin)or(aandb);sum<=(axorb)xorcin;ENDadder;ARCHITECTUREadder2OFfull_addIS--真值表实现SIGNALabcin:BIT_VECTOR(0to2);SIGNALyout:BIT_VECTOR(0to1);BEGINabcin<=a&b&cin;WITHabcinSELECTyout<="00"WHEN"000","01"WHEN"001","01"WHEN"010","10"WHEN"011","01"WHEN"100","10"WHEN"101","10"WHEN"110","11"WHEN"111";cout<=yout(0);sum<=yout(1);ENDadder2;：、4位加法器之前已生成了fulladd.vhdENTITYadd4parISPORT(c0:INBIT;a,b:INBIT_VECTOR(4downto1);c4:OUTBIT;sum:OUTBIT_VECTOR(4downto1));ENDadd4par;ARCHITECTUREadderofadd4parISCOMPONENTfull_addPORT(a,b,cin:INBIT;cout,sum:OUTBIT);ENDCOMPONENT;SIGNALc:BIT_VECTOR(3downto1);BEGINadder1:full_addPORTMAP(a=>a(1),b=>b(1),cin=>c0,cout=>c(1),sum=>sum(1))--上面的书写方式中，参数顺序可任意调整。adder2:full_addPORTMAP(a(2),b(2),c(1),c(2),sum(2));adder3:full_addPORTMAP(a(3),b(3),c(2),c(3),sum(3));adder4:full_addPORTMAP(a(4),b(4),c(3),c(4),sum(4));ENDadder;--利用生成语句，可进一下简化语句的书写ENTITYadd4genISPORT(c0:INBIT;a,b:INBIT_VECTOR(4downto1);--4改为8c4:OUTBIT;sum:OUTBIT_VECTOR(4downto1));--4改为8ENDadd4gen;ARCHITECTUREadderOFadd4genISCOMPONENTfull_addPORT(a,b,cin:INBIT;cout,sum:OUTBIT);ENDCOMPONENT;SIGNALc:BIT_VECTOR(4downto0);--4改为8BEGINc(0)v=cO;adders:FORiIN1to4GENERATE--FORiIN1to8GENERATEadder:full_addPORTMAP(a(i),b(i),c(i-1),c(i),sum(i));ENDGENERATE;c4<=c(4);--c8<=c(8)ENDadder;若要扩展为8位加法器，则很容易修改，将上面的4改为8即可