Protel 99 SEMaking Electronic Design Easy™
Designer’s Handbook
Supplement
Runs on
Windows
NT/95/98
2
Increase your PCB Design Productivity with Protel 99 SE
Welcome to the Protel 99 SE Designer's Handbook Supplement, your comprehensive guide to
exploring and using the new and enhanced features included in Protel 99 SE. The information in this
supplement will help you get the most from Protel 99 SE's advanced board design features, and
complements the comprehensive information provided in the Protel 99 Designer's Handbook.
Protel 99 SE is the latest version of Protel's integrated board-level design system for the Windows
NT/98/95 operating system. It builds on the foundation of Protel's unique Design Explorer platform,
introduced with the release of Protel 99, by adding a host of new and enhanced features aimed at
streamlining the board design process.
Protel 99 SE’s Design Explorer integration platform has been optimized to give fast application and
design document opening, more responsive performance and more efficient memory usage. You now
have a choice of design data storage methods – save your integrated design in a single Access
database, or as stand-alone files and folders using the simplicity of the Windows File System. With
either storage method you have available the full power and convenience of Protel 99 SE’s design
management and integration features.
From design entry through to manufacturing output creation, Protel 99 SE gives you greater design
flexibility and power. Capture your design faster and more accurately with Protel 99 SE’s enhanced
schematic editor, that now features direct on-sheet text editing, sheet-by-sheet and positional
annotation, automatic component class creation based on source schematic sheets, plus a host of time-
saving editing and interface enhancements.
Create your board from 32 signal layers, 16 internal plane layers, and 16 mechanical layers, with fully-
definable layer stackup and drill layer pairing. With enhanced power plane connectivity, new design
rules and rule scopes, and import/export of design rule sets, Protel 99 SE’s PCB editor gives you
unparalleled versatility in board design definition.
New and enhanced interactive component placement tools will slash design layout time. Protel 99 SE
supports on-board graphical creation and editing of placement rooms, dynamic real-time optimization
of connection lines during component moves, and the ability to group components for fast placement
of component blocks.
New PCB design features in Protel 99 SE include a powerful PCB print management system, an
advanced 3D PCB renderer and viewer, and an invaluable CAM Manager that gives you “one click”
output generation.
The above enhancements and features are just a taste of the many ways in which Protel 99 SE makes
your desktop a more productive board design environment. Please explore this supplement and see just
how much easier design can be with Protel 99 SE.
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Design Explorer
The Design Explorer is the name given to the Protel 99 SE design environment. When you select
Protel 99 from the Windows Start menu, the Design Explorer opens. The Design Explorer is the
interface to your designs, and the various design tools that you use to create your designs.
Windows File System Storage Option
Protel 99 SE includes a new document storage option that stores design documents directly on a disk
drive. The New Design Database dialog includes a new Design Storage Type option, where you specify
if the design documents will be stored in a single integrated Microsoft Access database, or if they will
be stored directly on a disk drive.
If the Storage Type is set to MS Access Database then all design documents are stored in a single
database. If the Storage Type is set to Windows File System then all design documents are stored
directly on the disk drive in the location specified at the bottom of the dialog.
Regardless of the storage system that is chosen, the way you work in the Design Explorer is exactly the
same. If your design uses the Windows File System Storage Type you still open the design first – then
open the schematic, PCB, or other design documents.
New documents are created in the same way for both storage types, select File » New to create a new
document. Note that you can not move documents into a Windows File System database with the
Windows File Explorer, they must be imported into a database before they can be opened. You can
import a number of files by importing a folder, or by dragging from the Windows File Explorer
directly into an open design.
Designs that use the Windows File System storage do not support any of the DesignTeam features,
such as document access control. Other design integration features, like synchronization and
background document opening when printing and netlisting, are supported.
Emailing from the Design Explorer
Design documents can be emailed directly from the Design Explorer. Select the documents in the
Design Explorer that you want to email, then select File » Send by Mail from the menus.
Select the document storage type when you create a new design
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New Document Find Feature
Protel 99 SE includes a new Document Finder, which operates like the File Find Feature in the
Microsoft Windows Explorer. The document finder can be used to search for documents in designs
that are currently open in the Design Explorer, or it can be used to search for documents in designs that
are on the hard disk. Select File » Find Files from the Design Explorer menus (when a folder is the
active window) to pop up the Find All Documents dialog.
Improved Performance
Protel 99 SE has been optimized for faster performance, with reduced Design Explorer startup time, as
well as faster opening of designs and design documents. Network performance has been enhanced with
reduced inter-design station communications and CPU usage.
Floating Licenses
Protel 99 SE supports floating licenses. This system allows you to install Protel 99 SE on as many PCs
as you like – Protel 99 SE automatically monitors how many copies are running and displays a
warning message when there are too many copies running at the same time.
If your network includes PCs that must have a single-user license permanently allocated disable the
Broadcast and Receive Floating Access Codes options at the bottom Security Locks dialog.
Enhanced Status Bar
The message zones on the Design Explorer Status Bar can be resized – position the cursor over the
arrow symbols on the status bar, when the cursor changes to a double-headed arrow click and drag to
resize a message zone.
Use the Document Finder to quickly locate a design document
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PCB Design
Protel 99 SE includes a large number of productivity enhancements for the PCB designer – increased
design layers and a new layer stack manager, extended and enhanced design rules, a new printing
engine with sophisticated print previewing and printout manipulation, a new manufacturing output file
management system, a powerful 3D visualization tool, enhanced placement features, new autorouting
cleaning passes, new import and export capabilities, enhanced library editing and management
features, and numerous workspace selection and editing improvements.
The PCB Editor in Protel 99 SE uses a new file format (PCB4.0). Refer to the File Importers and
Exporters topic later in this section of the supplement for details on exporting a PCB file to an older
version file format.
PCB Layer and Power Plane Enhancements
A PCB is fabricated as a series of layers, including copper electrical layers, insulation layers,
protective masking layers, and text and graphic overlay layers.
There are 2 types of electrical layers – signal layers, which contain the signal interconnect paths, and
power planes, which are layers of unbroken copper used to distribute current to power the components.
In Protel 99 SE these signal and plane layers are made available in the workspace by defining the layer
stack-up.
Defining the Layer Stack
To define the layer stack select Design » Layer Stack Manager from the menus. The Layer Stack Manager
dialog will appear. In the center of the dialog there is a image that shows the current layer stack, the
default is for a double-sided board. More layers can be added to the design by clicking on the Add
Layer and Add Plane buttons. Each new layer is added below the currently selected layer in the layer
stack.
The Menu button at the bottom of the dialog also includes a number of pre-packed example layer
stacks. Note that these example layer stacks are not fixed, you can start with one of these and easily
modify it. Once the required layers have been added, use the Move Up and Move Down buttons to
configure the layer stack. New layers can be added at any point in the design process.
There are a total of 32 signal layers available (top layer, bottom layer, and 30 mid-layers) and 16 plane
layers.
Layer stack for an eight layer board with 4 signal layers and 4 plane layers
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Selecting the Layer Stack-up Style
As well as the electrical layers, the stack-up includes the non-electrical insulation layers. There are
typically 2 kinds of insulation used in the fabrication of a PCB, usually referred to as core and prepreg.
What are these insulators and how are they used?
Consider the typical fabrication process for a 4 layer PCB. A 4 layer PCB normally starts out as a piece
of insulating core (usually a fiberglass material) which has thin layers of copper laminated on either
side – in fact it is simply a thin double-sided PCB.
These copper layers are etched to create the signal tracks. Once this inner ‘slice’ is ready, a layer of
prepreg insulation is applied to either side, then a layer of copper foil is applied to the outside of these
prepreg layers. This layered structure is then laminated (bonded together) under heat and pressure,
causing the prepreg layers to soften slightly and bond the various layers together. If the finished board
were sliced so you could see inside, it would look like the figure below.
The stack-up style refers to the order of the insulation layers through the layer stack. Three default
stack-up styles are supported – layer-pairs, internal layer-pairs, and build up. Changing the layer stack-
up style changes the way that the core and prepreg layers are distributed through the layer stack.
Select the preferred stack-up style at the top left of the Layer Stack Manager dialog. The stack-up style
is only important if you plan to use blind and buried vias, and for signal integrity analysis. If you are
not using blind and buried vias, or planning on performing a signal integrity analysis you can ignore
this option. If you are planning to use blind and buried vias you must consult with your PCB
manufacturer to ensure that that they can fabricate the design, and that the correct stack-up style is
selected.
Setting up the Layer Properties
The properties of each layer are defined by double-clicking on the layer name in the Layer Stack
Manager dialog (or on the layer in the stack-up image).
Signal layers properties that can be defined
include the layer name and the copper thickness.
The copper thickness setting is used for signal
integrity analysis.
Plane layer properties that can be defined include
the layer name, the copper thickness, and the net
name. The net name is selected from the list of
currently available nets. All thru-hole pads and
vias assigned to this net are automatically
connected to this plane, in accordance with the
appropriate Power Plane Connection Style design
rule (select Design » Rules from the menus to edit
the rules).
If you have not transferred the schematic design into the PCB workspace no nets will be available – if
this is the case, leave the net name unassigned until the design has been transferred.
A cut-away of a 4 layer PCB showing the arrangement of the insulation layers
Layer properties dialog for an internal plane layer
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Core and prepreg properties that can be defined include the material, the thickness, and the dielectric
constant. These settings are used during signal integrity analysis, leave them at their defaults unless
you have a specific need to change them.
Setting up the Drill-Pairs
The last step in defining the layer stack-up is to specify the drill-pairs. The term drill-pairs refers to the
2 layers that a drilling operation starts from, and stops at. Unless the board includes blind and buried
vias only one drill-pair is required, comprising the Top and Bottom layers. This drill-pair is on by
default and can not be deleted or modified.
Drill-pairs are defined in the Drill-Pair Manager dialog, click on the Drill-Pairs button in the Layer Stack
Manager dialog to display this dialog.
If the design includes blind and buried layers then the drill pairs must be defined to suit the layer stack-
up style. This should be done in consultation with your board manufacturer to ensure that your design
matches their fabrication technology. For more information on blind and buried vias refer to the Vias
topic in the PCB Design Objects chapter of the Designer’s Handbook.
Enabling and Naming the Mechanical Layers
Mechanical layers are general purpose non-electrical layers that can be used for any task your design
requires. Some examples of what they can be used for include: defining the board outline,
dimensioning, assembly information, NC routing details, special mask requirements (such as glue
masks or peelable solder masks), title block and border details, and so on.
To enable the mechanical layers select Design » Mechanical Layers from the PCB Editor menus. Each
mechanical layer can be named. Like other layers, a mechanical layer can only be disabled if there are
no design objects on it, if a layer has objects on it the Enable check box will be grayed out. Note that
you can also selectively display mechanical layers when single layer mode is enabled (single layer
mode hides all layers except the current layer – press the SHIFT+S shortcut keys to toggle single layer
mode on and off).
Controlling the Display of Layers
The display of enabled layers is controlled in the Document Options dialog, select Design » Options to
display this dialog. As well as the user-defined signal, plane and mechanical layers, this dialog gives
you control over the display of all the other layers available in the PCB Editor workspace.
Layer colors are defined in the Colors Tab of the Preferences dialog, select Tools » Preferences to
display this dialog.
Layer Specific Keepout Objects
Layer-specific keepout objects can be placed on electrical layers to act as a routing barrier. Select Place
» Keepout from the PCB Editor menus to place a keepout track, fill or arc (or use the K shortcut key to
pop up the Keepout sub-menu). Keepout objects are rendered in the same color as the layer they are
placed on, with a border drawn in the current keepout color. Keepout objects are not included in
Gerber generation, they can be included in printouts by enabling the Print Keepout Objects option in
the Power Print Preferences dialog.
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PCB Design Rules
Design Rules are the basis of design specification and control in the PCB Editor. The enhancements to
the rule system include: new rules, new rule scopes, the ability to disable individual rules, importing
and exporting of rule sets, new rule reports, and the ability to interrogate any design object on the
board to establish what rules apply to that object. The PCB Editor panel has also been enhanced to
include rules, making it easy to examine the rules and what each rule applies to.
This topic should be read in conjunction with the chapter Specifying the PCB Design Requirements in the
Protel 99 Designer’s Handbook.
New and Enhanced Routing Rules
Width Constraint
This rule now includes Minimum, Maximum, and Preferred settings. The Minimum and Maximum
settings are obeyed by on-line and batch DRC. The Preferred setting is obeyed during manual and auto
routing, and can be changed on-the-fly during manual routing by pressing the TAB shortcut key.
Routing Via Style
This rule now includes Minimum, Maximum, and Preferred settings. The Minimum and Maximum
settings are obeyed by on-line and batch DRC. The Preferred settings are obeyed during manual
routing, and (for the Board scope rule) during autorouting. The Preferred settings can be changed on-
the-fly during manual routing by pressing the TAB key.
SMD To Plane Constraint
This rule specifies the maximum total route length allowed from the center of an SMD pad to the
center of the power plane connection pad/via. This rule is obeyed by on-line and batch DRC.
SMD Neck-Down Constraint
This rule specifies the maximum allowable ratio of the track width to the SMD
pad width, expressed as a percentage. Tracks that result in a ratio larger than this
amount are flagged as a violation. This rule is obeyed by on-line and batch DRC.
New Manufacturing Rules
Hole Size Constraint
This rule specifies the maximum and minimum allowable hole size, expressed either as exact numeric
values, or as a percentage of the pad size. This rule is obeyed by on-line and batch DRC.
Layer-Pairs
This rule checks that vias and pads only connect between the defined drill pairs. To define the
allowable layer-pairs select Design » Layer Stack Manager, then click on the Drill Pairs button to display
the Drill-Pair Manager dialog. This rule is obeyed by the auto-via feature during manual routing, and by
on-line and batch DRC.
Testpoint Style
This rule specifies the allowable physical parameters of pads and vias that are flagged as testpoints. A
pad or via is defined as a testpoint when it has one or both of its Testpoint attributes enabled. All rule
attributes apart from the preferred size settings are checked by the online and batch DRC.
The rule is also used by the Find and set Testpoints feature (Tools menu), which searches the PCB for a
suitable pad/via in each net that complies with this rule, and then enables its testpoint attribute.
The autorouter also uses this rule if the Add Testpoint option is enabled in the Autorouter Setup dialog.
The autorouter places round pads of the size defined in the Preferred fields of the Testpoint Style Rule
dialog, on the layer specified in the Allowed Side settings.
The Allowed Side settings are used by the testpoint finder and the autorouter in the following pre-
defined order: Bottom (SMD Pads), Top (SMD pads), Bottom Thru-hole, and Top Thru-hole,
depending on which are enabled of course.
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Testpoint Usage
This rule specifies which nets are required to have a testpoint. Note that it can also be used to specify
nets that must not have a testpoint. This rule is obeyed by the Find Testpoint feature and by the
Autorouter during testpoint placement, and by the on-line and batch DRC.
Use the DRC report to identify nets that should have a testpoint, but do not. Use the Testpoint report
feature in the CAM Manager to identify the location of all testpoints (select File » CAM Manager from
the menus to configure this).
New and Enhanced Placement Rules
Component Clearance Constraint
This rule specifies the minimum clearance allowed between components. The Gap setting in the rule is
the distance allowed between components targeted by the rule scope. This rule is obeyed by on-line
and batch DRC, and by the cluster-based autoplacer.
Room Definition
This rule is used to define the location of a placement room, and the set of components that must be in
that room. Read the PCB Placement Enhancements section later in this document for more details on
how to use Rooms.
Other Rules Enhancements
Unconnected Pin Constraint
This rule detects pins that have no net assigned and no connecting tracks. This rule is obeyed by on-
line and batch DRC.
New and enhanced Rule Scopes
The scope of each rule defines exactly what that rule must target. To enhance the power and flexibility
of the rule system a number of new rule scopes have been
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