转 数字电路基本知识

转 数字电路基本知识 锁存器(latch):如RS锁存器，不过好像一般的数字电路 书 关于书的成语关于读书的排比句社区图书漂流公约怎么写关于读书的小报汉书pdf 都叫基本RS触 发器。触发器(flipflop，FF):如DFF，D触发器。好像除了基本RS触发器外， 数电书上后面的主从触发器、边沿触发器都有CP时钟信号，都是触发器，非 latch锁存器。门电路是构建组合逻辑电路的基础，而锁存器和触发器是构建 时序逻辑电路的基础。门电路是由晶体管构成的，锁存器是由门电路构成的， 而触发器是由锁存器构成的。也就是晶体管-门电路-锁存器-触发器,前一级是 后一级的基础。锁存器和触发器它们的输出都不仅仅取决于目前的输入，而且 和之前的输入和输出都有关系。它们之间的不同在于:锁存器没有时钟信号， 而触发器常常有时钟触发信号。锁存器是异步的，就是说在输入信号改变后， 输出信号也随之很快做出改变非常快。而另外一方面，今天许多计算机是同步 的，这就意味着所有的时序电路的输出信号随着全局的时钟信号同时做出改变。 触发器是一个同步版锁存器。找到一篇介绍latch和FF的区别的文章，写的确 实是不错。摘抄到这里供参考。Latches and flip-flops In the same way thatgates are the building blocks of combinatorial circuits,latches and flip-flops are the building blocks of sequential circuits.While gates had to be built directly from transistors,latches can be built from gates,and flip-flops can be built from latches.This fact will make it somewhat easier to understand latches and flip-flops.Both latches and flip-flops are circuit elements whose output depends not only on the current inputs,but also on previous inputs and outputs.The difference between alatch and aflip-flop is that alatch does not have aclock signal,whereas aflip-flop always does.LatchesHow can we make acircuit out of gates that is not combinatorial?The answer is feed-back,which means that we create loops in the circuit diagrams so that output values depend,indirectly,on themselves.If such feed-back is positive then the circuit tends to have stable states,and if it is negative the circuit will tend to oscillate.A latch has positive feedback.Here is an example of asimple latch:This latch is called SR-latch,which stands for set and reset.It is not practical to use the methods that we have used to describe combinatorial circuits to describe the behavior of the SR-latch.Later,we will show amethod for describing flip-flops and on to clocked sequential circuits.For now,we just rely on our intuitidescribe how latches work.The SR-latch is meant to have at most one of its inputs equal to 1at any time.When both of its inputs are 0it has two different stable states possible.Either xis 0,in which case we have the following signal values:or else xis 1,in which case we have the following signal values:The actual value depends on the history of input values as we will show next.Now suppose that sis 1(and therefore ris 0since we allow at most one input to be 1at any time).We get the following signal values:The 1on the sinput makes sure the output of the upper nor-gate is 0,and the two 0s on the input of the lower nor-gate make sure the xoutput is 1.Now suppose the sinput goes from 1to 0,while the rinput remains at 0.The second input of the upper nor-gate is 1,so the transition from 1to 0of the sinput,does not make any difference.The xoutput remains at 1.In this case,if the sand rinputs are both 0,there is only one possible stable state,the one that gives xthe value 1.Conversely,suppose that ris 1(and therefore sis 0since we allow at most one input to be 1at any time).We get the following signal values:The 1on the rinput makes sure the xoutput is 0,and the two 0s on the input of the upper nor-gate make sure the output of the upper nor-gate is 0.Now suppose the rinput goes from 1to 0,while the sinput remains at 0.The second input of the lower nor-gate is 1,so the transition from 1to 0of the rinput,does not make any difference.The output of the upper nor-gate remains at 1.In this case,if the sand rinputs are both 0,there is only one possible stable state,the one that gives xthe value 0.From the discussion above,we conclude that the SR-latch is able to remember the last state of the inputs,in the sense that it remembers which of the two inputs,s or r,last had the value of 1.When we need to draw an SR-latch,we use the following symbol:Flip-flopsLatches are asynchronous,which means that the output changes very soon after the input changes.Most computers today,on the other hand,are synchronous,which means that the outputs of all the sequential circuits change simultaneously to the rhythm of aglobal clock signal.A flip-flop is asynchronous version of the latch.To complicate -the situation even more,there are several fundamental types of flipflops.He re,we shall only consider atype called master-slave flip-flop.In addition to the fundamental types of flip-flops,there are minor variations depending on the number of inputs and how they control the state of the flip-flop.Here,we shall only consider avery simple type of flip-flop called aD-flip-flop.A master-slave D-flip-flop is built from two SR-latches and some gates.Here is the circuit The leftmost SR-latch is called the master and the rightmost diagram: is called the slave.Let us first consider what happens when the clock signal is 1.In this case,the two and-gates in front of the input of the master are open,i.e.,they let the value of the D-input through to the sinput of the master,and the inverse of the Dinput to the rinput of the master.Thus,the value of the Dinput will go straight trough the master to the xoutput of the master.But the two and-gates of the slave re closed,i.e.,their outputs are always 0,so the slave keeps its old value.When instead the clock signal is 0,the reverse is true,i.e.,the and-gates at the input of the master are closed,whereas the ones at the input of the slave are open.In this case,the flip-flop is completely insensitive to changes in input.Now,let us consider what happens when the clock goes from 1to 0.For this to work,we have to assume that the input remains the same during abrief period from right before to right after the clock signal changes.The first thing that happens is that the and-gates at the input of the master turn off,i.e.,they become insensitive to further changes in input.The value of the xoutput of the master is now the value of the Dinput right before the clock started changing.A brief moment later,the clock signal transition has traversed the inverter and reaches the and-gates of the slave.These gates open,allowing the xoutput of the master to be propagated to the xvalue of the slave.The xvalue of the slave,and therefore that of the entire flip-flop now contains the value of the Dinput right before the clock started changing.We can say that the clock transition copied the input to the output of the flip-flop.But at no point in time is there adirect path from input to output.The output changes only as aresult of clock transitions from 1to 0.Finally,let us see what happens when the clock goes from 0to 1.First,the and-gates of the master open,letting the value of the Dinput into the master.By the time the Dvalue reaches the master,the clock signal transition reaches the and-gates of the slave,and turns them off before the possibly modified output of the master reaches the slave.Thus,the slave keeps its old value.From the outside,nothing seems to happen,since the output does not change.From now on,however,the master is open to changes in the input.Here is the symbol we use for D-flip-flops:The little triangle for the clock input indicates that this input is sensitive only to transitions as opposed to levels as described in the previous paragraph.Sometimes we do not draw the clock input at all when it is understood that it is there.Clock signals are boring since they are all just connected to each other.There is therefore little use to draw them all,and thereby clutter the diagram unnecessarily.SummaryWe have shown how to build aD-flip-flop.It copies its input to its output as aresult of aclock signal transition from 1to 0.The value copied is the value the input has immediately before the clock transition.Most of the clock period,the D-flip-flop is insensitive to changes in the input.We shall use this key characteristic of the D-flip-flop to build synchronous sequential circuits.另外百度到一个高智勇吧，有一些他搜到 的一些东东，也放在这做参考最近看RISC CPU 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 ，发现里面的设计有Latch， 以前记得总是说最好不要用Latch，所以就有点怀疑，于是查了一些资料，发 现虽然Latch有一定的缺点，但是既然它存在，就肯定就有优点，原来它占用 面积更小，运行速度更快，所以有时会用在CPU设计，但是在普通设计中，还 是不提倡的，既然提到了Latch，那就不能不说说和它相关的几个其它概念:触发器、寄存器。锁存器(latch):我听过的最多的就是它是电平触发的，呵呵。锁存器是电平触发的存储单元，数据存储的动作取决于输入时钟(或者使能)信号的电平值，当锁存器处于使能状态时，输出才会随着数据输入发生变化。(简单地说，它有两个输入，分别是一个有效信号EN,一个输入数据信号DATA_IN，它有一个输出Q，它的功能就是在EN有效的时候把DATA_IN的值传给Q，也就是锁存的过程)。应用场合:数据有效迟后于时钟信号有效。这意味着时钟信号先到，数据信号后到。在某些运算器电路中有时采用锁存器作为数据暂存器。缺点:时序分析较困难。不要锁存器的原因有二:1、锁存器容易产生毛刺，2、锁存器在ASIC设计中应该说比ff要简单，但是在FPGA的资源中，大部分器件没有锁存器这个东西，所以需要用一个逻辑门和ff来组成锁存器，这样就浪费了资源。优点:面积小。锁存器比FF快，所以用在地址锁存是很合适的，不过一定要保证所有的latch信号源的质量，锁存器在CPU设计中很常见，正是由于它的应用使得CPU的速度比外部IO部件逻辑快许多。latch完成同一个功能所需要的门较触发器要少，所以在asic中用的较多触发器(flipflop):呵呵，当然最基本的就是边沿触发，也是我平时用的最多的了。记得刚接触IC时，死活就不明白ff到底是什么东西，呵呵应用场合:时钟有效迟后于数据有效。这意味着数据信号先建立，时钟信号后建立。在CP上升沿时刻打入到寄存器。锁存器与触发器的区别:锁存器电平触发会把输入端的毛刺带入输出;而触发器由于边沿作用可以有效抑制输入端干扰;寄存器(register):用来存放数据的一些小型存储区域，用来暂时存放参与运算的数据和运算结果。其实寄存器就是一种常用的时序逻辑电路，但这种时序逻辑电路只包含存储电路。寄存器的存储电路是由锁存器或触发器构成的，因为一个锁存器或触发器能存储1位二进制数，所以由N个锁存器或触发器可以构成N位寄存器。至于寄存器，是processor里面的东西，比如ARM核里面的R0~R15、CPSR、SPSR和MIPS核里面的[message]~，这些都是寄存器。而寄存器既可以由触发器设计，也可以由锁存器设计(register file设计是processor design里面非常核心的技术问 题 快递公司问题件快递公司问题件货款处理关于圆的周长面积重点题型关于解方程组的题及答案关于南海问题 之一)。Buffer:缓冲区，一个用于促初速度不同步的设备或者优先级不同的设备之间传输数据的区域，通过缓冲区，可以使进程之间的相互等待变少，从而是从速度慢的设备读入数据是，速度快的设备的操作进程不发生间断