补码乘法器VHDL.txt
Library IEEE;
Use IEEE.Std_logic_1164.ALL;
Use IEEE.Std_logic_unsigned.all;
Use IEEE.Std_logic_arith.all;
Entity Multiplier is
Generic(
Multiplicand_Width : integer;
Multiplicator_Width : integer);
Port(
Multiplicand : In Std_logic_vector(Multiplicand_Width-1 downto 0);
Multiplicator : In Std_logic_vector(Multiplicator_Width-1 downto 0);
Product : Out
Std_logic_vector(Multiplicand_Width+Multiplicator_Width-2 downto 0)); End Multiplier;
Architecture RTL of Multiplier Is
Component Adder
Generic(
Data_Width : integer);
Port(
Augend : In Std_logic_vector(Data_Width-1 downto 0);
Addend : In Std_logic_vector(Data_Width-1 downto 0);
Sum : Out Std_logic_vector(Data_Width-1 downto 0)); End Component;
Component Adder_Subtracter
Generic(
Data_Width : integer);
Port(
Add_Sub : In Std_logic;
Minuend : In Std_logic_vector(Data_Width-1 downto 0);
Subtrahend : In Std_logic_vector(Data_Width-1 downto 0);
Sum_Diff : Out Std_logic_vector(Data_Width-1 downto 0)); End Component;
Type Array_Product Is Array(Multiplicator_Width downto 0) Of std_logic_vector(Multiplicand_Width+Multiplicator_Width-1 downto 0); Signal Temp_Shift : Array_Product;
Signal Temp_Augend : Array_Product;
Signal Temp_Sum : Array_Product;
Signal Temp_Multiplicator : Std_logic_vector(Multiplicator_Width downto 0); Signal Fill_Zero : Std_logic_vector(Multiplicator_Width-1 downto 0); Signal Fill_Sign : Std_logic_vector(Multiplicator_Width-1 downto 0);
Signal Din :
Std_logic_vector(Multiplicand_Width+Multiplicator_Width-1 downto 0); Signal Add_Sub : Std_logic;
Begin
Gen_Sign : For Index in 0 to Multiplicator_Width-1 Generate
Fill_Sign(Index) <= Multiplicand(Multiplicand_Width-1);
End Generate Gen_Sign;
Fill_Zero <= (others => '0');
Temp_Multiplicator <= Multiplicator(Multiplicator_Width-1) & Multiplicator;
Temp_Shift(0) <= Fill_Sign & Multiplicand;
Gen_Shift : For Index in 1 to Multiplicator_Width Generate
Temp_Shift(Index) <= Fill_Sign(Multiplicator_Width-1-Index downto 0) &
Multiplicand & Fill_Zero(Index-1 downto 0);
End Generate Gen_Shift;
Gen_Augend : For Index in 0 to Multiplicator_Width Generate
Temp_Augend(Index) <= Temp_Shift(Index) When Temp_Multiplicator(Index) = '1'
Else (others => '0');
End Generate Gen_Augend;
--*****Serial Adder;
Inst_Adder_L : Adder
Generic Map(
Data_Width => Multiplicand_Width+Multiplicator_Width)
Port Map(
Augend => Temp_Augend(0),
Addend => Temp_Augend(1),
Sum => Temp_Sum(0));
Gen_Adder : For Index in 1 to Multiplicator_Width-2 Generate
Inst_Adder : Adder
Generic Map(
Data_Width => Multiplicand_Width+Multiplicator_Width)
Port Map(
Augend => Temp_Sum(Index-1),
Addend => Temp_Augend(Index+1),
Sum => Temp_Sum(Index));
End Generate Gen_Adder;
Add_Sub <= Multiplicator(Multiplicator_Width-1);
Inst_Adder_M : Adder_Subtracter
Generic Map(
Data_Width => Multiplicand_Width+Multiplicator_Width)
Port Map(
Add_Sub => Add_Sub,
Minuend => Temp_Sum(Multiplicator_Width-2),
Subtrahend => Temp_Augend(Multiplicator_Width),
Sum_Diff => Temp_Sum(Multiplicator_Width-1));
Product <=
Temp_Sum(Multiplicator_Width-1)(Multiplicand_Width+Multiplicator_Width-2 downto 0);
Din <= Temp_Sum(Multiplicator_Width-1)(Multiplicand_Width+Multiplicator_Width-1 downto 0);
End RTL;
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