6B595

D ata S heet 26185.122 8-BIT SERIAL-INPUT, DMOS POWER DRIVER The A6B595KA and A6B595KLW combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, sole- noids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in appli- cations requiring additional drive lines. Similar devices with reduced rDS(on) are available as the A6595KA and A6595KLW. The A6B595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6B595KA is furnished in a 20-pin dual in-line plastic package. The A6B595KLW is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C. FEATURES � 50 V Minimum Output Clamp Voltage � 150 mA Output Current (all outputs simultaneously) � 5 Ω Typical rDS(on) � Low Power Consumption � Replacements for TPIC6B595N and TPIC6B595DW 6B595 ADVANCE INFORMATION (Subject to change without notice) January 24, 2000 GROUND 1 2 3 8 9 13 14 15 16 17 19 4 5 6 7 12 18 20 SERIAL DATA OUT SERIAL DATA IN LOGIC SUPPLY VDD STROBE GROUND CLOCKCLK ST OUT7 OUT6 OUT5 Dwg. PP-029-12 OUT 0 OUT1 OUT 2 OUT 3 OUT 4 10 11 NO CONNECTION NO CONNECTIONNCNC OUTPUT ENABLE OE REGISTER CLEAR GROUND LA TC HE S RE G IS TE R RE G IS TE R LA TC HE S CLR Note that the A6B595KA (DIP) and the A6B595KLW (SOIC) are electrically identical and share a common terminal number assignment. Always order by complete part number: Part Number Package RθJA RθJC A6B595KA 20-pin DIP 55°C/W 25°C/W A6B595KLW 20-lead SOIC 70°C/W 17°C/W ABSOLUTE MAXIMUM RATINGS at TA = 25°C Output Voltage, VO ............................... 50 V Output Drain Current, Continuous, IO .......................... 150 mA* Peak, IOM ................................... 500 mA† Single-Pulse Avalanche Energy, EAS ................................................. 30 mJ Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VI ................................... -0.3 V to +7.0 V Package Power Dissipation, PD ........................................... See Graph Operating Temperature Range, TA ................................. -40°C to +125°C Storage Temperature Range, TS ................................. -55°C to +150°C * Each output, all outputs on. † Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1999, Allegro MicroSystems, Inc. FUNCTIONAL BLOCK DIAGRAM 50 75 100 125 150 2.5 0.5 0 A LL O W AB LE P AC KA G E PO W ER D IS SI PA TI O N IN W AT TS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 25 Dwg. GS-004A SUFFIX 'LW ', R = 70 °C/W θJA SUFFIX 'A', R = 55 °C/W θJA LOGIC SYMBOL 2 G3 C2 SRG8 C1 R 1D 2 4 5 6 7 14 15 16 17 18 9 12 8 3 13 Dwg. FP-043 GROUND Dwg. FP-013-4 CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE (ACTIVE LOW) SERIAL DATA OUTSERIAL-PARALLEL SHIFT REGISTER D-TYPE LATCHES VDD LOGICSUPPLY REGISTER CLEAR (ACTIVE LOW) OUT 0 OUT N GROUND Grounds (terminals 10, 11, and 19) must be connected together externally. 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com TRUTH TABLE Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Output Input Input I0 I1 I2 ... I6 I7 Output Strobe I0 I1 I2 ... I6 I7 Enable I0 I1 I2 … I6 I7 H H R0 R1 … R5 R6 R6 L L R0 R1 … R5 R6 R6 X R0 R1 R2 … R6 R7 R7 X X X … X X X — R0 R1 R2 … R6 R7 P0 P1 P2 … P6 P7 P7 P0 P1 P2 … P6 P7 L P0 P1 P2 … P6 P7 X X X … X X H H H H … H H L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State SERIAL DATA OUT LOGIC INPUTS Dwg. EP-063-1 VDD OUT DMOS POWER DRIVER OUTPUT IN Dwg. EP-010-16 VDD Dwg. EP-063 OUT RECOMMENDED OPERATING CONDITIONS over operating temperature range Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V High-Level Input Voltage, VIH ............................ ≥ 0.85VDD Low-level input voltage, VIL ................................. ≤0.15VDD 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Breakdown V(BR)DSX IO = 1 mA 50 — — V Voltage Off-State Output IDSX VO = 40 V, VDD = 5.5 V — 0.1 5.0 µA Current VO = 40 V, VDD = 5.5 V, TA = 125°C — 0.15 8.0 µA Static Drain-Source rDS(on) IO = 100 mA, VDD = 4.5 V — 4.2 5.7 Ω On-State Resistance IO = 100 mA, VDD = 4.5 V, TA = 125°C — 6.8 9.5 Ω IO = 350 mA, VDD = 4.5 V (see note) — 5.5 8.0 Ω Nominal Output ION VDS(on) = 0.5 V, TA = 85°C — 90 — mA Current Logic Input Current IIH VI = VDD = 5.5 V — — 1.0 µA IIL VI = 0, VDD = 5.5 V — — -1.0 µA SERIAL-DATA VOH IOH = -20 µA, VDD = 4.5 V 4.4 4.49 — V Output Voltage IOH = -4 mA, VDD = 4.5 V 4.0 4.2 — V VOL IOL = 20 µA, VDD = 4.5 V — 0.005 0.1 V IOL = 4 mA, VDD = 4.5 V — 0.3 0.5 V Prop. Delay Time tPLH IO = 100 mA, CL = 30 pF — 150 — ns tPHL IO = 100 mA, CL = 30 pF — 90 — ns Output Rise Time tr IO = 100 mA, CL = 30 pF — 200 — ns Output Fall Time tf IO = 100 mA, CL = 30 pF — 200 — ns Supply Current IDD(OFF) VDD = 5.5 V, Outputs OFF — 20 100 µA IDD(ON) VDD = 5.5 V, Outputs ON — 150 300 µA IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs OFF — 0.4 5.0 mA Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%. ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified). 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE OUTN Dwg. WP-029-2 50%SERIALDATA OUT DATA DATA 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED pt DATA 50% pt LOW = OUTPUT ON HIGH = OUTPUT OFF OUTPUT ENABLE OUTN Dwg. WP-030-2 DATA 10% 50% PHLt PLHt HIGH = ALL OUTPUTS DISABLED 90% ft rt A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 20 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CLK) ............................................. 40 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....................................................... 50 ns E. Strobe Pulse Width, tw(ST) .............................................. 50 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs NOTE – Timing is representative of a 12.5 MHz clock. Higher speeds are attainable. Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 TEST CIRCUITS 10 .5 Ω +15 V OUT 20 0 m H DUT Dwg. EP-066 INPUT IO VO tav IAS = 500 mA V(BR)DSX VO(ON) Single-Pulse Avalanche Energy Test Circuit and Waveforms EAS = IAS x V(BR)DSX x tAV/2 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com TERMINAL DESCRIPTIONS Terminal No. Terminal Name Function 1 NC No internal connection. 2 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V). 3 SERIAL DATA IN Serial-data input to the shift-register. 4-7 OUT0-3 Current-sinking, open-drain DMOS output terminals. 8 CLEAR When (active) low, the registers are cleared (set low). 9 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). 10 GROUND Reference terminal for output voltage measurements (OUT0-3). 11 GROUND Reference terminal for output voltage measurements (OUT0-7). 12 STROBE Data strobe input terminal; shift register data is latched on rising edge. 13 CLOCK Clock input terminal for data shift on rising edge. 14-17 OUT4-7 Current-sinking, open-drain DMOS output terminals. 18 SERIAL DATA OUT CMOS serial-data output to the following shift register. 19 GROUND Reference terminal for input voltage measurements. 20 NC No internal connection. NOTE — Grounds (terminals 10, 11, and 19) must be connected together externally. 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 A6B595KA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below. 0.014 0.008 0.300 BSC Dwg. MA-001-20 in 0.430 MAX 20 1 10 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 11 1.060 0.980 0.355 0.204 7.62 BSC Dwg. MA-001-20 mm 10.92 MAX 20 1 10 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 11 26.92 24.89 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com A6B595KLW Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-20 in 0.050 BSC 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.4961 0.0926 0.1043 0° TO 8° 1 20 2 30.51 0.33 0.10 MIN. Dwg. MA-008-20 mm 1.27 BSC 11 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.60 2.65 2.35 NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 This page intentionally left blank 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER www.allegromicro.com This page intentionally left blank 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.