PrimeTime 时序
分析
定性数据统计分析pdf销售业绩分析模板建筑结构震害分析销售进度分析表京东商城竞争战略分析
流程和方法
PrimeTime是Synopsys的一个单点的全芯片、门级静态时序分析器。它能分析大规模、同步、数字ASICS的时序。PrimeTime工作在设计的门级层次,并且和Synopsys其它工具整合得很紧密。
,m8F0u)D;|$l(G!Z*n9\bbs.dicder.com 基本特点和功能:DICDER,f5e&D6s3I(?
时序检查方面:
8\0n8y8H9z3g#P5u!?数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL建立和保持时序的检查(Setup and hold checks)
+h)b.P6v/A"k3}!Z1B(Q数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL重新覆盖和去除检查(Recovery and removal checks)
+i1z4I6O%YDigital IC Designer's forum时钟脉冲宽度检查(Clock pulse width checks)Digital IC Designer's forum#F3H(F'y#z#m(e5}.`
时钟门锁检查(Clock-gating checks)
(@8V$W"J$\3O6Ebbs.dicder.com 设计检查方面:
%`.V"C6v;|*\/VDICDER没有时钟端的寄存器&e9i9@8a$\&k!j;E(a2F#i
没有时序约束的结束点(endpoint)
9E!j4V6K(T:v(q数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL主从时钟分离(Master-slave clock separation)
;l3Z-C8`)z(D,n(_5c数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL有多哥时钟的寄存器bbs.dicder.com'g)W2i+J7h,D(G.X*e
对层次敏感的时钟(Level-sensitive clocking)
-x K$d:A.m(_+H.\1{Digital IC Designer's forum组合电路的反馈环(Combinational feedback loops)Digital IC Designer's forum*@6\(I:o#F:x+|'q
设计规则检查,包括最大电容(maximum capacitance)、最大传输时间(maximum transition)和最大扇出(maximum fanout)
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4D"p9e)^2obbs.dicder.comPrimeTime 时序分析流程和方法:0\5Q*i6X6q'T
在时序分析之前需要做的步骤:
4N,D3n9J3?Digital IC Designer's forum1、 建立设计环境
3s6h;n#p'V(L"]"J"f-nDigital IC Designer's forum- 建立搜索路径(search path)和链接路径(link path)数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL7K/]*N.a/P%E:W!e
- 读入设计和库数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL$V+o&d,['i.C#[+T)o
- 链接顶层设计数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL3W7C'b4U-^
- 建立运作条件、连线负载模型、端口负载、驱动和传输时间bbs.dicder.com"a:Q!j8~)k5`.R0j/b
2、 说明时序声明(约束)Digital IC Designer's forum-[#J;]"K.|3c*E9D5Y;L
- 定义时钟周期、波形、不确定性(uncertainty)和滞后时间(latency)Digital IC Designer's forum;N'q/[(B!f3L9E#w
- 说明输入、输出端口的延时
a/\6Y-~9a;k%s+Sbbs.dicder.com3、 说明时序例外情况(timing exceptions)(j(D,B)z'N
- 多周期路径(multicycle paths)数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&{!Q!z/J4}&h'C
- 不合法路径(false paths)
(H6i(V"q;J;K-n2@- 说明最大和最小延时、路径分割(path segmentation)和失效弧(disabled arcs)
/K"r.D(s([,c-j4、 进行分析和生成
报告
软件系统测试报告下载sgs报告如何下载关于路面塌陷情况报告535n,sgs报告怎么下载竣工报告下载
$q%g.{5m;F:u9D9h数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL- 检查时序数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL9t+Y5\6T8\8v"V*\-~
- 生成约束报告数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL9e-m!_'s d4R
- 生成路径时序报告数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL*G%O2~.x6D(j
7l,H2{#C'v!q8Z
开始数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5C"x5h3t!z:H)T9N q
先建立目录并将PrimeTime本身所带的一个例子拷到新建的目录下,在下面的内容中将要用到这个例子。数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL4~'H8H0k+c S
mkdir primetime
$q)s/~3V"?&LDICDERcd primetime数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL7P%a"e,m7q.?'x
cp –r $SYNOPSYS/doc/pt/tutorial .
&?&B*H%X,a1bcd tutorial
;{.j%W%P;r6~1|,[Digital IC Designer's forum确认目录中有以下这些文件:
,O8T'X/G!u!`-obbs.dicder.comAM2910.db The design .db for the top-level of the design
9e-A-O${8d:g;G(B'B&[CONTROL.db The design .db for the CONTROL block
#{.n"V4R-z4M)GDICDERREGCNT.db The design .db for the REGCNT blockbbs.dicder.com0}&`4{ M1N"g&E0M
UPC.db The design .db for the UPC block-D(U6A$F%S"_:l8t6Z+M
Y.data The Stamp data file for the Y block
5q"u+y-z'K;[数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLY.mod The Stamp model file for the Y block
+s4C3i,?7X6b-Q7v数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLY_lib.db The library .db for the Y blockbbs.dicder.com5o9b#C%_/b&t"p3@$r%r
STACK_lib.db The library .db for the STACK block数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL)E(y2t(Q+c5x7h.f*l
pt_lib.db The technology library .dbDigital IC Designer's forum;?8U+}&N+c'x0_8F
stack.qtm.pt The quick timing model script for the stack block
$U:["F$o,g,S.]/o%L4r/p:m数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLoptimize.dcsh The dc_shell optimization scriptDigital IC Designer's forum.C8w.J!F5_6x.G
timing.dcsh An example DC shell timing script for translationDigital IC Designer's forum"]6P*J2S7P1w6]+`3[
tutorial.pt The complete PrimeTime tutorial script for your数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL6G0[0@)I7y:u
reference.
,z:b,G7L)H*B(rDICDER
(Y2c,?0U4C数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL例子是一个AM2910微处理器,如图所示模块图。
9|)c6Z#S(R1B"C5PDigital IC Designer's forum [attachment=141] DICDER;D-@0l"^6^+h!x$E
bbs.dicder.com1h)T1m#M8t9F5V'M8I
运行PrimeTime:
!u,V6t'H8Q4i;|&[数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shellDICDER9A,@(b5D/m2C#Q
:G5y7T0s)nDigital IC Designer's forum定义搜索路径和链接路径:
N+x,q.U0o%H*^,sbbs.dicder.compt_shell>set search_path “.”数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL"k:|4u#z)V;r&X0p
Pt_shell>set link_path “* pt_lib.db STACK_lib.db Y_lib.db” z.Z6n;~:D1\+D)T9P1^%{
* pt_lib.db STACK_lib.db Y_lib.db:R&M+_*f"i*Z/e
数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL;r7v ?6N+@.e5D;o-|8F4|$e
读入设计:
8m#t5p2Q.y0@8[0s6x:zbbs.dicder.comPrimeTime支持以下设计格式:
!A,E%S%W e#[数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL. Synopsys database files (.db) (Use the read_db command)
&~*N/X(F;Y%I. Verilog netlist files (Use the read_verilog command)Digital IC Designer's forum-A&`5t$D2B)m
. Electronic Design Interchange Format (EDIF) netlist files (Use the read_edif command.)7t-K+]%r8D9k"_ H3I)M(M
. VHDL netlist files (Use the read_vhdl command.)Digital IC Designer's forum W.s4K'u;g%j:S2_
读入AM2910的顶层设计文件:数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&\%a6T7E;N:U,n%j
pt_shell> read_db AM2910.db r4o$?.g5F/p#V:^
Loading db file '/u/joe/primetime/tutorial/AM2910.db'数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL1`-a7b2V3w8x
1
7_*[3T N(?.f!`数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLDigital IC Designer's forum4m;a+J1I*?:p
链接设计:
$Q3a8h!~.j;j)J!?bbs.dicder.compt_shell> link_design AM2910
7D'B:\,U7@1E-e数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLLoading db file '/u/joe/primetime/tutorial/pt_lib.db'数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5|3_!z:q'P9G"l
Loading db file '/u/joe/primetime/tutorial/STACK_lib.db'
'M*l2j3E4~ U k%t1?.bLoading db file '/u/joe/primetime/tutorial/Y_lib.db'DICDER7~+d'B6n:G Y1c
Linking design AM2010 ...
1i3Q)w%F!m.I8tLoading db file '/u/joe/primetime/tutorial/STACK.db'数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL H!i$Y'L1E
...数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL+L1E#R2]4M*T r#M
Designs used to link AM2910:
#f%`$N2_6\/F/]CONTROL, REGCNT, STACK, UPC, Y;_!K$C:u5V)g ^
Libraries used to link AM2910:
5s;t6^#l.cDigital IC Designer's forumSTACK_lib, Y_lib, pt_lib
4]5i/_!~8R:{3s9}5i*r数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLDesign 'AM2910' was successfully linked
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;J M2J+_ h+Q-P'p$Q%b9}数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL显示当前已载入的设计:数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL.l4I O4|0u([6E.v3?
pt_shell>list_designs
6w)|$e.X2E/c;_5j'Z数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL得到当前载入单元的信息:
1R-a$n$^1G8X R9v6w1Cbbs.dicder.compt_shell>report_cell)c)j/O"N2d&C&y
数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL/G:r+H,d;d&g
编译一个标记模型(Stamp Model):
)];Z*K0B+G7m8J数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL标记模型是一个诸如像DSP或RAMS那样复杂模块的静态时序模型。
1x(L(h3o+}(g/`+n#o数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL标记模型与.lib模型共存,而不能代替它们。(W2f,P(j0}.N,N)x
- 建立标记模型是用在晶体管层次的设计上,在这个层次上没有门级网
表
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3n*r2F%^*i1z0W2j ]:x数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL- 标记模型语言是一种源代码语言,被编译成Synopsys的.db文件格式,可以被PrimeTime或Design Compiler使用。数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL;A-?9W-X'J.w2X-P
- 标记模型包含引脚到引脚的时序弧、建立和保持时间数据、模式信息、引脚的电容和驱动能力等等。标记模型还能保存属性(面积等等)。
$r-D-y2H/q'e6d1D2g"B数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL- 三态输出、锁存器和内部生成的时钟都可以被建模。Digital IC Designer's forum,e5`6d-z&Q1[+~:E
一个标记模型包括两种源代码文件格式:
%U(g,E8K3}.d数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL- .mod文件
&U5z(A0e"L*v数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL仅包含引脚到引脚的弧的描述(没有延时数据)。
$D5y$i*r2C.`6\- .data文件
4U1d4G,M7[,`'R#N'qDigital IC Designer's forum包含.mod文件中每条弧的延时数据。DICDER9f![-W"c-s w
标记模型可以有多个.data文件来描述不同运作条件下的时序。Digital IC Designer's forum(_)^!c/o6{6m"o!l V
两种文件格式都需要编译成一个.db模型。:G!]5I;[(y9D
0\"T#\&F7q#n'h0\数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL编译AM2910中Y模块的标记模型(标记源代码文件是Y.mod和Y.data):
#X'o8L"r,S:l数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shell> compile_stamp_model -model_file Y.mod \
;F R+Q&m)r数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-data_file Y.data -output Y数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL"@;[7R3m0^#U0r.t)^ [7M
Wrote model library core to ‘./Y_lib.db’
'h,y)y8T(c,H:B8_DICDERWrote model to ‘./Y.db’数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL/R5}-Y O){%] J&W2Q
PrimeTime生成两个.db文件:数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL2X1b4n;Y$R+t*o*w)v)N;J%y
Y_lib.db:一个库文件,包含一个单元(cell)。这个单元叫做核(core)。bbs.dicder.com7m(l/D#R9e!v
Y.db:一个设计文件,引用Y_lib.db中的单元核。
9v6{4E$i-s.H数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL
3U6H7B%Z,H(Xbbs.dicder.comDigital IC Designer's forum3h"b2D&x5a+[8]1]8b6c
编译一个快速时序模型(Quick Timing Model):数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL'H5r&F&g$Z-Z4e
可以为设计中还没有完成的模块建立一个快速时序模型,以使得完整的时序分析能够进行。通常的情形是:
7f&S%W2R*]数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL- 模块的HDL代码还没有完成时数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5j l9z*J)V2s
- 为了划分设计,在评估阶段为实际设计进行时序预测、约束估计时
,z#V9\3Q5Z(?#`7[- 模块的标记模型还没有完成时数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL8j!N%S$@(F1k
一个快速时序模型是一组PrimeTime命令,而不是一种语言。为了方便和文档化可以将它们写在一个脚本文件中,然后保存为.db的格式。在PrimeTime和Design Compile中快速时序模型很有用处。
&z,t3h$v)L+?)H数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL还可以将快速时序模型保存为标记模型,这是开始一个复杂标记模型的一种便利的方法。DICDER&l)l:]:{(r:S&e/r$A3G
例子中STACK模块的快速时序模型脚本文件是stack.qtm.pt,建立这个模型:数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL0L1O6S*p"@#P1R0h:_/P
pt_shell> source -echo stack.qtm.pt
$O.X*|$L1J+|3A&@bbs.dicder.com...(y:a R(i)F X9r9p8O5^
pt_shell> report_qtm_model;
"|.l ]0N*H+k0|9{(w,}Digital IC Designer's forum...Digital IC Designer's forum0g0T!R5e9g
pt_shell> save_qtm_model -output STACK -format db+c&I(t;M F;R'G8I;y:n
Wrote model library core to './STACK_lib.db'
8t!F2B"I.a C%tDICDERWrote model to './STACK.db'bbs.dicder.com2[!O8m+y2E/O8H#A*P
,S9[7J9r'j$i8c i&O
)g9J:c)a;Y,q1G1A"C#r数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL进行时序分析DICDER%g"j5u4D'?&d5b.f(B5}
配置运作环境
/i9? v6}*\%a E*t数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL!x"[5n*l$H9N;P4L
读入并链接AM2910设计:
8r'M,l5Y3M7^数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shell> set search_path "."
+d1w5^8I,n:?*b4n数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shell> set link_path "* pt_lib.db STACK_lib.db Y_lib.db"bbs.dicder.com1u%Q9C9i2|1a(J2q
pt_shell> read_db AM2910.db
6F2@.C9_8v3d)`数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shell> link_design AM2910
(|;A9e*]&e%\&B:F,w数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL链接了AM2910会导致其它已经链接的设计变为不链接的状态。在内存里只允许有一个链接的设计。当一个设计不链接,所有时序信息将被去除,并会出现警告,这和Design Compiler不同。如果需要保存所标注的信息,可以在链接一个新的设计之前用write_script命令。如果以后重新链接这个设计,只要运行这个脚本就可以了。数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL#s-r5t1M!{%O$x:X
9z7T%U*c0t建立运作条件和连线负载模型:
5`6V;X2e0p7~"I4D2w&_+J'k数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLPrimeTime在生成建立时序报告(setup timing reports)时使用最大(Maximum)运作条件和连线负载模型;在生成保持时序报告(hold timing reports)时使用最小(Minimum)运作条件和连线负载模型。Digital IC Designer's forum8^"w4I(o-M
pt_shell> set_operating_conditions -library pt_lib -min BCCOM -max WCCOMDICDER0s:x8K"M9O3T1O%w
pt_shell> set_wire_load_mode topbbs.dicder.com8@1n-s$h Q m9|-Q
pt_shell> set_wire_load_model -library pt_lib -name 05x05 -min
2?6a"n+|4l2H2~5{bbs.dicder.compt_shell> set_wire_load_model -library pt_lib -name 20x20 –max数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL8P3d"B/i;[#`*@-p
如果运作条件在两个不同的库中,用set_min_library命令来在最大库和最小库中建立联系。
:p ?2I&o6k8N6}&[ A:Gbbs.dicder.com得到一张库的列表:数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&S9B*m8E0X'n
pt_shell> list_librariesDICDER:w/s%`:A:[%i0I2Z9J
Library Registry:Digital IC Designer's forum3N'@8w;o9Y7M S7\
STACK_lib /home/gray/primetime/tutorial/
0i c(x8H&s1Sbbs.dicder.comSTACK_lib.db:STACK_lib
&`*i*~8D;w%w#pbbs.dicder.comY_lib /home/gray/primetime/tutorial/Y_lib.db:Y_lib
2N;~5D!J-a4BDICDER* pt_lib /home/gray/primetime/tutorial/
6v/V*v4l1t.G2@6iDigital IC Designer's forumpt_lib.db:pt_lib数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL(F2r/_+F*F8z
得到一个库的详细信息:
6U!|5y9T$Abbs.dicder.compt_shell>report_lib pt_lib
8q,i1}5{%k+g&{)rDICDER
4J3u c3m5~6x0P"u4`'_数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL基本声明:数字,集成电路,IC,FAQ,Design compiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5z2Z:?8I2z-}:M:^)d
pt_shell> create_clock -period 30 [get_ports CLOCK]
$f7y-m7D;`8Y1Y rDICDERpt_shell> set clock [get_clock CLOCK]bbs.dicder.com:u(E;N*p*s0H&g6r5E
pt