[精选]现代CMOS工艺基本流程

现代CMOS工艺基本流程现代CMOS工艺基本流程1SiliconSubstrateP+~2um~725umSiliconEpiLayerP−选择衬底晶圆的选择掺杂类型（N或P）电阻率（掺杂浓度）晶向高掺杂(P+)的Si晶圆低掺杂(P−)的Si外延层2SiliconSubstrateP+SiliconEpiLayerP−PadOxide热氧化热氧化形成一个SiO2薄层，厚度约20nm高温，H2O或O2气氛缓解后续步骤形成的Si3N4对Si衬底造成的应力3SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideSi3N4淀积Si3N4淀积厚度约250nm化学气相淀积(CVD)作为后续CMP的停止层4SiliconSubstrateP+SiliconEpiLayerP-SiliconNitridePhotoresist光刻胶成形光刻胶成形厚度约0.5~1.0um光刻胶涂敷、曝光和显影用于隔离浅槽的定义5SiliconSubstrateP+SiliconEpiLayerP-SiliconNitridePhotoresistSi3N4和SiO2刻蚀Si3N4和SiO2刻蚀基于氟的反应离子刻蚀(RIE)6SiliconSubstrateP+SiliconEpiLayerP-SiliconNitridePhotoresistTransistorActiveAreasIsolationTrenches隔离浅槽刻蚀隔离浅槽刻蚀基于氟的反应离子刻蚀(RIE)定义晶体管有源区7SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideTransistorActiveAreasIsolationTrenches除去光刻胶除去光刻胶氧等离子体去胶，把光刻胶成分氧化为气体8SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideFuturePMOSTransistorSiliconDioxideFutureNMOSTransistorNocurrentcanflowthroughhere!SiO2淀积SiO2淀积用氧化物填充隔离浅槽厚度约为0.5~1.0um，和浅槽深度和几何形状有关化学气相淀积(CVD)9SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideFuturePMOSTransistorFutureNMOSTransistorNocurrentcanflowthroughhere!化学机械抛光化学机械抛光(CMP)CMP除去 表 关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf 面的氧化层到Si3N4层为止10SiliconSubstrateP+SiliconEpiLayerP-FuturePMOSTransistorFutureNMOSTransistor除去Si3N4除去Si3N4热磷酸(H3PO4)湿法刻蚀，约180℃11TrenchOxideCrossSectionBareSilicon平面视图完成浅槽隔离(STI)12SiliconSubstrateP+SiliconEpiLayerP-FuturePMOSTransistorFutureNMOSTransistorPhotoresist光刻胶成形光刻胶成形厚度比较厚，用于阻挡离子注入用于N-阱的定义13SiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorPhotoresistN-WellPhosphorous(-)Ions磷离子注入磷离子注入高能磷离子注入形成局部N型区域，用于制造PMOS管14SiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorN-Well除去光刻胶15PhotoresistSiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorN-Well光刻胶成形光刻胶成形厚度比较厚，用于阻挡离子注入用于P-阱的定义16SiliconSubstrateP+SiliconEpiLayerP-PhotoresistN-WellBoron(+)IonsP-Well硼离子注入高能硼离子注入形成局部P型区域，用于制造NMOS管硼离子注入17SiliconSubstrateP+SiliconEpiLayerP-N-WellP-Well除去光刻胶18SiliconSubstrateP+SiliconEpiLayerP-P-WellN-Well退火退火在600~1000℃的H2环境中加热修复离子注入造成的Si表面晶体损伤注入杂质的电激活同时会造成杂质的进一步扩散快速加热工艺(RTP)可以减少杂质的扩散19TrenchOxideN-WellP-WellCrossSection完成N-阱和P-阱平面视图20SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSacrificialOxide牺牲氧化层生长牺牲氧化层生长厚度约25nm用来捕获Si表面的缺陷21SiliconSubstrateP+SiliconEpiLayerP-P-WellN-Well除去牺牲氧化层除去牺牲氧化层HF溶液湿法刻蚀剩下洁净的Si表面22SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellGateOxide栅氧化层生长栅氧化层生长工艺中最关键的一步厚度2~10nm要求非常洁净，厚度精确(±1Å)用作晶体管的栅绝缘层23SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPolysilicon多晶硅淀积多晶硅淀积厚度150~300nm化学气相淀积(CVD)24SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistChannelLengthPolysilicon光刻胶成形光刻胶成形工艺中最关键的图形转移步骤栅长的精确性是晶体管开关速度的首要决定因素使用最先进的曝光技术——深紫外光(DUV)光刻胶厚度比其他步骤薄25SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistChannelLength多晶硅刻蚀多晶硅刻蚀基于氟的反应离子刻蚀(RIE)必须精确的从光刻胶得到多晶硅的形状26SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellGateOxidePolyGateElectrode除去光刻胶27TrenchOxideN-WellP-WellCrossSectionPolysilicon平面视图完成栅极28SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellGateOxidePolyGateElectrodePolyRe-oxidation多晶硅氧化多晶硅氧化在多晶硅表面生长薄氧化层用于缓冲隔离多晶硅和后续步骤形成的Si3N429SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresist光刻胶成形光刻胶成形用于控制NMOS管的衔接注入30SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistArsenic(-)IonsNTipNMOS管衔接注入NMOS管衔接注入低能量、浅深度、低掺杂的砷离子注入衔接注入用于削弱栅区的热载流子效应31SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellNTip除去光刻胶32SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistNTip光刻胶成形光刻胶成形用于控制PMOS管的衔接注入33SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistBF2(+)IonsNTipPTipPMOS管衔接注入低能量、浅深度、低掺杂的BF2+离子注入衔接注入用于削弱栅区的热载流子效应PMOS管衔接注入34SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellNTipPTip除去光刻胶35SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSiliconNitrideThinnerHereThickerHereNTipPTipPTipSi3N4淀积Si3N4淀积厚度120～180nmCVD36SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSpacerSidewallNTipPTipPTipSi3N4刻蚀Si3N4刻蚀水平表面的薄层Si3N4被刻蚀，留下隔离侧墙侧墙精确定位晶体管源区和漏区的离子注入RIE37SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistNTipPTip光刻胶成形光刻胶成形用于控制NMOS管的源/漏区注入38SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistArsenic(-)IonsN+DrainN+SourcePTipNMOS管源/漏注入NMOS管源/漏注入浅深度、重掺杂的砷离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入39SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourcePTip除去光刻胶40SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourcePhotoresistPTip光刻胶成形光刻胶成形用于控制PMOS管的源/漏区注入41SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellBF2(+)IonsPhotoresistN+DrainN+SourceP+SourceP+DrainPMOS管源/漏注入PMOS管源/漏注入浅深度、重掺杂的BF2+离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入42SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+SourceP+DrainLightlyDoped“Tips”除去光刻胶和退火除去光刻胶和退火用RTP工艺，消除杂质在源/漏区的迁移43TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacer平面视图完成晶体管源/漏极，电子器件形成44SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+Source除去表面氧化物除去表面氧化物在HF溶液中快速浸泡，使栅、源、漏区的Si暴露出来45SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitaniumTi淀积Ti淀积厚度20~40nm溅射工艺Ti淀积在整个晶圆表面46SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitaniumSilicideUnreactedTitaniumTiSi2形成TiSi2形成RTP工艺，N2气氛，800℃在Ti和Si接触的区域，形成TiSi2其他区域的Ti没有变化称为自对准硅化物工艺(Salicide)47SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitaniumSilicideTi刻蚀Ti刻蚀NH4OH+H2O2湿法刻蚀未参加反应的Ti被刻蚀TiSi2保留下来，形成Si和金属之间的欧姆接触48SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGBPSG淀积硼磷硅玻璃(BPSG)淀积CVD，厚度约1umSiO2并掺杂少量硼和磷改善薄膜的流动性和禁锢污染物的性能这一层绝缘隔离器件和第一层金属49SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGBPSG抛光硼磷硅玻璃(BPSG)抛光CMP在BPSG层上获得一个光滑的表面50SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGPhotoresist光刻胶成形光刻胶成形用于定义接触孔(Contacts)这是一个关键的光刻步骤51SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGPhotoresist接触孔刻蚀接触孔刻蚀基于氟的RIE获得垂直的侧墙提供金属和底层器件的连接52SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSG除去光刻胶53SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGTitaniumNitrideTiN淀积TiN淀积厚度约20nm溅射工艺有助于后续的钨层附着在氧化层上54SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGTitaniumNitrideTungsten钨淀积钨淀积CVD厚度不少于接触孔直径的一半填充接触孔55SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlug钨抛光钨抛光CMP除去表面的钨和TiN留下钨塞填充接触孔56TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContact平面视图完成接触孔，多晶硅上的接触孔没有出现在剖面图上57SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1Ti(200Å)-electromigrationshuntTiN(500Å)-diffusionbarrierAl-Cu(5000Å)-mainconductorTiN(500Å)-antireflectivecoatingMetal1淀积第一层金属淀积(Metal1)实际上由多个不同的层组成溅射工艺58SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1Photoresist光刻胶成形光刻胶成形用于定义Metal1互连59SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistMetal1刻蚀Metal1刻蚀基于氯的RIE由于Metal1由多层金属组成，所以需要多个刻蚀步骤60SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1除去光刻胶61TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1平面视图完成第一层互连62SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1IMD淀积金属间绝缘体(IMD)淀积未掺杂的SiO2连续的CVD和刻蚀工艺，厚度约1um填充在金属线之间，提供金属层之间的绝缘隔离63SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1IMD抛光IMD抛光CMP64SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1Photoresist光刻胶成形光刻胶成形用于定义通孔(Vias)65SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistIMD1通孔刻蚀通孔刻蚀基于氟的RIE，获得垂直的侧墙提供金属层之间的连接66SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1除去光刻胶67TungstenSiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlugTiN和钨淀积TiN和钨淀积同第一层互连68SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlug钨和TiN抛光钨和TiN抛光同第一层互连69TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1Via1平面视图完成通孔70SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlugMetal2Metal2淀积Metal2淀积类似于Metal1厚度和宽度增加，连接更长的距离，承载更大的电流71SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistIMD1WViaPlugMetal2光刻胶成形光刻胶成形相邻的金属层连线方向垂直，减小层间的感应耦合72SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1PhotoresistIMD1WViaPlugMetal2Metal2刻蚀Metal2刻蚀类似于Metal173SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlugMetal2除去光刻胶74TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1Via1Metal2平面视图完成第二层互连，后面的剖面图将包括右上角的压焊点75SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlugPassivationMetal2钝化层淀积钝化层淀积多种可选的钝化层，Si3N4、SiO2和聚酰亚胺等保护电路免受刮擦、污染和受潮等76SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGWContactPlugMetal1IMD1WViaPlugPassivationBondPadPolyGateGateOxideSilicideSpacerMetal2钝化层成形钝化层成形压焊点打开，提供外界对芯片的电接触77CrossSectionTrenchOxideN+Source/DrainP+Source/DrainSpacerContactMetal1PolysiliconVia1+5VSupplyVOUTN-WellP-WellMetal2GroundBondPadVIN平面视图完成，显示了电气连接和部分压焊点78完成79略有不同的另一个工艺流程Vth校正注入场氧化层TiN80 演讲 办公室主任竞聘演讲中层竞聘演讲护士长竞聘演讲演讲比赛活动要求对演讲比赛的点评 完毕，谢谢观看！