VEGAS Soft Vector Processor with Scratchpad Memory拉斯维加斯的软向量处理器暂存存储器

VEGAS:SoftVectorProcessorwithScratchpadMemoryChristopherHan-YuChouAaronSeverance,AlexD.Brant,ZhiduoLiu,SaurabhSant,GuyLemieuxUniversityofBritishColumbiaMotivationEmbeddedprocessingonFPGAsHighperformance,computationallyintensiveSoftprocessors,e.g.Nios/MicroBlaze,tooslowHowtodeliverHighPerformance?MultiprocessoronFPGACustomHardwareaccelerators(VerilogRTL)Synthesizedaccelerators(CtoFPGA)MotivationSoftvectorprocessortotherescuePreviousworkshavedemonstratedsoftvectorprocessorasaviableoptiontoprovide:ScalableperformanceandareaPurelysoftware-basedDecoupleshardware/softwaredevelopmentKeyperformancebottlenecksMemoryaccesslatencyOn-chipdatastorageefficiencyContributionVEGASArchitecturekeyfeaturesCachelessScratchpadMemoryFracturableALUsConcurrentmemoryaccessviaDMAAdvantagesEliminateson-chipdatareplicationAlso:huge#ofvectors,longvectorlengthsMoreparallelALUsFewermemoryloads/storesVEGASArchitectureScalarCore:NiosII/f@200MHzDMAEngine&ExternalDDR2VectorCore:VEGAS@120MHzConcurrentExecutionFIFOsynchronizedVEGASScratchpadMemoryinActionVectorScratchpadMemoryVectorLane0VectorLane1VectorLane2VectorLane3srcAsrcBDestsrcAsrcBDestScratchpadMemoryinActionsrcADestScratchpadAdvantagePerformanceHugeworkingset(256kB++)ExplicitlymanagedbysoftwareAsyncload/storeviaconcurrentDMAEfficientdatastorageDouble-clockedmemory(Trad.RF2xcopies)8bdatastaysas8b(Trad.RF4xcopies)Nocache(Trad.RF+1copy)ScratchpadAdvantageAccessedbyaddressregisterHuge#ofvectorsinscratchpadVEGASusesonly8vectoraddr.reg.(V0..V7)ModifycontenttoaccessdifferentvectorsAuto-incrementlessensneedtochangeV0..V7LongvectorlengthsFillentirescratchpadScratchpadAdvantage:MedianFilterVectoraddressregisterseasierthanunrollingTraditionalVectorMedianFilterForJ=0..12ForI=J..24V1=vector[i]vectorloadV2=vector[j]vectorloadCompareAndSwap(V1,V2)vector[j]=V2vectorstoreVector[i]=V1vectorstoreOptimizeaway1vectorload+1vectorstoreusingtempTotalof222loadsand222storesScratchpadAdvantage:MedianFilterFracturableALUsMultiplier–uses4x16bmultipliersMultiplieralsodoesshifts+rotateAdder–uses4x8baddersFracturableALUsAdvantageIncreasedprocessingpower4-LaneVEGAS4x32boperations/cycle8x16boperations/cycle16x8boperations/cycleMedianfilterexample32bdata:184cycles/pixel16bdata:93cycles/pixel8bdata:47cycles/pixelAreaandFrequencyNum.LanesVEGASALMDSPM9KFmax13831840131248811240131469762040130811824364012516198436840122323661113240116ALMUsagePerformanceBenchmarkNiosII/fVEGASNiosII/V32SpeedupV1V32fir509919855494693108xmotest1668869825152471767xmedian13881857208xautocor12433845027282244xconven489883462189725ximgblend12311721758903548534xfilt3x365565928134717534987xArea-DelayProductArea*Delaymeasures“throughputpermm2”Comparedtoearliervectorprocessors,VEGASoffers2-3xbetterthroughputperunitareaIntegerMatrixMultiplyIntegerMatrixMultiply4096x4096integers(64MBdataset)IntelCore2(65nm),2.5GHz,16GBDDR2VanillaIJK:474secondsVanillaKIJ:134sTiledIJK:93sTiledKIJ:68sVEGAS(65nmAlteraStratix3)Vector:44s(Niosonly:5407s)256kBScratchpad,32Lanes(about50%ofchip)200MHzNIOS,100MHzVector,1GBDDR2SODIMMConclusionsVectorprocessorPurelysoftware-basedaccelerationNohardwaredesign/RTLrecompileneeded—justprogramFasterchipdesignCanbuildvectorprocessorbeforesoftwarealgorithmsfinalizedSimpleprogrammingmodelMapswelltoFPGAManysmallmemories,multiplierblocksShouldmapwelltoASICConclusionsKeyfeaturesScratchpadMemoryEnhanceperformancewithfewerloads/storesNoon-chipdatareplication;efficientstorageDouble-clockedtohidememorylatencyFracturableALUsOperateson8b,16b,32bdataefficientlySinglevectorcoreacceleratesmanyapplicationsResult2-3xbetterArea-DelayproductthanVIPERS/VESPAOutperformsIntelCore2atIntegerMatrixMultiplyIssues/FutureWorkNofloating-pointyetAdding“complexfunction”support,toincludefloating-pointorsimilaroperationsAlgorithmswithonlyshortvectorsSplitvectorprocessorinto2,4,8piecesRunmultipleinstancesofalgorithmMultiplevectorprocessorsConnectingthemtoworkcooperativelyGoals:increasethroughput,exploittask-levelparallelism(ie,chainingorpipelining)