湖南工业大学秒表eda实验报告

EDA实验报告学院：电气学院班级：学号姓名：实验六数字秒表的设计实验目的1）进一步熟悉掌握QuartusⅡ。2）进一步熟悉和掌握GW48-CK或其他EDA实验开发系统的应用。3）学习和掌握VHDL进程语句和元件例化语句的使用。实验内容设计并调试好数字秒表,并用GW48-CK或其他EDA实验开发系统进行硬件验证。实验条件1）开发软件：QuartusⅡ。2）实验设备：GW48-CKEDA实验开发系统。3）拟用芯片：EP3C55F484C8.实验设计1）系统原理框图本实验是由3MHZ~100HZ分频器、六进制计数器、十进制计数器、动态显示控制器CLKGEN、数据动态显示控制DISPLAY和数字秒表组成。数字秒表电路逻辑图2）VHDL程序--3MHZ~100HZ分频器CTRLS.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCTRLSISPORT(CLK:INSTD_LOGIC;SEL:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDENTITYCTRLS;ARCHITECTUREARTOFCTRLSISSIGNALCNT:STD_LOGIC_VECTOR(2DOWNTO0);BEGINPROCESS(CLK)ISBEGINIFCLK'EVENTANDCLK='1'THENIFCNT="111"THENCNT<="000";ELSECNT<=CNT+'1';ENDIF;ENDIF;ENDPROCESS;SEL<=CNT;ENDARCHITECTUREART;六进制计数器CNT6LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT6ISPORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;ENA:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);CO:OUTSTD_LOGIC);ENDENTITYCNT6;ARCHITECTUREARTOFCNT6ISSIGNALCQI:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,CLR,ENA)ISBEGINIFCLR='1'THENCQI<="0000";ELSIFCLK'EVENTANDCLK='1'THENIFENA='1'THENIFCQI="0101"THENCQI<="0000";ELSECQI<=CQI+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(CQI)ISBEGINIFCQI="0000"THENCO<='1';ELSECO<='0';ENDIF;ENDPROCESS;CQ<=CQI;ENDARCHITECTUREART;十进制计数器CNT10LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;ENA:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);CO:OUTSTD_LOGIC);ENDENTITYCNT10;ARCHITECTUREARTOFCNT10ISSIGNALCQI:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,CLR,ENA)ISBEGINIFCLR='1'THENCQI<="0000";ELSIFCLK'EVENTANDCLK='1'THENIFENA='1'THENIFCQI="1001"THENCQI<="0000";ELSECQI<=CQI+'1';ENDIF;ENDIF;ENDIF;ENDPROCESS;PROCESS(CLK,CQI)ISBEGINIFCLK'EVENTANDCLK='1'THENIFCQI<"1001"THENCO<='0';ELSECO<='1';ENDIF;ENDIF;ENDPROCESS;CQ<=CQI;ENDARCHITECTUREART;动态显示控制器CLKGENLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCLKGENISPORT(CLK:INSTD_LOGIC;NEWCLK:OUTSTD_LOGIC);ENDENTITYCLKGEN;ARCHITECTUREARTOFCLKGENISSIGNALCNT:INTEGERRANGE0TO10#29999#;BEGINPROCESS(CLK)ISBEGINIFCLK'EVENTANDCLK='1'THENIFCNT=10#29999#THENCNT<=0;ELSECNT<=CNT+1;ENDIF;ENDIF;ENDPROCESS;PROCESS(CNT)ISBEGINIFCNT=10#29999#THENNEWCLK<='1';ELSENEWCLK<='0';ENDIF;ENDPROCESS;ENDARCHITECTUREART;数据动态显示控制器DISPLAYLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYDISPLAYISPORT(SEL:INSTD_LOGIC_VECTOR(2DOWNTO0);DATAIN:INSTD_LOGIC_VECTOR(23DOWNTO0);COM:OUTSTD_LOGIC_VECTOR(7DOWNTO0);SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDISPLAY;ARCHITECTUREARTOFDISPLAYISSIGNALDATA:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(SEL)ISBEGINCASESELISWHEN"000"=>COM<="11111110";WHEN"001"=>COM<="11111101";WHEN"010"=>COM<="11111011";WHEN"011"=>COM<="11110111";WHEN"100"=>COM<="11101111";WHEN"101"=>COM<="11011111";WHEN"110"=>COM<="10111111";WHEN"111"=>COM<="01111111";WHENOTHERS=>COM<="11111111";ENDCASE;ENDPROCESS;PROCESS(SEL)ISBEGINCASESELISWHEN"000"=>DATA<=DATAIN(3DOWNTO0);WHEN"001"=>DATA<=DATAIN(7DOWNTO4);WHEN"010"=>DATA<=DATAIN(11DOWNTO8);WHEN"011"=>DATA<=DATAIN(15DOWNTO12);WHEN"100"=>DATA<=DATAIN(19DOWNTO16);WHEN"101"=>DATA<=DATAIN(23DOWNTO20);WHENOTHERS=>DATA<="0000";ENDCASE;CASEDATAISWHEN"0000"=>SEG<="00111111";--3FHWHEN"0001"=>SEG<="00000110";--06HWHEN"0010"=>SEG<="01011011";--5BHWHEN"0011"=>SEG<="01001111";--4FHWHEN"0100"=>SEG<="01100110";--66HWHEN"0101"=>SEG<="01101101";--6DHWHEN"0110"=>SEG<="01111101";--7DHWHEN"0111"=>SEG<="00000111";--07HWHEN"1000"=>SEG<="01111111";--7FHWHEN"1001"=>SEG<="01101111";--6FHWHENOTHERS=>SEG<="00000000";--00HENDCASE;ENDPROCESS;ENDARCHITECTUREART;数字秒表TIMES--TIMES.VHDLLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYTIMESISPORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;ENA:INSTD_LOGIC;CLK2:INSTD_LOGIC;COM:OUTSTD_LOGIC_VECTOR(7DOWNTO0);SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0);DOUT1:OUTSTD_LOGIC_VECTOR(23DOWNTO0));ENDENTITYTIMES;ARCHITECTUREARTOFTIMESISCOMPONENTCLKGENISPORT(CLK:INSTD_LOGIC;NEWCLK:OUTSTD_LOGIC);ENDCOMPONENTCLKGEN;COMPONENTCNT10ISPORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;ENA:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);CO:OUTSTD_LOGIC);ENDCOMPONENTCNT10;COMPONENTCNT6ISPORT(CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;ENA:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);CO:OUTSTD_LOGIC);ENDCOMPONENTCNT6;COMPONENTCTRLSISPORT(CLK:INSTD_LOGIC;SEL:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDCOMPONENTCTRLS;COMPONENTDISPLAYISPORT(SEL:INSTD_LOGIC_VECTOR(2DOWNTO0);DATAIN:INSTD_LOGIC_VECTOR(23DOWNTO0);COM:OUTSTD_LOGIC_VECTOR(7DOWNTO0);SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENTDISPLAY;SIGNALS0:STD_LOGIC;SIGNALS1,S2,S3,S4,S5:STD_LOGIC;SIGNALS:STD_LOGIC_VECTOR(2DOWNTO0);SIGNALDOUT:STD_LOGIC_VECTOR(23DOWNTO0);BEGINU0:CLKGENPORTMAP(CLK=>CLK,NEWCLK=>S0);U1:CNT10PORTMAP(S0,CLR,ENA,DOUT(3DOWNTO0),S1);U2:CNT10PORTMAP(S1,CLR,ENA,DOUT(7DOWNTO4),S2);U3:CNT10PORTMAP(S2,CLR,ENA,DOUT(11DOWNTO8),S3);U4:CNT6PORTMAP(S3,CLR,ENA,DOUT(15DOWNTO12),S4);U5:CNT10PORTMAP(S4,CLR,ENA,DOUT(19DOWNTO16),S5);U6:CNT6PORTMAP(S5,CLR,ENA,DOUT(23DOWNTO20));U10:CTRLSPORTMAP(CLK2,S(2DOWNTO0));U11:DISPLAYPORTMAP(S,DOUT,COM,SEG);DOUT1<=DOUT;ENDARCHITECTUREART;3）管脚锁定如图4）编程下载及验证连接好下载电缆，打开电源。执行【Tool】→【Programmer】命令，打开编程下载窗口，进行有关选择设置之后在执行编程下载。5）硬件执行结果如图6）仿真图形7）RTL图形8）经验与 总结 初级经济法重点总结下载党员个人总结TXt高中句型全总结.doc高中句型全总结.doc理论力学知识点总结pdf 本次实验在进行仿真的时候，刚开始大家都只看到SEG输出的是3F，也就是0，都弄不清楚到底是哪里出了问 题 快递公司问题件快递公司问题件货款处理关于圆的周长面积重点题型关于解方程组的题及答案关于南海问题 ，于是老师建议我们加上一个DOUT输出口，对计数器的输出进行观察。在加入了DOUT输出口之后，根据DOUT的显示我们清楚的看到了SEG的变化，原来是DOUT信号变化太快，SEG才难以看清楚。