tsc2046

FEATURES � SAME PINOUT AS ADS7846 � 2.2V TO 5.25V OPERATION � 1.5V TO 5.25V DIGITAL I/O � INTERNAL 2.5V REFERENCE � DIRECT BATTERY MEASUREMENT (0V TO 6V) � ON-CHIP TEMPERATURE MEASUREMENT � TOUCH-PRESSURE MEASUREMENT � QSPI AND SPI 3-WIRE INTERFACE � AUTO POWER-DOWN � AVAILABLE IN TSSOP-16, QFN-16, AND VFBGA-48 PACKAGES APPLICATIONS � PERSONAL DIGITAL ASSISTANTS � PORTABLE INSTRUMENTS � POINT-OF-SALE TERMINALS � PAGERS � TOUCH SCREEN MONITORS � CELLULAR PHONES US Patent No. 6246394 QSPI and SPI are registered trademarks of Motorola. DESCRIPTION The TSC2046 is a next-generation version to the ADS7846 4-wire touch screen controller which supports a low-voltage I/O interface from 1.5V to 5.25V. The TSC2046 is 100% pin-compatible with the existing ADS7846, and will drop into the same socket. This allows for easy upgrade of current applications to the new version. The TSC2046 also has an on-chip 2.5V reference that can be used for the auxiliary input, battery monitor, and temperature measurement modes. The reference can also be powered down when not used to conserve power. The internal reference operates down to 2.7V supply voltage, while monitoring the battery voltage from 0V to 6V. The low-power consumption of < 0.75mW typ at 2.7V (reference off), high-speed (up to 125kHz sample rate), and on-chip drivers make the TSC2046 an ideal choice for battery-operated systems such as personal digital assistants (PDAs) with resistive touch screens, pagers, cellular phones, and other portable equipment. The TSC2046 is available in TSSOP-16, QFN-16, and VFBGA-48 packages and is specified over the –40°C to +85°C temperature range. CDAC Internal 2.5V Reference SAR TSC2046 Comparator 6− Channel MUX Serial Data In/Out Temperature Sensor Pen Detect Battery Monitor DOUT BUSY CS DCLK DIN VBAT AUX VREF +VCC IOVDD X+ X− Y+ Y− PENIRQ TSC2046 SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 Low Voltage I/O TOUCH SCREEN CONTROLLER ��������� � � �� �������� �� ������� �� � ����������� ����� �������� ��� ��� �� ����� �������� ��� ��� ����� � ����� ����������� �������� ��������� ���������� ���������! ���� ��� ����������� ������� ������! � ��� ����������� www.ti.com Copyright  2002−2007, Texas Instruments Incorporated All trademarks are the property of their respective owners. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 2 ABSOLUTE MAXIMUM RATINGS(1) +VCC and IOVDD to GND −0.3V to +6V. . . . . . . . . . . . . . . . . . . . . Analog Inputs to GND −0.3V to +VCC + 0.3V. . . . . . . . . . . . . . . . . Digital Inputs to GND −0.3V to IOVDD + 0.3V. . . . . . . . . . . . . . . . . Power Dissipation 250mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature +150°C. . . . . . . . . . . . . . . . . . . . . . Operating Temperature Range −40°C to +85°C. . . . . . . . . . . . . . . . Storage Temperature Range −65°C to +150°C. . . . . . . . . . . . . . . . . Lead Temperature (soldering, 10s) +300°C. . . . . . . . . . . . . . . . . . . . . (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT NOMINAL PENIRQ PULLUP RESISTOR VALUES MAXIMUM INTEGRAL LINEARITY ERROR (LSB) PACKAGE- LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TSSOP-16 PW −40°C to +85°C TSC2046I TSC2046IPW Rails, 100 TSSOP-16 PW −40°C to +85°C TSC2046I TSC2046IPWR Tape and Reel, 2500 4x4, 1mm TSC2046IRGVT Tape and Reel, 250 TSC2046I 50kΩ ±2 4x4, 1mm QFN-16 RGV −40°C to +85°C TSC2046 TSC2046IRGVR Tape and Reel, 2500TSC2046I 50kΩ ±2 QFN-16 RGV −40 C to +85 C TSC2046 TSC2046IRGVRG4 Tape and Reel, 2500 4x4 GQC −40°C to +85°C AZ2046 TSC2046IGQCR Tape and Reel, 2500 4x4 VFBGA-48 ZQC −40°C to +85°C BC2046 TSC2046IZQCT Tape and Reel, 250 VFBGA-48 ZQC −40°C to +85°C BC2046 TSC2046IZQCR Tape and Reel, 2500 TSC2046I(2) 90kΩ ±2 4x4 GQC −40°C to +85°C AZ2046A TSC2046IGQCR-90 Tape and Reel, 2500 TSC2046I(2) 90kΩ ±2 4x4VFBGA-48 ZQC −40°C to +85°C BC2046A TSC2046IZQCR-90 Tape and Reel, 2500 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at www.ti.com. (2) High-impedance version. �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 3 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, and +VCC must be • IOVDD, unless otherwise noted. TSC2046 PARAMETER CONDITION MIN TYP MAX UNITS ANALOG INPUT Full-Scale Input Span Positive Input−Negative Input 0 VREF V Absolute Input Range Positive Input −0.2 +VCC + 0.2 V Negative Input −0.2 +0.2 V Capacitance 25 pF Leakage Current 0.1 µA SYSTEM PERFORMANCE Resolution 12 Bits No Missing Codes 11 Bits Integral Linearity Error ±2 LSB(1) Offset Error ±6 LSB Gain Error External VREF ±4 LSB Noise Including Internal VREF 70 µVrms Power-Supply Rejection 70 dB SAMPLING DYNAMICS Conversion Time 12 CLK Cycles Acquisition Time 3 CLK Cycles Throughput Rate 125 kHz Multiplexer Settling Time 500 ns Aperture Delay 30 ns Aperture Jitter 100 ps Channel-to-Channel Isolation VIN = 2.5VPP at 50kHz 100 dB SWITCH DRIVERS On-Resistance Y+, X+ 5 Ω Y−, X− 6 Ω Drive Current(2) Duration 100ms 50 mA REFERENCE OUTPUT Internal Reference Voltage 2.45 2.50 2.55 V Internal Reference Drift 15 ppm/°C Quiescent Current 500 µA REFERENCE INPUT Range 1.0 +VCC V Input Impedance SER/DFR = 0, PD1 = 0 1 GΩ Internal Reference Off Internal Reference On 250 Ω BATTERY MONITOR Input Voltage Range 0.5 6.0 V Input Impedance Sampling Battery 10 kΩ Battery Monitor Off 1 GΩ Accuracy VBAT = 0.5V to 5.5V, External VREF = 2.5V −2 +2 % VBAT = 0.5V to 5.5V, Internal Reference −3 +3 % TEMPERATURE MEASUREMENT Temperature Range −40 +85 °C Resolution Differential Method(3) 1.6 °C TEMP0(4) 0.3 °C Accuracy Differential Method(3) ±2 °C TEMP0(4) ±3 °C (1) LSB means Least Significant Bit. With VREF = +2.5V, one LSB is 610µV.(2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary. (4) Temperature drift is −2.1mV/°C. (5) TSC2046 operates down to 2.2V. (6) IOVDD must be − (+VCC).(7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0. �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 4 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (continued) At TA = −40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, digital inputs = GND or IOVDD, and +VCC must be • IOVDD, unless otherwise noted. TSC2046 PARAMETER UNITSMAXTYPMINCONDITION DIGITAL INPUT/OUTPUT Logic Family CMOS Capacitance All Digital Control Input Pins 5 15 pF VIH | IIH | ≤ +5µA IOVDD • 0.7 IOVDD + 0.3 V VIL | IIL | ≤ +5µA −0.3 0.3 • IOVDD V VOH IOH = −250µA IOVDD • 0.8 V VOL IOL = 250µA 0.4 V Data Format StraightBinary POWER-SUPPLY REQUIREMENTS +VCC(5) Specified Performance 2.7 3.6 V Operating Range 2.2 5.25 V IOVDD(6) 1.5 +VCC V Quiescent Current(7) Internal Reference Off 280 650 µA Internal Reference On 780 µA fSAMPLE = 12.5kHz 220 µA Power-Down Mode with 3 µA CS = DCLK = DIN = IOVDD Power Dissipation +VCC = +2.7V 1.8 mW TEMPERATURE RANGE Specified Performance −40 +85 °C (1) LSB means Least Significant Bit. With VREF = +2.5V, one LSB is 610µV.(2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary. (4) Temperature drift is −2.1mV/°C. (5) TSC2046 operates down to 2.2V. (6) IOVDD must be − (+VCC).(7) Combined supply current from +VCC and IOVDD. Typical values obtained from conversions on AUX input with PD0 = 0. �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 5 PIN CONFIGURATION Top View 1 2 3 4 5 6 7 8 +VCC X+ Y+ X− Y− GND VBAT AUX DCLK CS DIN BUSY DOUT PENIRQ IOVDD VREF 16 15 14 13 12 11 10 9 TSC2046 Top View QFN TSSOP Top View VFBGA NC NCA B C D E F G 21 3 4 5 6 7 DCLK +VCC +VCC X+ Y+ PENIRQ IOVDD VREF AUX CS DIN BUSY DOUT X− Y− GND GND VBAT NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NCNC NC BUSY DIN CS DCLK AUX VBAT GND Y− 1 2 3 4 12 11 10 9 TSC2046 D O UT PE NI R Q IO VD D V R EF 16 15 14 13 + V C C X+ Y+ X − 5 6 7 8 (1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. (Thermal Pad)(1) PIN DESCRIPTION TSSOP PIN # VFBGA PIN # QFN PIN # NAME DESCRIPTION 1 B1 and C1 5 +VCC Power Supply 2 D1 6 X+ X+ Position Input 3 E1 7 Y+ Y+ Position Input 4 G2 8 X− X− Position Input 5 G3 9 Y− Y− Position Input 6 G4 and G5 10 GND Ground 7 G6 11 VBAT Battery Monitor Input 8 E7 12 AUX Auxiliary Input to ADC 9 D7 13 VREF Voltage Reference Input/Output 10 C7 14 IOVDD Digital I/O Power Supply 11 B7 15 PENIRQ Pen Interrupt 12 A6 16 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is highimpedance when CS is high. 13 A5 1 BUSY Busy Output. This output is high impedance when CS is high. 14 A4 2 DIN Serial Data Input. If CS is low, data is latched on the rising edge of DCLK. 15 A3 3 CS Chip Select Input. Controls conversion timing and enables the serial input/output register.CS high = power-down mode (ADC only). 16 A2 4 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serialdata I/O. �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 6 TYPICAL CHARACTERISTICS At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. +VCC SUPPLY CURRENT vs TEMPERATURE −40 −20 0 20 40 60 80 100 + V C C Su pp ly Cu rr en t(µ A) 400 350 300 250 200 150 100 Temperature (°C) IOVDD SUPPLY CURRENT vs TEMPERATURE −40 −20 0 20 40 60 80 100 IO VD D Su pp ly Cu rr en t(µ A) 30 25 20 15 10 5 Temperature (°C) POWER−DOWN SUPPLY CURRENT vs TEMPERATURE −40 −20 0 20 40 60 80 100 Su pp ly Cu rr en t(n A) 140 120 100 80 60 40 Temperature (°C) +VCC SUPPLY CURRENT vs +VCC 2.0 2.5 3.0 3.5 4.0 4.5 5.0 +VCC (V) + V C C Su pp ly Cu rr en t(µ A) 450 400 350 300 250 200 150 100 fSAMPLE = 125kHz fSAMPLE = 12.5kHz IOVDD SUPPLY CURRENT vs IOVDD 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IOVDD (V) IO VD D Su pp ly Cu rr en t(µ A) 60 50 40 30 20 10 0 +VCC ≥ IOVDD fSAMPLE = 125kHz fSAMPLE = 12.5kHz MAXIMUM SAMPLE RATE vs +VCC 2.0 5.02.5 3.0 3.5 4.0 4.5 +VCC (V) Sa m pl e R at e (H z) 1M 100k 10k 1k �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 7 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. CHANGE IN GAIN vs TEMPERATURE −40 −20 0 20 40 60 80 100 0.15 0.10 0.05 0 −0.05 −0.10 −0.15 Temperature (°C) De lta fr om + 25 ° C (LS B) CHANGE IN OFFSET vs TEMPERATURE −40 −20 0 20 40 60 80 100 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 Temperature (°C) De lta fr om + 25 ° C (LS B) REFERENCE CURRENT vs SAMPLE RATE 0 25 50 75 100 125 Sample Rate (kHz) R ef er en ce Cu rr e nt (µ A ) 14 12 10 8 6 4 2 0 Temperature (°C) REFERENCE CURRENT vs TEMPERATURE −40 −20 0 20 40 60 80 100 R ef er e nc e Cu rr e n t(µ A) 18 16 14 12 10 8 6 SWITCH ON− RESISTANCE vs +VCC (X+, Y+: +VCC to Pin; X−, Y−: Pin to GND) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 +VCC (V) 8 7 6 5 4 3 Y− X− X+, Y+ R O N (Ω ) SWITCH ON−RESISTANCE vs TEMPERATURE (X+, Y+: +VCC to Pin; X−, Y−: Pin to GND) −40 −20 0 20 40 60 80 100 8 7 6 5 4 3 2 1 Y− X− X+, Y+ Temperature (°C) R O N (Ω ) �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 8 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 M ax Ab so lu te D el ta Er ro r fro m R IN = 0 (LS B) 20 40 60 80 100 120 140 160 180 200 Sampling Rate (kHz) MAXIMUM SAMPLING RATE vs RIN INL: RIN = 500Ω INL: RIN = 2kΩ DNL: RIN = 500Ω DNL: RIN = 2kΩ INTERNAL VREF vs TEMPERATURE − 40 − 35 − 30 − 25 − 20 − 15 − 10 − 5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 In te rn al V R EF (V ) 2.5080 2.5075 2.5070 2.5065 2.5060 3.5055 2.5050 2.5045 2.5040 2.5035 2.5030 Temperature (°C) INTERNAL VREF vs +VCC 2.5 3.0 3.5 4.0 4.5 5.0 +VCC (V) In te rn al V R EF (V ) 2.510 2.505 2.500 2.495 2.490 2.485 2.480 INTERNAL VREF vs TURN−ON TIME 0 200 400 600 800 1000 1200 1400 In te rn a lV R EF (% ) 100 80 60 40 20 0 Turn-On Time (µs) 1µF Cap (124µs) 12-Bit Settling No Cap (42µs) 12-Bit Settling TEMP DIODE VOLTAGE vs TEMPERATURE − 40 − 35 − 30 − 25 − 20 − 15 − 10 − 5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 TE M P D io de Vo lta ge (m V) 850 800 750 700 650 600 550 500 450 90.1mV 135.1mV TEMP1 TEMP0 Temperature (°C) TEMP0 DIODE VOLTAGE vs +VCC 2.7 3.0 3.3 +VCC (V) TE M P0 D io de Vo lta ge (m V) 604 602 600 598 596 594 �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 9 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VCC = +2.7V, IOVDD = +1.8V, VREF = External +2.5V, 12-bit mode, PD0 = 0, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. TEMP1 DIODE VOLTAGE vs +VCC 2.7 3.0 3.3 +VCC (V) TE M P1 D io de Vo lta ge (m V) 720 718 716 714 712 710 THEORY OF OPERATION The TSC2046 is a classic successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on capacitive redistribution, which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µm CMOS process. The basic operation of the TSC2046 is shown in Figure 1. The device features an internal 2.5V reference and uses an external clock. Operation is maintained from a single supply of 2.7V to 5.25V. The internal reference can be overdriven with an external, low-impedance source between 1V and +VCC. The value of the reference voltage directly sets the input range of the converter. The analog input (X-, Y-, and Z-Position coordinates, auxiliary input, battery voltage, and chip temperature) to the converter is provided via a multiplexer. A unique configuration of low on-resistance touch panel driver switches allows an unselected ADC input channel to provide power and the accompanying pin to provide ground for an external device, such as a touch screen. By maintaining a differential input to the converter and a differential reference architecture, it is possible to negate the error from each touch panel driver switch’s on-resistance (if this is a source of error for the particular measurement). +VCC +VCC X+ Y+ X− Y− VBAT AUX B1 C1 D1 E1 G2 G3 G6 E7 G4 G5 A2 A3 A4 A5 A6 B7 C7 D7 DCLK CS DIN BUSY DOUT PENIRQ IOVDD VREF Serial/Conversion Clock Chip Select Serial Data In Converter Status Serial Data Out + 1∝F to 10∝F (Optional) +2.7V to +5V TSC2046 Auxiliary Input To Battery Voltage Regulator Touch Screen 0.1∝F Pen Interrupt GND GND NOTE: VFBGA package and pin names shown. Figure 1. Basic Operation of the TSC2046 �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 10 ANALOG INPUT Figure 2 shows a block diagram of the input multiplexer on the TSC2046, the differential input of the ADC, and the differential reference of the converter. Table 1 and Table 2 show the relationship between the A2, A1, A0, and SER/DFR control bits and the configuration of the TSC2046. The control bits are provided serially via the DIN pin—see the Digital Interface section of this data sheet for more details. When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (shown in Figure 2) is captured on the internal capacitor array. The input current into the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor is fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. ADC Logic Level Shifter −REF +REF +IN −IN VBAT AUX Battery On GND 2.5V Reference Ref On/Off X+ X− +VCC TEMP1 PENIRQ 50kΩ or 90kΩ Y+ Y− VREFIOVDD TEMP0 7.5kΩ 2.5kΩ A2− A0 (Shown 001B) SER/DFR (Shown Low) Figure 2. Simplified Diagram of Analog Input A2 A1 A0 VBAT AUXIN TEMP Y− X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS Y-DRIVERS 0 0 0 +IN (TEMP0) Off Off 0 0 1 +IN Measure Off On 0 1 0 +IN Off Off 0 1 1 +IN Measure X−, On Y+, On 1 0 0 +IN Measure X−, On Y+, On 1 0 1 +IN Measure On Off 1 1 0 +IN Off Off 1 1 1 +IN (TEMP1) Off Off Table 1. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high) A2 A1 A0 +REF −REF Y− X+ Y+ Y-POSITION X-POSITION Z1-POSITION Z2-POSITION DRIVERS 0 0 1 Y+ Y− +IN Measure Y+, Y− 0 1 1 Y+ X− +IN Measure Y+, X− 1 0 0 Y+ X− +IN Measure Y+, X− 1 0 1 X+ X− +IN Measure X+, X− Table 2. Input Configuration (DIN), Differential Reference Mode (SER/DFR low) �"�#$%& SBAS265F − OCTOBER 2002 − REVISED AUGUST 2007 www.ti.com 11 INTERNAL REFERENCE The TSC2046 has an internal 2.5V voltage reference that can be turned on or off with the control bit, PD1 (see Table 5 and Figure 3). Typically, the internal reference voltage is only used in the single-ended mode for battery monitoring, temperature measurement, and for using the auxiliary input. Optimal touch screen performance is achieved when using the differential mode. The internal reference voltage of the TSC2046 must be commanded to be off to maintain compatibility with the ADS7843. Therefore, after power-up, a write of PD1 = 0 is required to insure the reference is off (see the Typical Characteristics for power-up time of the reference from power-down). Buffer Band Gap Reference Power−Down To CDAC Optional VREF Figure 3. Simplified Diagram of the Internal Reference REFERENCE INPUT The voltage difference between +REF and –REF (see Figure 2) sets the analog input range. The TSC2046 operates with a reference in the range of 1V to +VCC. There are several critical items concerning the reference