74LVC4245A

DATA SHEET Product specification Supersedes data of 1998 Jul 29 File under Integrated Circuits, IC24 1999 Jun 15 INTEGRATED CIRCUITS 74LVC4245A Octal dual supply translating transceiver; 3-state 查询74LVC4245A供应商 1999 Jun 15 2 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A FEATURES • In accordance with JEDEC standard no. 8-1A • Wide supply voltage range: 3 V port: 1.5 to 3.6 V 5 V port: 1.5 to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Control inputs accept voltages up to 5.5 V. DESCRIPTION The 74LVC4245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 and 5 V bus in a mixed 3/5 V supply environment. The 74LVC4245A features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. (OE) controls the outputs so that the buses are effectively isolated. In suspend mode, when VCCA is zero, there will be no current flow from one supply to the other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typ. 0.7 V). VCCA ≥ VCCB (except in suspend mode). QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; Σ(CL × VCC2 × fo) = sum of the outputs. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay CL = 50 pF An to Bn VCCA = 5.0 V 4.0 ns Bn to An VCCB = 3.3 V 4.0 ns CI/O input/output capacitance 10.0 pF CPDA A port An to Bn VI = GND to VCC; note 1 7.8 pF Bn to An VI = GND to VCC; note 1 27.9 pF CPDB B port An to Bn VI = GND to VCC; note 1 26 pF Bn to An VI = GND to VCC; note 1 10.4 pF 1999 Jun 15 3 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION PINNING INPUT INPUT/OUTPUT OE DIR An Bn L L A = B inputs L H inputs B = A H X Z Z OUTSIDE NORTH AMERICA NORTH AMERICA PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC4245AD 74LVC4245AD −40 to +85 °C 24 SO plastic SOT137-1 74LVC4245ADB 74LVC4245ADB 24 SSOP plastic SOT340-1 74LVC4245APW 74LVC4245ADH 24 TSSOP plastic SOT355-1 PIN SYMBOL DESCRIPTION 1 VCCA DC supply voltage (5 V bus) 2 DIR direction control 3, 4, 5, 6, 7, 8, 9 and 10 A0 to A7 data inputs/outputs 11, 12 and 13 GND ground (0 V) 14, 15, 16, 17, 18, 19, 20 and 21 B7 to B0 data inputs/outputs 22 OE output enable input (active LOW) 23 and 24 VCCB DC supply voltage (3 V bus) 1999 Jun 15 4 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A Fig.1 Pin configuration. handbook, halfpage VCCA GND VCCB GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 4245 MNA451 DIR A0 A1 A2 A3 A4 A5 A6 A7 GND VCCB OE B0 B1 B3 B4 B2 B5 B6 B7 Fig.2 Logic symbol. handbook, halfpage 3 2 DIR 21 22 B0 B1 B2 B3 B4 B5 B6 B7 4 20 5 19 6 18 7 17 8 16 9 15 10 A0 A1 A2 A3 A4 A5 A6 A7 14 OE MNA453 Fig.3 IEC logic symbol. handbook, halfpage 20 3 2 22 2 1 19 4 18 5 17 6 16 7 15 8 14 9 21 G3 3EN1 3EN2 10 MNA452 1999 Jun 15 5 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A RECOMMENDED OPERATING CONDITIONS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. SYMBOL PARAMETER CONDITIONS LIMITS UNIT MIN. MAX. VCCA DC supply voltage 5 V port (for maximum speed performance) VCCA ≥ VCCB (see Fig.5) 1.5 5.5 V VCCB DC supply voltage 3 V port (for low-voltage applications) VCCA ≥ VCCB (see Fig.5) 1.5 3.6 V VI DC input voltage range (control inputs) 0 5.5 V VI/O DC input voltage range; output 3-state 0 5.5 V DC output voltage range; output HIGH or LOW state 0 VCC V Tamb operating ambient temperature range see DC and AC characteristics per device −40 +85 °C tr,tf input rise and fall times VCCB = 2.7 to 3.0 V 0 20 ns/V VCCB = 3.0 to 3.6 V 0 10 VCCA = 3.0 to 4.5 V 0 20 VCCA = 4.5 to 5.5 V 0 10 SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA DC supply voltage 5 V port −0.5 +6.5 V VCCB DC supply voltage 3 V port −0.5 +4.6 V IIK DC input diode current VI < 0 − −50 mA VI DC input voltage note 1 −0.5 +6.5 V IOK DC output diode current VO > VCC or VO < 0 − ±50 mA VI/O DC output voltage; output HIGH or LOW note 1 −0.5 VCC + 0.5 V DC input voltage; output 3-state note 1 −0.5 +6.5 V IO DC output diode current VO = 0 to VCC − ±50 mA IGND, ICC DC VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation per package plastic mini-pack (SO) above 70 °C derate linearly with 8 mW/K − 500 mW plastic shrink mini-pack (SSOP and TSSOP) above 60 °C derate linearly with 5.5 mW/K − 500 mW 1999 Jun 15 6 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A DC CHARACTERISTICS Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). Notes 1. All typical values are at VCCA = 5.0 V, VCCB = 3.3 V and Tamb = 25 °C. 2. Not for I/O pins. SYMBOL PARAMETER TEST CONDITIONS Tamb (°C) UNIT OTHER VCCA/B(V) −40 to +85 MIN. TYP.(1) MAX. VIH HIGH-level input voltage 3 V port 2.7 to 3.6 2.0 − − V 5 V port 4.5 to 5.5 2.0 − − VIL LOW-level input voltage 3 V port 2.7 to 3.6 − − 0.8 V 5 V port 4.5 to 5.5 − − 0.8 VOH HIGH-level output voltage (3 V port) VI = VIH or VIL; IO = −12 mA 2.7 VCC − 0.5 − − V VI = VIH or VIL; IO = −100 µA 3.0 VCC − 0.2 VCC − VI = VIH or VIL; IO = −24 mA 3.0 VCC − 1.0 − − HIGH-level output voltage (5 V port) VI = VIH or VIL; IO = −12 mA 4.5 VCC − 0.5 − − V VI = VIH or VIL; IO = −100 µA 4.5 VCC − 0.2 VCC − VI = VIH or VIL; IO = −24 mA 4.5 VCC − 0.8 − − VOL LOW-level output voltage (3 V port) VI = VIH or VIL; IO = 12 mA 2.7 − − 0.40 V VI = VIH or VIL; IO = 100 µA 3.0 − − 0.20 VI = VIH or VIL; IO = 24 mA 3.0 − − 0.55 LOW-level output voltage (5 V port) VI = VIH or VIL; IO = 12 mA 4.5 − − 0.40 V VI = VIH or VIL; IO = 100 µA 4.5 − − 0.20 VI = VIH or VIL; IO = 24 mA 4.5 − − 0.55 II input leakage current VI = 5.5 V or GND; note 2 3.6 − ±0.1 ±5 µA IIHZ/IILZ input current for common I/O pins (3 V port) VI = VCC or GND 3.6 − 0.1 ±15 µA input current for common I/O pins (5 V port) VI = VCC or GND 5.5 − 0.1 ±15 µA IOZ 3-state output OFF-state current (3 V port) VI = VIH or VIL; VO = VCC or GND 3.6 − 0.1 ±5 µA 3-state output OFF-state current (5 V port) VI = VIH or VIL; VO = VCC or GND 5.5 − 0.1 ±5 µA ICC quiescent supply current (3 V port) VI = VCC or GND; IO = 0 3.6 − 0.1 10 µA quiescent supply current (5 V port) VI = VCC or GND; IO = 0 5.5 − 0.1 10 µA ∆ICC additional quiescent supply current per control pin (3 V port) VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 − 5 500 µA additional quiescent supply current per control pin (5 V port) VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − 5 500 µA 1999 Jun 15 7 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; Tamb = −40 to 85 °C. Notes 1. Typical values are measured at VCCA = 5.0 V and VCCB = 3.3 V and Tamb = 25 °C. 2. Typical values are measured at VCCA = 5.0 V and Tamb = 25 °C. SYMBOL PARAMETER WAVEFORMS LIMITS UNIT VCCA = 5 V ± 0.5 V VCCB = 3.3 V ± 0.3 V VCCB = 2.7 V MIN. TYP.(1) MAX. MIN. TYP.(2) MAX. tPHL/tPLH propagation delay An to Bn see Figs 4 and 7 1.5 4.0 6.5 1.5 4.5 7.0 ns propagation delay Bn to An see Figs 4 and 7 1.5 4.0 6.5 1.5 4.5 7.0 ns tPZH/tPZL 3-state output enable time OE to An see Figs 6 and 7 1.5 6.2 10 1.5 7.0 11.0 ns 3-state output enable time OE to Bn see Figs 6 and 7 1.5 5.0 8.1 1.5 5.7 8.7 ns tPHZ/tPLZ 3-state output disable time OE to An see Figs 6 and 7 1.5 5.3 7.5 1.5 5.7 8.0 ns 3-state output disable time OE to Bn see Figs 6 and 7 1.5 5.8 7.8 1.5 6.2 8.5 ns AC WAVEFORMS Fig.4 The input (An, Bn) to output (Bn, An) propagation delays. handbook, halfpage MNA366 An, Bn INPUT Bn, An OUTPUT tPHL tPLH GND VI VM VM VOH VOL VM = 1.5 V at 2.7 V ≤ VCCB ≤ 3.6 V; VM = 0.5VCCA at VCCA ≥ 4.5 V; VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Supply operation area. handbook, halfpage 1.5 2.7 5.7 Complies with TTL levels 3.9 0.9 MNA454 3.92.1 4.5 5.13.3 1.5 2.1 2.7 3.3 3.6 1.2 1.8 2.4 3.0 VCCA (V) VCCB (V) VCCA ≥ VCCB Full operation 1999 Jun 15 8 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A Fig.6 The 3-state enable and disable times. handbook, full pagewidth MNA367 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled OUTPUT LOW-to-OFF OFF-to-LOW OUTPUT HIGH-to-OFF OFF-to-HIGH OE INPUT VI VOL VOH VCC VM GND GND tPZL tPZH VM VM VM = 1.5 V at 2.7 V ≤ VCCB ≤ 3.6 V; VM = 0.5VCCA at VCCA ≥ 4.5 V; VX = VOL + 0.3 V at VCCB ≤ 3.6 V; VX = VOL + 0.1 (VCCA − VOL) at VCCA ≥ 4.5 V VY = VOH − 0.3 V at VCCB ≤ 3.6 V; VY = VOH − 0.1 (VOH − GND) at VCCA ≥ 4.5 V; VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 Load circuitry for switching times. Definitions for test circuit: RL = Load resistor; see chapter “AC characteristics”. CL = Load capacitance including jig and probe capacitance (see chapter “AC characteristics”). RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator. TEST S1 tPLH/tPHL open tPLZ/tPZL 2 × VCC tPHZ/tPZH GND VCC VI for A and B port <2.7 V VCC for B port 2.7 to 3.6 V 2.7 V for A port 4.5 to 5.5 V 3.0 V handbook, full pagewidth open GND 50 pF 2 × VCC VCC VI VO MNA368 D.U.T. CLRT RL 500 Ω RL 500 Ω PULSE GENERATOR S1 1999 Jun 15 9 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A PACKAGE OUTLINES UNIT Amax. A1 A2 A3 bp c D (1) E (1) (1)e HE L Lp Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 2.65 0.300.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 SOT137-1 X 12 24 w M θ A A1 A2 bp D HE Lp Q detail X E Z c L v M A 13 (A )3 A y 0.25 075E05 MS-013AD pin 1 index 0.10 0.0120.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.0550.4190.394 0.043 0.039 0.035 0.0160.01 0.25 0.01 0.0040.0430.0160.01 e 1 0 5 10 mm scale SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 95-01-24 97-05-22 1999 Jun 15 10 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A UNIT A1 A2 A3 bp c D(1) E(1) (1)e HE L Lp Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.210.05 1.80 1.65 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 0.8 0.4 8 0 o o0.13 0.10.2 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 SOT340-1 MO-150AG 93-09-0895-02-04 X w M θ A A1 A2 bp D HE Lp Q detail X E Z e c L v M A (A )3 A 1 12 24 13 0.25 y pin 1 index 0 2.5 5 mm scale SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 A max. 2.0 1999 Jun 15 11 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A UNIT A1 A2 A3 bp c D(1) E(2) (1)e HE L Lp Q Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.150.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o0.13 0.10.21.0 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT355-1 MO-153AD 93-06-1695-02-04 0.25 0.50.2 w M bp Z e 1 12 24 13 pin 1 index θ AA1 A2 Lp Q detail X L (A )3 HE E c v M A X AD y 0 2.5 5 mm scale TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 A max. 1.10 1999 Jun 15 12 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Jun 15 13 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A Suitability of surface mount IC packages for wave and reflow soldering methods Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PACKAGE SOLDERING METHOD WAVE REFLOW(1) BGA, SQFP not suitable suitable HLQFP, HSQFP, HSOP, SMS not suitable(2) suitable PLCC(3), SO, SOJ suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 1999 Jun 15 14 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A NOTES 1999 Jun 15 15 Philips Semiconductors Product specification Octal dual supply translating transceiver; 3-state 74LVC4245A NOTES © Philips Electronics N.V. SCA All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be a