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电流控制DC-DC设计指南 748 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 3, MAY 2004 A Design Method for Paralleling Current Mode Controlled DC–DC Converters Peng Li, Member, IEEE and Brad Lehman, Member, IEEE Abstract—This paper proposes a new current sharing method. It ...

电流控制DC-DC设计指南
748 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 3, MAY 2004 A Design Method for Paralleling Current Mode Controlled DC–DC Converters Peng Li, Member, IEEE and Brad Lehman, Member, IEEE Abstract—This paper proposes a new current sharing method. It is based on current mode controlled dc–dc converters and achieves the current sharing by forcing all inner current loops to have the same current reference. Meanwhile, this method decouples con- trol loops from the voltage regulation and current-sharing regula- tion instead of adding control loops as in traditional master–slave methods. Therefore, the large signal performance is good while its stability is guaranteed. Further, unlike multi-module methods, the modularity of single dc–dc converter is retained. Design rules and small signal analysis are presented. The advantages of the proposed method are verified by experimental results. Index Terms—Current-sharing regulation, current mode con- trolled (CMC), dc–dc converter, master–slave method. I. INTRODUCTION PARALLEL power systems have seen widespread applica-tions due to their benefits in redundancy, thermal man- agement, efficiency and modularity. Typically, parallel power systems are designed so that the stresses among the paralleled dc–dc converters are balanced. This is commonly achieved by current-sharing control. Among the many proposed schemes [1]–[8], the master-slave method is widely utilized [3]–[8] because of its good voltage regulation, modularity and simplicity. In this approach, the par- alleled converters share information on output current through a current sharing bus; one converter is chosen as the master converter to ensure the voltage regulation, and others, the slave converters, try to keep their output currents to be the same as the master’s by regulating their voltage reference through (ad- ditional) current-sharing control loops. Because of the added current-sharing control loops, the par- allel system with master-slave method becomes a multi-input, multi-output system. Therefore, the design and analysis requires sophistication [9], [10]. As a result, in system design, the band- width of the current-sharing control loop is kept much lower than that of the voltage control loop of the converter in order to guarantee the stability of the parallel system [5], [9], [11], [12]. However, this design rule results in a slow dynamic performance of the current sharing, and ongoing research is attempting to ad- dress these problems [13], [14]. Manuscript received March 31, 2003; revised November 21, 2003. This paper was presented in part at the APEC’03 Conference, Miami Beach, FL, 2003. Recommended by Associate Editor D. Maksimovic. P. Li is with Performance Motion Devices, Inc., Lincoln, MA 01773 USA (e-mail: pli@ece.neu.edu). B. Lehman is with the Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA. Digital Object Identifier 10.1109/TPEL.2004.826497 On the other hand, it is widely known that the current source behavior of the inner current loops of current mode controlled (CMC) dc–dc converters can be used to obtain current sharing [15], [16]. For example, when multiple dc–dc converters are par- alleled, all inner current loops can be forced to share one voltage loop [17]–[19]. Ongoing research focuses on improving robust- ness by adding third common output filter [18] or by introducing an additional control loop [20], [21]. However, these approaches have the disadvantage of losing the modularity of the dc–dc con- verters. Alternatively, [6] uses the source/sink capacity imbal- ance of UC3843 to force all converters to share the same inner current reference. However, the UC3843’s on the slaves are sat- urated, and therefore, so are their voltage control loops. This paper recognizes both the benefits and limitations of master-slave methods and the methods using the inherent current source properties of CMC converters. We propose a new master-slave current sharing design using the inner current source of CMC converters. It includes two parts: loop design and saturation prevention. In the loop design procedure, all inner current references are sent to a current sharing bus, and one reference is chosen as the master. Then all inner current loops take the master value as their reference to achieve current sharing by modifying the sensed current signal. Therefore, only the voltage control loop of the master is active in voltage regulation while those in the slaves are decoupled from the system. However, those voltage control loops in the slaves will saturate because of different references, and this implies performance degradation when the master fails. Therefore, the second part of the method is saturation prevention: to make those voltage loops have the same inner current reference as the master. Hence, the voltage loops of slaves actively act as backups for the master voltage loop. Specifically, the current sharing approach in this paper has the following features. 1) The proposed method is a master-slave method, and the current sharing bus is a minimum-master bus. 2) The proposed method uses the inner current loop of the CMC converter to achieve current sharing. Therefore, the current sharing response speed is fast and of the order of the speed of the inner current loop of an individual converter. 3) The proposed method achieves current sharing by modi- fying the sensed current signal. Thus, no additional cur- rent sensing circuit is needed. 4) The proposed method decouples the voltage control loops of slave converters from the parallel system. This makes 0885-8993/04$20.00 © 2004 IEEE LI AND LEHMAN: PARALLELING CURRENT MODE CONTROLLED DC–DC CONVERTERS 749 Fig. 1. Simplified schematic of proposed current sharing method. the stability analysis of the entire paralleled system sim- ilar to the stability analysis of an individual dc–dc con- verter. Therefore, the system design is simple. 5) Unlike traditional current sharing methods using inner current loops of CMC converters, modularity of each single converter is maintained and no controller in the converters is in saturation. 6) The proposed method is implemented by using off-the-shelf dc–dc converters with current mode PWM controllers, UC3843. 7) Because the proposed method does not need additional current sharing loops, the implementation is simple and saves cost and space. The implementation of the method is presented in Section II based on current mode PWM controller, UC3843. The operation of master and slave converter is shown in Section III. A small signal model and design rules are presented in Section IV. This method is implemented by using off-the-shelf dc–dc converters in Section V. Experimental results verify the proposed design. Conclusions are given in Section VI. Detailed small signal anal- ysis is given in Appendix. II. IMPLEMENTATION DESCRIPTION The implementation of the method is shown in Fig. 1. The dc–dc converter used is a peak current mode controlled converter with UC3843, and the amplifiers used are rail-to-rail single supply op amps. Specifically, each block has function as follows. DC–DC Converter: The solid box represents a peak current mode controlled dc–dc converter with input voltage, , and load. A buck converter is shown as the power train. Many dc–dc converters use synchronous rectification, and barrier diodes are commonly used for parallel design. As shown in Fig. 1, bar- rier diode is placed between the output and the load, and remote sense is used to compensate the voltage drop on the barrier diode and distribution lines. is the voltage trim resistor. Later it will be shown that only the trim resistor network and the outer voltage loop gain are needed for the system design while the other details such as the parameters of the power train and con- troller are not critical. There are different current sensing methods, and, for sim- plicity, it is assumed that the inductor current is sensed, and is the gain of the current sensing function. (Usually, it is the value of the current sensing resistor or the sample resistor at the output of the current transformer.) Originally, the output of is connected to and used as an input to UC3843, which is represented in a dashed box. is the inner current reference while the output of pin 1 of UC3843, , is proportional to with the bias of the voltage drop on the two diodes [22]. Therefore, in normal operation, the output of pin 1 can also be viewed as the current reference. Specifically (1) where is the forward voltage drop on the diode, and the number of 3 comes from voltage division and the relation be- tween and in Fig. 1. 750 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 3, MAY 2004 Fig. 2. Function of T . However, (1) is only true in normal operation because is limited to 1 V by the Zener diode paralleled with . Originally, the sensed current signal is . In the proposed method as shown in Fig. 1, the current sensing gain is modified to in order to maintain the current signal at , which will be shown later. Minimum-Master Bus: The minimum-master bus consists of Amp 1, the diode at its output, the current sharing bus and the current source. Therefore, the minimum voltage to Amp 1 will appear on the bus. In Fig. 1, the converter with the minimum current reference is the master. That is (2) where is the voltage of the current sharing bus and is of the master. Details of the min- imum-master bus can be found in [8], which also includes hot-swap circuits. The voltage signal of the current sharing bus is forwarded to the input of function block through a small voltage bias in Fig. 1. The small voltage bias, given as , is used to improve the noise immunity and to prevent bus competition. Therefore, there is (3) In following analysis, will be ignored if not specified. Function Block : In Fig. 1, if is larger than , func- tion block is simply a low-pass filter. However, all amplifiers in Fig. 1 are single supply op amps, and their lowest output voltage is zero. Therefore, is a nonlinear function, as shown in Fig. 2. The function in Fig. 2 is a piecewise-linear function (the nonlinear part of ) and can be represented as else. (4) where . and are the inputs to the positive input and the negative input of Amp 2, respectively. On the other hand, because in Fig. 1, have the same value and , the low-pass filter is the right block in Fig. 2 where and . Finally, the inputs to are the outputs of pin 1, , of UC3843’s, and (1) shows its relation with inner current refer- ence . Specifically, the positive input to Amp 2 is (5) where is the inner current reference of the converter. From (1) and (3), the negative input to Amp 2 is (6) where is the inner current reference of the master and is a small dc bias. Therefore, if and is ignored, at steady state (7) Here, is defined as the difference between of the con- verter and . Amp 3: Amp 3 with and is an addition function. With the values in Fig. 1, there is (8) where is the current signal in the original converter. Equa- tion (8) explains the reason the current sensing function is mod- ified to in the proposed method in Fig. 1. Function Block : Function Block is a proportional func- tion. With the value of resistors in Fig. 1, there is (9) where bias is for matching the steady state output voltage. Therefore, will adjust the output voltage of the converter by regulating trim pin based on the output of . It will prevent the voltage loops of the slaves from saturation, as will be ex- plained later. In real applications, is almost always needed for voltage limiting, due to the output range limit of the compo- nents, which will be shown in the implementation in Section V. III. OPERATION A. Operation of the Slave When current mode controlled dc–dc converters are paral- leled directly without current sharing regulation, the inner cur- rent loops will have different reference values due to the tol- erance on components and references. Suppose there are two same peak current mode controlled converters directly paral- leled. One converter has a higher inner current reference of , while another has a lower inner current reference of . Fig. 3(a) shows the current signal waveform, , of the converter with , which is fed to the pin 3 (CS) of UC3843 in Fig. 1. In addition, is the solid line and is the dashed line. The difference between the two references is , as in (7), and can be viewed as the reason for the current imbalance among the converters. That is (12) Current sharing can be obtained by equalizing the peak values of output currents in the application of peak current mode controlled converters. Therefore, the proposed method achieves current sharing by forcing the peak values of the current signal to be equal. Assume that and hold constant. Fig. 3(b) shows the current signal waveform of the converter with , which is the slave converter in the implementation of Fig. 1. Fig. 3(b) shows that the sensed current signal has a bias value . In fact, in Fig. 1, is the sum of the real current signal of the output inductor LI AND LEHMAN: PARALLELING CURRENT MODE CONTROLLED DC–DC CONVERTERS 751 Fig. 3. (a) Current signal in a paralleled converter without current sharing. (b) Current signal in the slave converter with proposed method (V current reference of the master;V : current reference of the slave). and , as shown in (8). Therefore, with (8) and (12), the peak value of the real current signal is (13) Equation (13) shows that the real output current of the slave has the same peak value as that of the master, and thus current sharing is achieved when the inductors and current sense gains are the same among the converters. Therefore, this method forces all inner loops to have the same output current peak value by modifying the sensed current signal. It can also be viewed as an indirect way to set the inner current references to the value of the master converter’s. As a result, only the voltage control loop of the master converter is working effectively. The above analysis assumes that all inner current references hold constant. However, in real applications, the voltage com- pensators of the slaves will try to regulate their own output to force the true output currents to meet their own inner references. So the current references of slaves, which are the output of the voltage compensators, tend to go into saturation. The function block is used to prevent this from occurring. The output of , which is connected to the trim pin of the converter, regulates the voltage reference of the converter to re- duce . is a constant voltage to match the dc point of the output. Therefore, prevents the voltage control loops of the slave converters from saturating. We call this control loop the minor loop. Obviously, the minor loop does not participate in current-sharing control directly in normal operation. Mean- while, it will be shown later that, if the bandwidth of the minor loop is sufficiently lower than that of the voltage control loop of the converter, the reference regulation is decoupled from the voltage regulation. That is, voltage loop bandwidth/ regulation is unaffected if is properly selected. Therefore, this method “removes” the voltage loops of slaves to achieve current sharing instead of adding another current- sharing loop. As a result, there is no tradeoff between the sta- bility and bandwidth of current sharing loop design, and the par- allel system will have good large signal performance. On the other hand, because the design for saturation preven- tion is not directly related to the current sharing, the proposed method divides the parallel design procedure into two indepen- dent and easier solved problems. The first is to maintain current sharing. The second, independent problem is to keep all control loops in the system working normally. As a result, system de- sign becomes simple. Meanwhile, the inner current sources have higher crossover frequencies than that of the voltage loops, and it implies that the parallel system will have fast voltage and cur- rent sharing dynamic response. IV. ANALYSIS AND DESIGN Although the proposed method is a master-slave method, the known analysis method in [3]–[5], [9], [10] cannot be used be- cause there is no additional current sharing control loop in the implementation, as shown in Fig. 1. Therefore, this section first presents a small signal model of the proposed method based on a macro model of CMC converters. Then design rules are pro- posed based on this model. It shows that the stability analysis of the proposed method is straightforward and justifies that the proposed method has fast current sharing response speed. System Model: A dc–dc converter can be modeled as a con- trolled voltage source with output impedance [10]. Further, the inner loop of the CMC converter can be modeled as a current source. This leads to a small signal model of a CMC converter as shown in Fig. 4(a). Using the notation of [10], is the transfer function from the voltage sense point to the comparison point with ref. In the simplest case, is a scaling factor from a re- sistor network. is the transfer function of the voltage con- troller in the converter. The block 1/3 is the proportion between and in Fig. 1. Referring to Fig. 4(a), the output of transfer function , given as , is the inner current reference, which corresponds to pin 1 of UC3843. The dashed box represents the inner cur- rent loop and it is a voltage controlled current source. is the transfer function from small signal inner current reference to small signal inductor current when the current loop is closed. (For peak current mode control, the inner current refer- ence in Fig. 1 is the peak value of the output current, so is . Therefore, although they correspond to and , respec- tively, there is a difference between the variables.) is the output impedance of the inner current loop and is sometimes approximated as the impedance of the output capac- itor bank. Therefore, for a single module, the outer voltage loop, , is (14) where . In most cases, the impedance of the load can be ignored compared with that of . That is (15) Based on the current source model, the model of the proposed method is shown in Fig. 4(b). For simplicity, only two converters are shown, and the effects of the barrier diode and impedance of the distributed lines are ignored. Because the proposed method modifies the current signal at the comparison point with the (peak) inner current reference , from the point of view of 752 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 3, MAY 2004 Fig. 4. Model of (a) a current mode controlled converter and (b) proposed method. small signal, it can also be viewed as modifying . Mean- while, this method is a master-slave method, and any converter can obtain the current sharing bus and be the master. However, when the master position is established and the system is in steady state, from the point of view of small signal, the system is the same as the dedicated master-slave system. Therefore, dedicated master-slave structure is used in system modeling. In Fig. 4(b), the upper converter is the master module, and the lower is the slave module. Design Considerations: From the schematic, the minor loop in the proposed method is similar as the current sharing control loop in traditional master-slave methods: Both methods have control loops to regulate the trim pin [5], [9], [12]. However, the control goal in the proposed method is different. In the tra- ditional master-slave methods, the current sharing control loop regulates the trim pin in order to change the converter’s output voltage and then to achieve current sharing. On the other hand, as shown before, the minor loop in the proposed method is used to prevent loop saturation, and it does not directly participate in current sharing. Therefore, the issue on slow current respo
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