US20210375866A1(19)UnitedStates(12)PatentApplicationPublication(lo)Pub.No.:US2021/0375866AlLiaw(43)Pub.Date:Dec.2,2021(54)INTEGRATEDCIRCUITDEVICEAND(52)U.S.Cl.METHODOEEORMINGTHESAMECPC.....HOIL27/0924(2013.01);HOIL27/0207(2013.01);HOIL21/823821(2013.01);HOIL(71)Applicant:TaiwanSemiconductor2027/11887(2013.01);HOIL27/0886ManufacturingCo.,Ltd.,Hsinchu(2013.01);HOIL29/41791(2013.01);HOIL(TW)21/823431(2013.01)(72)Inventor:JhonJhyLiaw,HsinchuCounty(TW)(57)ABSTRACT(21)Appl.No.:17/400,965(22)Filed:Aug.12,2021Anintegratedcircuitdeviceincludesafirstdeviceandaseconddevice.ThefirstdeviceisdisposedwithinafirstRelatedU.S.ApplicationDatacircuitregion,thefirstdeviceincludingapluralityoffirstsemiconductorstripsextendinglongitudinallyinafirst(62)DivisionofapplicationNo.16/415,320,filedonMaydirection.Adjacentonesofthepluralityoffirstsemicon17,2019,nowPat.No.11,094,695.ductorstripsarespacedapartfromeachotherinaseconddirection,whichisgenerallyperpendiculartothefirstdirecPublicationClassificationtion.Theseconddeviceisdisposedwithinasecondcircuit(51)Int.Cl.region,thesecondcircuitregionbeingadjacenttothefirstHOIL27/092(2006.01)circuitregioninthefirstdirection.TheseconddeviceHOIL27/02(2006.01)includesasecondsemiconductorstripextendinglongitudiHOIL21/8238(2006.01)nallyinthefirstdirection.AprojectionofalongitudinalaxisHOIL21/8234(2006.01)ofthesecondsemiconductorstripalongthefirstdirectionHOIL27/088(2006.01)liesinaspaceseparatingtheadjacentonesofthepluralityHOIL29/417(2006.01)offirstsemiconductorstrips.CellboundaryofSCIAbuttingcellboundariesCellboundaryofSC2[........w•U-i(>2C/5on1.......o1;104ACZl£n5c........\AW2SourceDrainContactContacthd&s100reST3>Cellboundary"S-Cellboundary/&sfWellboundariesAbuttingcellboundaries\S'P-types/StandardCellhdFillerStandardCellwellregion=Row1'"Ceff"Muitiple-FinFinFETsSingle-FinFinFETsS"N-type&swellregionS'_____StmidardCell_____........._Standard_Cell..........sRow2Single-FinFinFETsSingle-FinFinFETsP-typewellregionO«b*ls>104BOSCIAbuttingcellboundariesSC2ls>P-type.104A____.Standard_Cell_______StiuidardCell...........wellregion'CZ5Rowi>Hi—)Single-FinFinFETsCTMultiple-FinFinFETsN-typewellregionRowi+1>FillerStandardCellStandardCelloSingle-FinFinFETsSingle-FinFinFETsP-typewellregionSC3SC4dWellboundariesvyls>O<1U100FIGURE1>CellboundaryofSC1AbuttingcellboundariesCellboundaryofSC2116306BU4A314AFIGURE2ACellboundaryofSCIAbuttingcellboundariesCellboundaryofSC2LongitudinalaxesofProjectionofCL2infinstructures106Bx-directionintoSCIJ----------II{IIWI{IiwIII{IRowi-j™-JJISDiJ1JIIIfJI4JE3lJJIIJLLongitudinalaxesoffinstructures106AProjectionofCL1inx-directionintoSCIFIGURE2BPatentApplicationPnblicationSheet4of26US2021/0375866AlPatentApplicationPnblicationSheet5of26US2021/0375866AlPatentApplicationPnblicationDec.2,2021Sheet6of26US2021/0375866AlPatentApplicationPnblicationDec.2,2021Sheet7of26US2021/0375866Al1pa&0PatentApplicationPnblicationDec.2,2021Sheet8of26US2021/0375866Al0I—*PatentApplicationPnblicationDec.2,2021Sheet9of26US2021/0375866AlK5sopo•—MOB"S-MOBMOB340BS'shd■=S"■&s1S's11O«1Hi1sb*K»ls>i1CZ5JCTre■ret▼oI103-2o116340A340Advyls><100SourceDrainFIGURE7ContactContactPatentApplicationPnblicationDec.2,2021Sheet11of26US2021/0375866AlCellboundaryofSCIAbuttingcellboundariesCelIboundaryofSC2■■11111i1J■tSourceDrainFIGURE9ContactContactCellboundaryofSCIAbuttingcellboundariescellboundaryofSC2re100ST3>"S-&sMl’(Vss)S'J—sIhdI=JIIMlS"I&s1Mlu.J(ZJd*',S'IsJS:MlJJMlJJMlORowi-0«JHiJMlIsb*Ils>I\!MloJU-ils>IMlccIoIIMlIIMls-JreJreI1▼oMl’(Vdd)dvyls>oW4O<100DrainFIGURE10ContactContactCellboundary^ofSCICellboundaryofSC2Abuttingcellboundaries340B"»»II.....4:iII11s\/IcziI(AJJ/\»/’JIMlRowi-fMl—VG—a—"VGcZo-SkSourceDrainFIGURE11ContactContacthd&sreST3>"S-’&s«S'shdc2S"&sS'sO«ffils>Ols>STrereU1oo\dvyls>ols>o<1U100PatentApplicationPnblicationDec.2,2021Sheet16of26US2021/0375866Alhd&sreS>T3&sS'shd=S"&sS'sO«ffiu*ls>oFIGURE13BK»s-ffi<1odvyls>oK»o<1U100hd&sreST3>"S-’&s«S'shdc2S"&sS'sO«ffils>Ols>STrere00oo\dvyls>ols>o<1U100PatentApplicationPnblicationSheet19of26US2021/0375866AlPatentApplicationPnblicationSheet20of26US2021/0375866AlPatentApplicationPnblicationSheet21of26US2021/0375866AlPatentApplicationPnblicationSheet22of26US2021/0375866Alhd&sreST3>"S-&sS'shdc2S"&sS'so«K>ls>ols>CZ5CTffiffils>OK»O\dCZ5ls>O<1U100FIGURE1411O\>PatentApplicationPnblicationSheet24of26US2021/0375866AlPatentApplicationPnblicationSheet25of26US2021/0375866Alhd&sreST3>"S-&sS'shd=S"&sS'sO«ffiK>ls>Ols>CZ5CTls>O\oK»O\dCZ5ls>Ols>o<1U100FIGURE15US2021/0375866AlDec.2,20211INTEGRATEDCIRCUITDEVICEAND[0012]FIGS.7and9to10showsimplifledtop-downMETHODOEFORMINGTHESAMEschematicviewsofinterconnectstructuresdisposedintheflrststandardcellandthesecondstandardcell,inaccordance[0001]ThisapplicationisaDivisionalofU.S.patentwithoneormoreembodiments;applicationSer.No.16/415,320,filedMay17,2019,which[0013]FIG.8illustratesametallizationlayer,inaccorisherebyincorporatedbyreferenceinitsentirety.dancewithanembodiment;BACKGROUND[0014]FIG.11showsasimplifledtop-downschematicviewoftheflrststandardcellandthesecondstandardcellof[0002]Thesemiconductorintegratedcircuit(IC)industrythearrayofstandardcellsofFIG.1,inaccordancewithhasexperiencedexponentialgrowth.Technologicalanotherembodiment;advancesinICmaterialsanddesignhaveproducedgenera[0015]FIG.12showsasimplifledtop-downschematictionsofICswhereeachgenerationhassmallerandmoreviewofathirdstandardcellandafourthstandardcellofthecomplexcircuitsthanthepreviousgeneration.InthecoursearrayofstandardcellsofFIG.1,inaccordancewithanofICevolution,functionaldensity(i.e.,thenumberofembodiment;interconnecteddevicesperchiparea)hasgenerally[0016]FIGS.13Ato13Jand14Ato14Jshowaprocessincreasedwhilegeometrysize(i.e.,thesmallestcomponent,flowillustratingamethodforformingflnstructuresintheorline,thatcanbecreatedusingafabricationprocess)hasflrststandardcellandthesecondstandardcellofthearraydecreased.ofstandardcellsofFIG.1,inaccordancewithanembodi[0003]Despiteadvancesinmaterialsandfabricationtechment;andniques,scalingofplanardevices,suchasthemetal-oxide-[0017]FIG.15showsaflowchartdescribingamethodforsemiconductorfieldeffecttransistor(MOSFET)device,hasformingflnstructuresintheflrststandardcellandthesecondprovenchallenging.Toovercomethesechallenges,non-standardcellofthearrayofstandardcellsofFIG.1,inplanartransistorshavebeendeveloped,examplesbeingaccordancewithanembodiment.gate-all-around(GAA)transistorsandfin-likefieldeffecttransistors(FinFETs).Advantagesofnon-planartransistorsDETAILEDDESCRIPTIONincludeareductionoftheshortchanneleffect,reducedleakage,andhighercurrentflow.Notwithstandingthese[0018]Thefollowingdisclosureprovidesmanydifferentadvantages,non-planartransistorscanexhibitincreasedembodiments,orexamples,forimplementingdifferentfeacontactresistanceandcapacitanceasfeaturesizeisreducedturesoftheprovidedsubjectmatter.Speciflcexamplesofastechnologyprogressestowardssmallertechnologynodes.componentsandarrangementsaredescribedbelowtosimImprovementsinintegratedcircuitsincludingnon-planarplifythepresentdisclosure.Theseare,ofcourse,merelytransistorsmaybeneeded.examplesandarenotintendedtobelimiting.Forexample,theformationofaflrstfeatureoveroronasecondfeatureBRIEFDESCRIPTIONOFTHEDRAWINGSinthedescriptionthatfollowsmayincludeembodimentsinwhichtheflrstandsecondfeaturesareformedindirect[0004]Thepresentdisclosureisbestunderstoodfromthecontactandmayalsoincludeembodimentsinwhichaddifollowingdetaileddescriptionwhenreadwiththeaccomtionalfeaturesmaybeformedbetweentheflrstandsecondpanyingflgures.Itisemphasizedthat,inaccordancewithfeatures,suchthattheflrstandsecondfeaturesmaynotbethestandardpracticeintheindustry,variousfeaturesarenotindirectcontact.Inaddition,thepresentdisclosuremaydrawntoscaleandareusedforillustrationpurposesonly.Inrepeatreferencenumeralsand/orlettersinthevariousfact,thedimensionsofthevariousfeaturesmaybearbiexamples.Thisrepetitionisforthepurposeofsimplicityandtrarilyincreasedorreducedforclarityofdiscussion.clarityanddoesnotinitselfdictatearelationshipbetween[0005]FIG.1showsasimplifledlayoutofanintegratedthevariousembodimentsand/orconflgurationsdiscussed.circuitthatincludesanarrayofstandardcells,inaccordance[0019]Further,spatiallyrelativeterms,suchas“beneath,”withanembodiment;“below,”“lower,”“above,”“upper”andthelike,maybe[0006]FIG.2Ashowsasimplifledtop-downschematicusedhereinforeaseofdescriptiontodescribeoneelementviewofaflrststandardcellandasecondstandardcelloftheorfeature’srelationshiptoanotherelement(s)orfeature(s)arrayofstandardcellsofFIG.1,inaccordancewithanasillustratedintheflgures.Thespatiallyrelativetermsareembodiment;intendedtoencompassdifferentorientationsofthedevicein[0007]FIG.2Bshowsasimplifledtop-downschematicuseoroperationinadditiontotheorientationdepictedintheviewofflnstructureslocatedwithinboundariesoftheflrstflgures.Theapparatusmaybeotherwiseoriented(rotated90standardcellandthesecondstandardcellofFIG.2A,indegreesoratotherorientations)andthespatiallyrelativeaccordancewithanembodiment;descriptorsusedhereinmaylikewisebeinterpretedaccord[0008]FIG.3showsasimplifledperspectiveviewofaingly.Stillfurther,whenanumberorarangeofnumbersisportionoftheflrststandardcellshowninFIG.2A,indescribedwith“about,”“approximate,”andthelike,theaccordancewithanembodiment;termisintendedtoencompassnumbersthatarewithin[0009]FIG.4showsasimplifledperspectiveviewofa+/-10%ofthenumberdescribed,unlessotherwisespecifled.portionofthesecondstandardcellshowninFIG.2A,inForexample,theterm“about5nm”encompassestheaccordancewithanembodiment;dimensionrangefrom4.5nmto5.5nm.[0010]FIGS.5Aand5Bshowcross-sectionalviewsoffln[0020]Foradvancedintegratedcircuit(IC)technologystructuresoftheflrststandardcellshowninFIG.3,innodes,non-planartransistordeviceshavebecomeapopularaccordancewithanembodiment;andpromisingcandidateforhighperformanceandlow[0011]FIGS.6Aand6Bshowcross-sectionalviewsofflnleakageapplications,particularlyforsystem-on-chip(SoC)structuresofthesecondstandardcellshowninFIG.4,inproducts.Oneexampleofanon-planartransistordeviceisaccordancewithanembodiment;aflnfleld-effecttransistor(FinFET)device.TheFinFETUS2021/0375866AlDec.2,20212devicehasanelevatedchannelwrappedbyagatestructuremethodology—thegeneralclasstowhichstandardcellsonmorethanoneside.Forexample,thegatestructurewrapsbelong—makesitpossibleforonedesignertofocusontheatopsurfaceandsidewallsofastripofsemiconductorhigh-level(logicalfunction)aspectofdigitaldesign,whilematerial(referredtoasa“fin”)extendingoutofasubstrateanotherdesignerfocusesontheimplementation(physical)fromamajorsurfacethereof.Comparedtoplanartransisaspect.Alongwithsemiconductormanufacturingadvances,tors,theFinFETdeviceprovidesbettercontrolofthestandardcellmethodologyhashelpeddesignersscaleASICschannelandreducesshortchanneleffects,inparticular,byfromcomparativelysimplesingle-functionICs(ofseveralreducingsub-thresholdleakage(whichmayrefertocouthousandgates),tocomplexmulti-milliongatesystem-on-plingbetweenasourceandadrainoftheFinFETdeviceina-chip(SoC)devices.Invariousexamples,astandardcellthe“off’state).However,astechnologyprogressestowards(e.g.whichmaybereferredtoasafunctionalcell,asmallertechnologynodes(e.g.32nm,28nm,20nm,andfunctionallogiccell,and/oracircuitregion)mayincludeasmaller),thereisacorrespondingdecreaseinawidthofafingroupoftransistorsandinterconnectstructuresthatmayoftheFinFETdevice(whichmaybeneededforshortimplementacircuit,forexample,acircuitprovidingachannelcontrol,forexample).Insomecases,thewidthofBooleanlogicfunction(e.g.AND,OR,XOR,XNOR,thefinmaybedecreasedtobeintherangeofabout5NAND,NOR,inverters,etc.)orastoragefunction(e.g.nanometerstoabout20nanometers.Suchnarrowfinwidthsflip-floporlatch).Thesimpleststandardcellsaredirectplacesignificantconstraintsonmulti-layerinterconnectfearepresentationsoftheelementalNAND,NOR,andXORturesthatareneededtofacilitateoperationoftheFinFETBooleanfunction,althoughcellsofmuchgreatercomplexitydevice.Forexample,multi-layerinterconnectfeaturesmayarecommonlyused(e.g.suchasa2-bitfull-adder,ormuxedincludeacontact(e.g.aslotcontact)thatlandsonaD-inputflip-flop).source/drainregionofthenarrowfin(e.g.tophysically[0023]Thearrayofstandardcellsmaybearrangedincontactthesource/drainregion).However,duetotherows,witheachrowincludingapluralityofstandardcells.reducedwidthofthefin,thecontact-to-source/drainlandingEachstandardcellisdemarcatedordelineatedbyacellmarginisdegraded.Additionally,asmallercontactareaisboundary,asillustratedinFIG.1,andadjacentstandardcellsmadebetweenthecontactandthesource/drainregionoftheinagivenrowmayhavecellboundariesthatabuteachother.narrowfin(e.g.comparedtoaplanartransistororanotherAdditionally,asillustratedinFIG.1,standardcellsinFinFETdevicewithafinhavingawidthgreaterthantheadjacentrowsmayhavecellboundariesthatabuteachother.aforementionedrange).ThesmallercontactarearesultsinAsdiscussedabove,eachstandardcellmayincludeagroupincreasedcontactresistanceandincreasedcontactcapacioftransistorsandinterconnectstructuresthatmayimpletance.mentacircuit(e.g.providingaBooleanlogicfunctionora[0021]Thepresentdisclosureaimstocircumventthestoragefunction).Toimplementsuchfunctionality,theabove-describeddrawbacksthataccompanythedecreaseinstandardcellsmayeachincludecomplementarymetal-featuresize.Forexample,thepresentdisclosureproposesaoxide-semiconductorfleld-elfecttransistors(CMOSFETs)layoutforafirststandardcell(havingoneormoremultiple-havingoneormoreP-typeMOSIT'Ts(PMOSFETs)formedfinFinFETdevice)andasecondstandardcell(havingoneinanN-typewellregionaswellasoneormoreN-typeormoresingle-finFinFETdevice)thatarelocatedadjacentMOSFETs(NMOSFETs)formedinaP-typewellregion.toeachotheralongarowofanarrayofstandardcells.IntheTheN-typewellregions,theP-typewellregions,andtheproposedlayout,asingle-finstructureofthesecondstandardboundariestherebetweenareshowninFIG.1.Inanembodicellispositionedsuchthatthelongitudinalaxisofthement,eachoftheoneormorePMOSFETsandtheoneorsingle-finstructure,whenprojectedfromthesecondstanmoreNMOSFETsofastandardcellmaybeimplementeddardcelltothefirststandardcell,liesinaspacethatusingaFinFETdevice.separatesadjacentfinstructuresofamultiple-finFinFET[0024]AsshowninFIG.1,arowofthearrayofstandarddeviceofthefirststandardcell.Theproposedlayoutallecells(e.g.RowiofFIG.1)includesafirststandardcellSCIviatesconstraintsonthesource/drainlandingmarginfortheandasecondstandardcellSC2,whichareadjacentto(e.g.single-finFinFETdevicesofthesecondstandardcellandimmediatelyadjacentto)eachotherinafirstdirection(e.g.alignsthesingle-finstructuresofthesecondstandardcelltoanx-direction).ThefirststandardcellSCIdiffersfromtheacenterregionofcontacts(e.g.slotcontacts)thatlandonsecondstandardcellSC2inthatthefirststandardcellSCIandcontactthedrainfeaturesofthesingle-finFinFETincludesoneormoremultiple-finFinFETdevices,whilethedevicesofthesecondstandardcell,which,inturn,decreasessecondstandardcellSC2includesoneormoresingle-fincontactresistanceandcontactcapacitance.WhilethepresFinFETdevices.Amultiple-finFinFETdevicemaybeaentdisclosurespatialandpositionalfeaturesoffinstructuresFinFETdevicethatincludestwoormoresemiconductorofFinFETdevices,itisnotedthatthespatialandpositionalfins,whereagatestructure(thatiscommontothetwoorfeaturesdescribedhereinarealsoapplicabletoothernon-moresemiconductorfins)controlscurrentflowinchannelplanartransistordevices(e.g.gate-all-aroundtransistorregionsdisposedinthetwoormoresemiconductorfins.Ondevices).theotherhand,asingle-finFinFETdevicemaybeaFinFET[0022]FIG.1showsasimplifiedlayoutofanintegrateddevicethatincludesnomorethanonesemiconductorfin,circuitdevice100thatincludesanarrayofstandardcells,inwhereagatestructure(whichmaybedifferentfromthegateaccordancewithanembodiment.Insemiconductordesign,structureofthemultiple-finFinFETdevice)engagestheonestandardcellmethodologyisamethodofdesigningapplisemiconductorfinandcontrolscurrentflowinachannelcation-specificintegratedcircuits(ASICs)withmostlydigiregiondisposedintheonesemiconductorfin.Consequently,tal-logicfeatures.StandardcellmethodologyisanexampleRowiofFIG.1maybearowofthearraythatincludesaofdesignabstraction,wherebyalow-levelvery-large-scalestandardcellincludingoneormoremultiple-finFinFETintegration(VLSI)layoutisencapsulatedintoanabstractdevices(e.g.firststandardcellSCI)thatisadjacenttologicrepresentation(e.g.suchasaNANDgate).Cell-basedanotherstandardcellincludingoneormoresingle-finFin-US2021/0375866AlDec.2,20213FETdevices(e.g.secondstandardcellSC2).ThesefeaturesFinFETdevicelOlB.IntheexampleofFIG.3,eachoftheoffirstandsecondstandardcellsSCI,SC2areillustratedfirstandsecondFinFETdeviceslOlA,lOlBincludestwoandexplainedingreaterdetailinFIGS.2A,2B,3,4,5A,SB,fins;however,themultiple-finFinFETdevicesofthefirst6A,and6B.Inanembodiment,thefirststandardcellSCIstandardcellSCImayincludemorethantwofinsinothermaybeusedforhighspeedapplicationssinceitincludesembodiments.Furthermore,asillustratedinFIGS.2Aand3,FinFETdeviceshavingmultiple-fins.Thesecondstandardthefirstgatestructure103-1isorientedalongthesecondcellSC2,conversely,maybeusedforlowleakageandlowdirection(e.g.they-direction).Stateddifferently,alongitupower(e.g.lowactivepowerand/orlowstandbypower)dinalaxisofthefirstgatestructure103-1maybeorientedapplicationssinceitincludesFinFETdeviceshavingaalongtheseconddirection,whileatransverseaxisofthefirstsingle-fin.Consequently,theintegratedcircuitdevice100,gatestructure103-1maybeorientedalongthefirstdirechavingbothmultiple-finFinFETdevicesandsingle-fintion.ItisnotedthatthetransverseaxesofthefinstructuresFinFETdevices,maybeusedforbothhighperformanceand106A,306A,106B,306Bmaybeorientedalongthesecondlowleakageapplications,particularlyforSoCproducts.direction.[0025]FIG.2Ashowsasimplifiedtop-downschematic[0029]FIG.3alsoillustratesalineA-AandalineB-BviewofthefirststandardcellSCIandthesecondstandardalongwhichcross-sectionalviewsofthefirststandardcellcellSC2ofFIG.1,inaccordancewithanembodiment.FIG.SCIaretaken.Thecross-sectionalviewalongthelineA-A2AillustratesthecellboundariesofthefirstandsecondisillustratedinFIG.5A,andthecross-sectionalviewalongstandardcellsSCI,SC2.FIG.2AalsoillustratesisolationthelineB-BisillustratedinFIG.5B.Itisnotedthatthestructures303-1,303-2,303-3(e.g.implementedusingcross-sectionalviewalongthelineA-Aisalongthelongidielectricgates)thataredisposedontheboundariesofthetudinalaxisofafinstructure106AofthefirstFinFETdevicefirstandsecondstandardcellsSCI,SC2toisolatethefirstlOlA.Inlikemanner,thecross-sectionalviewalongthelineandsecondstandardcellsSCI,SC2fromeachotherandB-Bisalongthelongitudinalaxisofafinstructure106BoffromotherstandardcellsoftheRowi.Asanexample,thethesecondFinFETdevicelOlB.firstandsecondstandardcellsSCI,SC2areisolatedfrom[0030]FIG.4showsasimplifiedperspectiveviewofaeachotherbytheisolationstructure303-2.Theisolationportion204ofthesecondstandardcellSC2showninFIG.structures303-1,303-2,303-3mayincludeadielectric2A,inaccordancewithanembodiment.Asillustratedinmaterialsuchassiliconoxideorsiliconnitride,asexamples.FIG.4,thesecondstandardcellSC2includesathirdFinFET[0026]StandardcellsoftheRowimayhaveadimensiondevice301AandafourthFinFETdevice301B.ThethirdH,(e.g.acellheight),measuredinaseconddirection(e.g.andfourthFinFETdevices301A,301Bhaveoppositeay-direction)thatissubstantiallyperpendiculartothefirstconductivity-types.ThethirdFinFETdevice301Ahasthedirection.Thedimensionamaybeindicativeof(e.g.equalsameconductivity-typeasthefirstFinFETdevicelOlA,to)adistancebetweenopposingboundariesofthecellsofwhilethefourthFinFETdevice301BhasthesameconductheRowi.ThedimensionII,maybeinarangeofabout50tivity-typeasthesecondFinFETdevicelOlB.Incontrasttonanometersandabout400nanometers.thefirstandsecondFinFETdeviceslOlA,lOlBofthefirst[0027]Asdiscussedabove,thestandardcellsincludestandardcellSCI,eachofthethirdandfourthFinFETCMOSFETs,whichmaybeimplementedusingFinFETdevices301A,301Bisasingle-finFinFETdevice.Asandevices.Consequently,asseeninFIG.2A,thefirststandardexample,eachofthethirdandfourthFinFETdevices301A,cellSCIincludesfinstructures106A,106Bthatareoriented301Brespectivelyincludesonefin,andasecondgateorroutedalongthefirstdirection(e.g.thex-direction),whilestructure103-2engagestheonefinofeach
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