EDA常见实例源程序代码vhdl

EDA-常见实例源程序代码vhdl第4章用VHDL程序实现常用逻辑电路4.1组合逻辑电路 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 4.1.1基本逻辑门libraryieee;useiee.std_logic_1164.all;entityjbmisport(a,b:inbit;f1,f2,f3,f4,f5,f:outbit);endjbm;architectureaofjbmisbeginf1<=aandb;--构成与门f2<=aorb;--构成或门f<=nota;--构成非门f3<=anandb;--构成与非门f4<=anorb;--构成异或门f5<=not(axorb);--构成异或非门即同门end;4.1.2三态门libraryieee;useieee.std_logic_1164.all;entitytri_sisport(enable:instd_logic;datain:instd_logic_vector(7downto0);dataout:outstd_logic_vector(7downto0));endtri_s;architecturebhvoftri_sisbeginprocess(enable,datain)beginifenable='1'thendataout<=datain;elsedataout<="ZZZZZZZZ";endif;endprocess;endbhv;4.1.33-8译码器libraryieee;useieee.std_logic_1164.all;entitydecoder3_8isport(a,b,c,g1,g2a,g2b:instd_logic;y:outstd_logic_vector(7downto0));enddecoder3_8;architectureaofdecoder3_8issignaldz:std_logic_vector(2downto0);begindz<=c&b&a;process(dz,g1,g2a,g2b)beginif(g1='1'andg2a='0'andg2b='0')thencasedziswhen"000"=>y<="11111110";when"001"=>y<="11111101";when"010"=>y<="11111011";when"011"=>y<="11110111";when"100"=>y<="11101111";when"101"=>y<="11011111";when"110"=>y<="10111111";when"111"=>y<="01111111";whenothers=>y<="XXXXXXXX";endcase;elsey<="11111111";endif;endprocess;4.1.4优先编码器libraryieee;useieee.std_logic_1164.allentitycoderisport(din:instd_logic_vector(0to7);output:outstd_logic_vector(0to2));endcoder;architecturebehaveofcoderissignalsint:std_logic_vevtor(4downto0);beginprocess(din)beginif(din(7)='0')thenoutput<="000";elsif(din(6)='0')thenoutput<="100";elsif(din(5)='0')thenoutput<="010";elsif(din(4)='0')thenoutput<="110";elsif(din(3)='0')thenoutput<="001";elsif(din(2)='0')thenoutput<="101";elsif(din(1)='0')thenoutput<="011";elseoutput<="111";endif;endprocess;endbehav;4.1.57段码译码器libraryieee;useieee.std_logic_1164.allentitydecl7sisport(a:instd_logic_vector(3downto0);led7s:outstd_logic_vector(6downto0));enddecl7s;architecturebehaveofdecl7sisbeginprocess(a)begincaseaiswhen"0000"=>led7s<="0111111";when"0001"=>led7s<="0000110";when"0010"=>led7s<="1011011";when"0011"=>led7s<="1001111";when"0100"=>led7s<="1100110";when"0101"=>led7s<="1101101";when"0110"=>led7s<="1111101";when"0111"=>led7s<="0000111";when"1000"=>led7s<="1111111";when"1001"=>led7s<="1101111";when"1010"=>led7s<="1110111";when"1011"=>led7s<="1111100";when"1100"=>led7s<="0111001";when"1101"=>led7s<="1011110";when"1110"=>led7s<="1111001";when"1111"=>led7s<="1110001";whenothers=>null;endcase;endprocess;endbehave;4.1.6二-十进制BCD译码器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entitybcdymqisport(din:inintegerrange15downto0;a,b:outintegerrange9downto0);end;architecturefpq1ofbcdymqisbeginp1:process(din)beginifdin<10thena<=din;b<=0;elsea<=din-10;b<=1;endif;endprocessp1;end;4.1.7多位加（减）法器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entityjianfaqiisport(a,b:instd_logic_vector(0to3);c0:instd_logic;c1:outstd_logic;d:outstd_logic_vector(0to3));end;architectureaofjianfaqiisbeginprocessbeginifa>b+c0thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);endif;endprocess;end;4.2时序逻辑电路设计4.2.1触发器RS触发器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entityrsffisport(r,s,clk:instd_logic;q,qb:bufferstd_logic);endrsff;architecturersff_artofrsffissignalq_s,qb_s:std_logic;beginprocess(clk,r,s)beginif(clk'eventandclk='1')thenif(s='1'andr='0')thenq_s<='0';qb_s<='1';elsif(s='0'andr='1')thenq_s<='1';qb_s<='0';elsif(s='0'andr='0')thenq_s<=q_s;qb_s<=qb_s;endif;endif;q_s<=q_s;qb_s<=qb_s;endprocess;endrsff_art;同步复位D触发器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entitysyndffisport(d,clk,reset:instd_logic;q,qb:outstd_logic);endsyndff;architecturedff_artofsyndffisbeginprocess(clk)beginif(clk'eventandclk='1')thenif(reset='0')thenq<='0';qb<='1';elseq<=d;qb<=notq;endif;endif;endprocess;enddff_art;JK触发器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entityasynjkffisport(j,k,clk,set.reset:instd_logic;q,qb:outstd_logic);endasynjkff;architecturejkff_artofasynjkffissingalq_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif(set='0'andreset='1')thenq_s<='1';qb_s<='0';elsif(set='1'andreset='0')thenq_s<='0';qb_s<='1';elsif(clk'eventandclk='1')thenif(j='0'andk='1')thenq_s<='0';qb_s<='1';elsif(j='1'andk='0')thenq_s<='1';qb_s<='0';elsif(j='1'andk='1')thenq_s<=notq_s;qb_s<=notqb_s;endif;endif;q<=q_s;qb<=qb_s;endprocess;endjkff_art;T触发器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_signed.all;entitytffisport(t,clk:instd_logic;q:outstd_logic);end;architecturetff_artoftffissignalq_temp:std_logic;beginp1:process(clk)beginifrising_edge(clk)thenift='1'then--当T=1时T触发器具有2分频的功能q_temp<=notq_temp;elseq_temp<=q_temp;endif;endif;q<=q_temp;endprocess;q<=q_temp;endtff_art;4.2.2计数器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt4ISport(clk:instd_logic;q:outstd_logic_vector(3downto0));endcnt4;architecturebehaveofcnt4issignalq1:std_logic_vector(3downto0);beginprocess(clk)beginif(clk'eventandclk='1')thenq1<=q1+1;endif;endprocess;q<=q1;endbehave;一般计数器设计libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt10isport(clk,rst,en,updown:instd_logic;cq:outstd_logic_vector(3downto0));endcnt10;architecturebehaveofcnt10isbeginprocess(clk,rst,en,updown)variablecqi:std_logic_vector(3downto0);beginifrst='1'thencqi:=(others=>'0');--计数器异步复位elsif(clk'eventandclk='1')then--检测时钟上升沿ifen='1'then--检测是否允许计数（同步使能）ifupdown='0'thenifcqi<9thencqi:=cqi+1;--允许计数,检测是否小于9elsecqi:=(others=>'0');--大于9，计数值清零endif;elseifcqi>0thencqi:=cqi-1;--检测是否大于0elsecqi:=(others=>'1');---否则，计数值置1endif;endif;endif;endif;cq<=cqi;--将计数值向端口输出endprocess;endbehave;4.2.3分频器libraryieee;usestd_logic_1164.all;usestd_logic_unsigned.all;entityfreq1isport(clk:instd_logic;d:instd_logic_vector(7downto0);fout:outstd_logic);end;architectureoneofdvfissignalfull:std_logic;beginp_reg:process(clk)variablecnt8:std_logic_vector(7downto0);beginifclk'eventandclk='1'then--检测时钟上升沿ifcnt8=''11111111''thencnt8:=d;--当CNT8计数计满时，输入数据D被同步预置给计数器CNT8full<='1';--同时使溢出标志信号FULL输出为高电平elsecnt8:=cnt8+1;--否则继续作加1计数full<='0';--且输出溢出标志信号FULL为低电平endif;endif;endprocessp_reg;p_div:process(full)variablecnt2:std_logic;beginiffull'eventandfull='1'thencnt2:=notcnt2;--如果溢出标志信号FULL为高电平，T触发器输出取反ifcnt2='1'thenfout<='1';elsefout<='0';endif;endif;endprocessp_div;end;4.2.4移位寄存器libraryieee;useieee.std_logic_1164.all;entityshiftisport(clk,c0:instd_logic;--时钟和进位输入md:instd_logic_vector(2downto0);--移位模式控制字d:instd_logic_vector(7downto0);--待加载移位的数据qb:outstd_logic_vector(7downto0);--移位数据输出cn:outstd_logic);--进位输出end;architecturebehaveofshiftissignalreg:std_logic_vector(7downto0);signalcy:std_logic;beginprocess(clk,md,c0)beginifclk'eventandclk='1'thencasemdiswhen"001"=>reg(0)<=c0;reg(7downto1)<=reg(6downto0);cy<=reg(7);--带进位循环左移when"010"=>reg(0)<=reg(7);reg(7downto1)<=reg(6downto0);--自循环左移when"011"=>reg(7)<=reg(0);reg(6downto0)<=reg(7downto1);--自循环右移when"100"=>reg(7)<=C0;reg(6downto0)<=reg(7downto1);cy<=reg(0);--带进位循环右移when"101"=>reg(7downto0)<=d(7downto0);--加载待移数whenothers=>reg<=reg;cy<=cy;--保持endcase;endif;endprocess;qb(7downto0)<=reg(7downto0);cn<=cy;--移位后输出endbehav;4.3状态机逻辑电路设计4.3.1一般状态机设计libraryieee;useieee.std_logic_1164.all;entitys_machineisport(clk,reset:instd_logic;state_inputs:instd_logic_vector(0to1);comb_outputs:outintegerrange0to15);ends_machine;architecturebehvofs_machineistypefsm_stis(s0,s1,s2,s3);--数据类型定义，状态符号化signalcurrent_state,next_state:fsm_st;--将现态和次态定义为新的数据类型beginreg:process(reset,clk)--主控时序进程beginifreset='1'thencurrent_state<=s0;--检测异步复位信号elsifclk='1'andclk'eventthencurrent_state<=next_state;endif;endprocess;com:process(current_state,state_inputs)--主控组合进程begincasecurrent_stateiswhens0=>comb_outputs<=5;ifstate_inputs="00"thennext_state<=s0;elsenext_state<=s1;endif;whens1=>comb_outputs<=8;ifstate_inputs="00"thennext_state<=s1;elsenext_state<=s2;endif;whens2=>comb_outputs<=12;ifstate_inputs="11"thennext_state<=s0;elsenext_state<=s3;endif;whens3=>comb_outputs<=14;ifstate_inputs="11"thennext_state<=s3;elsenext_state<=s0;endif;endcase;endprocess;endbehv;4.3.2状态机的应用libraryieee;useieee.std_logic_1164.all;entityasm_ledisport(clk,clr:instd_logic;led1,led2,led3:outstd_logic);end;architectureaofasm_ledistypestatesis(s0,s1,s2,s3,s4,s5);--对状态机的状态声明signalq:std_logic_vector(0to2);signalstate:states;beginp1:process(clk,clr)beginif(clr='0')thenstate<=s0;elsif(clk'eventandclk='1')thencasestateiswhens0=>state<=s1;whens1=>state<=s2;whens2=>state<=s3;whens3=>state<=s4;whens4=>state<=s5;whens5=>state<=s0;whenothers=>state<=s0;endcase;endif;endprocessp1;p2:process(clr,state)beginif(clr='0')thenled1<='0';led2<='0';led3<='0';elsecasestateiswhens0=>led1<='1';led2<='0';led3<='0';whens1=>led1<='0';led2<='1';led3<='0';whens2=>led1<='0';led2<='1';led3<='0';whens3=>led1<='0';led2<='0';led3<='1';whens4=>led1<='0';led2<='0';led3<='1';whens5=>led1<='0';led2<='0';led3<='1';whenothers=>null;endcase;endif;endprocessp2;end;第6章EDA仿真技术应用实例6.1带使能和片选端的16：4线优先编码器设计子模块设计源代码：libraryieee;useieee.std_logic_1164.all;entitypencoderisport(d:instd_logic_vector(7downto0);ei:instd_logic;--ei:enableinputgs,eo:outbit;--gs:chipselectoutput;eo:enableoutputq2,q1,q0:outstd_logic);endpencoder;architectureencoderofpencoderisbeginprocess(d)beginif(d(0)='0'andei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0'andei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0'andei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0'andei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0'andei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0'andei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0'andei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0'andei='0')then--d7priotyencoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';elsif(d="11111111"andei='0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';endif;endprocess;endencoder;6.27段显示译码器设计译码器设计源代码：libraryieee;useieee.std_logic_1164.all;entitydecoder47isport(lt,ibr,ib_ybr:inbit;a:instd_logic_vector(3downto0);y:outstd_logic_vector(6downto0));enddecoder47;architectureartofdecoder47isbeginprocess(lt,ibr,ib_ybr,a)variables:std_logic_vector(3downto0);begins:=a(3)&a(2)&a(1)&a(0);iflt='0'andib_ybr='1'theny<="1111111";--检查七段显示管是否正常elsifibr='0'anda="0000"theny<="0000000";elsecasesiswhen"0000"=>y<="1111110";--7Ewhen"0001"=>y<="0110000";--30when"0010"=>y<="1101101";--6Dwhen"0011"=>y<="1111001";--79when"0100"=>y<="0110011";--33when"0101"=>y<="1011011";--5Bwhen"0110"=>y<="0011111";--5Fwhen"0111"=>y<="1110000";--70when"1000"=>y<="1111111";--7Ewhen"1001"=>y<="1110011";--7Bwhen"1010"=>y<="0001101";--0Dwhen"1011"=>y<="0011001";--19when"1100"=>y<="0100011";--23when"1101"=>y<="1001011";--4Bwhen"1110"=>y<="0001111";--0Fwhen"1111"=>y<="0000000";endcase;endif;endprocess;endart;6.3带异步清零端的12位二进制全加器设计子模块源代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityadder4bisport(clr,cin:instd_logic;a,b:instd_logic_vector(3downto0);s:outstd_logic_vector(3downto0);cout:outstd_logic);endadder4b;architectureartofadder4bissignalsint:std_logic_vector(4downto0);signalaa,bb:std_logic_vector(4downto0);beginprocess(clr)beginifclr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;endif;s<=sint(3downto0);cout<=sint(4);endprocess;endart;顶层模块设计源代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityadder12bisport(clr,cin:instd_logic;a,b:instd_logic_vector(11downto0);s:outstd_logic_vector(11downto0);cout:outstd_logic);endadder12b;architectureartofadder12biscomponentadder4bisport(clr,cin:instd_logic;a,b:instd_logic_vector(3downto0);s:outstd_logic_vector(3downto0);cout:outstd_logic);endcomponent;signalcarry_out1:std_logic;signalcarry_out2:std_logic;beginu1:adder4bportmap(clr=>clr,cin=>cin,a=>a(3downto0),b=>b(3downto0),s=>s(3downto0),cout=>carry_out1);u2:adder4bportmap(clr=>clr,cin=>carry_out1,a=>a(7downto4),b=>b(7downto4),s=>s(7downto4),cout=>carry_out2);u3:adder4bportmap(clr=>clr,cin=>carry_out2,a=>a(11downto8),b=>b(11downto8),s=>s(11downto8),cout=>cout);endart;6.4带异步清零/置位端的JK触发器设计带异步清零/置位端的JK触发器源程序如下：libraryieee;useieee.std_logic_1164.all;entityjkff_logicisport(j,k,clk,clr,set:instd_logic;q:outstd_logic);endjkff_logic;architectureartofjkff_logicissignalq_s:std_logic;beginprocess(clk,clr,set,j,k)beginifset='0'thenq_s<='1';--异步置位elsifclr='1'thenq<='0';--异步复位elsifclk'eventandclk='1'thenif(j='0')and(k='1')thenq_s<='0';elsif(j='1')and(k='0')thenq_s<='1';elsif(j='1')and(k='1')thenq_s<=notq_s;endif;endif;q<=q_s;endprocess;endart;6.54位锁存器设计子模块设计源代码：libraryieee;useieee.std_logic_1164.all;entitylatch1bisport(d:instd_logic;ena:instd_logic;--使能端q:outstd_logic);endlatch1b;architectureartoflatch1bisbeginprocess(d,ena)beginifena='1'thenq<=d;endif;endprocess;endart;元件声明程序包设计源代码：libraryieee;useieee.std_logic_1164.all;packagemy_packageiscomponentlatch1port(d:instd_logic;ena:instd_logic;q:outstd_logic);endcomponent;end;顶层模块设计源代码：libraryieee;useieee.std_logic_1164.all;usework.my_package.all;--使用用户自定义的程序包entitylatch4disport(d:instd_logic_vector(3downto0);oen:inbit;q:outstd_logic_vector(3downto0));endlatch4d;architectureoneoflatch4dissignalsig_save:std_logic_vector(3downto0);begingetlatch:fornin0to3generate--用for_generate语句循环例化4个1位锁存器latchx:latch1portmap(d(n),g,sig_save(n));--关联endgenerate;q<=sig_savewhenoen='0'else"ZZZZ";endone;6.632进制多样型计数器设计（1）32进制同步加法计数器源程序32进制同步加法计数器源程序如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounter_plusisport(clk,clr:instd_logic;dout0,dout1:outstd_logic_vector(3downto0));end;architectureartofcounter_plusissignald0,d1:std_logic_vector(3downto0);--d0代 表 关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf 个位，d1代表十位beginprocess(clk,clr,)beginifclr='1'thend1<=(others=>'0');d0<="0000";--同步清零elsifclk'eventandclk='1'thenif(d1=3andd0=1)thend1<="0000";d0<="0000";--计数到32时清零elsif(d0=1)thend0<="0000";d1<=d1+1;elsed0<=d0+1;endif;endif;dout1<=d1;dout0<=d0;endprocess;endart;（2）32进制同步减法计数器源程序32进制同步减法计数器源程序如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounter_subisport(clk,clr:instd_logic;dout0,dout1:outstd_logic_vector(3downto0));end;architectureartofcounter_subissignald0,d1:std_logic_vector(3downto0);--d0代表个位，d1代表十位beginprocess(clk,clr)beginifclr='1'thend1<="0000";d0<="0000";--异步清零elsifclk'eventandclk='1'thenif(d1=0andd0=0)thend1<="0011";d0<="0001";--设定容量31elsif(d0=0)thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;endif;endif;dout1<=d1;dout0<=d0;endprocess;endart;（3）32进制同步可逆计数器源程序32进制同步可逆计数器源程序如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounter_reversibleisport(clk,clr,s:instd_logic;--s=1加法计数，s=0减法计数dout0,dout1:outstd_logic_vector(3downto0));end;architectureartofcounter_reversibleissignald0,d1:std_logic_vector(3downto0);--d0代表个位，d1代表十位beginprocess(clk,clr,s)beginifclr='1'thend1<="0000";d0<="0000";--异步清零elsif(clk'eventandclk='1')thenifs='1'thenif(d1=3andd0=1)thend1<="0000";d0<="0000";--计数到31时清零elsif(d0=1)thend0<="0000";d1<=d1+1;elsed0<=d0+1;endif;elsifs='0'thenif(d1=0andd0=0)thend1<="0011";d0<="0001";--设定容量31elsif(d0=0)thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;endif;endif;endif;dout1<=d1;dout0<=d0;endprocess;endart;（4）32进制异步加法计数器源程序32进制异步加法计数器源程序如下：①子模块D触发器源程序设计。libraryieee;useieee.std_logic_1164.all;entitydffrisport(clk,clr,d:instd_logic;q,qb:outstd_logic);end;architectureartofdffrissignalqin:std_logic;beginq<=qin;qb<=notqin;process(clk,clr)beginifclr='1'thenqin<='0';elsif(clk'eventandclk='1')thenqin<=d;endif;endprocess;endart;②顶层异步加法计数器源程序设计。libraryieee;useieee.std_logic_1164.all;entitycounter_ais--异步加法计数器port(clk,clr:instd_logic;count:outstd_logic_vector(4downto0));end;architectureartofcounter_aissignalcount_in:std_logic_vector(5downto0);componentdffrport(clr,clk,d:instd_logic;q,qb:outstd_logic);endcomponent;begincount_in(0)<=clk;getddfr:foriin0to4generateux:dffrportmap(clk=>count_in(i),clr=>clr,d=>count_in(i+1),q=>count(i),qb=>count_in(i+1));endgenerate;endart;6.78位多样型移位寄存器设计（1）8位串入/并出移位寄存器源程序8位串入/并出移位寄存器源程序如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityshift_risport(clr,clk,en,din:instd_logic;dout:bufferstd_logic_vector(7downto0));end;architectureartofshift_rissignaltemp:std_logic_vector(7downto0);beginprocess(clr,clk)beginifclr='0'thentemp<=(others=>'0');elsif(clk'eventandclk='1')thenif(en='1')thentemp<=shl(temp,"1");temp(0)<=din;endif;endif;endprocess;dout<=temp;endart;（2）8位并入/串出移位寄存器源程序8位并入/串出移位寄存器源程序如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityshift_pisport(clr,clk,en,load:instd_logic;din:instd_logic_vector(7downto0);dout:outstd_logic);end;architectureartofshift_pissignaltemp:std_logic_vector(7downto0);beginprocess(clr,clk)beginifclr='0'thentemp<=(others=>'0');elsif(clk'eventandclk='1')thenif(load='1')thentemp<=din;elsifen='1'thentemp<=shl(temp,'1');temp(0)<='0';endif;endif;endprocess;dout<=temp(7);endart;（3）8位双向移位寄存器源程序8位双向移位寄存器源程序如下：libraryieee;useieee.std_logic_1164.all;entitydcshiftis--双向移位寄存器port(clr,load,clk,s,dir,dil:instd_logic;data:instd_logic_vector(7downto0);dout:bufferstd_logic_vector(7downto0));enddcshift;architectureartofdcshiftissignaltemp:std_logic_vector(7downto0);beginprocess(clr,clk,load,s,dir,dil)beginifclr='0'thentemp<="00000000";elsif(clk'eventandclk='1')thenif(load='1')thentemp<=data;elsifs='1'thenforiin7downto1loop--实现右移循环temp(i-1)<=dout(i);endloop;temp(7)<=dir;elseforiin0to6loop--实现左移循环temp(i+1)<=dout(i);endloop;temp(0)<=dil;endif;endif;dout<=temp;endprocess;endart;6.8Moore状态机的设计针对有限Moore状态机采用了不同 方案 气瓶 现场处置方案 .pdf气瓶 现场处置方案 .doc见习基地管理方案.doc关于群访事件的化解方案建筑工地扬尘治理专项方案下载 ，其源程序分别如下：方案一：双进程有限Moore状态机libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymoore_stateisport(clk,clr,input:instd_logic;output:outstd_logic_vector(3downto0));end;architectureartofmoore_stateistypestate_typeis(s0,s1,s2,s3);--状态 说明 关于失联党员情况说明岗位说明总经理岗位说明书会计岗位说明书行政主管岗位说明书 signalstate:state_type;beginprocess1:process(clk,clr)--时钟进程beginifclr='1'then--状态机复位state<=s0;elsif(clk'eventandclk='1')thencasestateiswhens0=>ifinput='0'thenstate<=s1;endif;whens1=>ifinput='1'thenstate<=s2;endif;whens2=>ifinput='1'thenstate<=s3;endif;whens3=>ifinput='0'thenstate<=s0;endif;endcase;endif;endprocess;process2:process(state)--组合进程begincasestateiswhens0=>output<="0010";whens1=>output<="1001";whens2=>output<="1100";whens3=>output<="1110";endcase;endprocess;endart;方案二：三进程有限Moore状态机libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymoore_stateisport(clk,clr,input:instd_logic;output:outstd_logic_vector(3downto0));end;architectureartofmoore_stateistypestate_typeis(s0,s1,s2,s3);--状态说明signalcurrent_state,next_state:state_type;beginp1:process(current_state,input)--组合进程begincasecurrent_stateiswhens0=>ifinput='0'thennext_state<=s1;endif;whens1=>ifinput='1'thennext_state<=s2;endif;whens2=>ifinput='1'thennext_state<=s3;endif;whens3=>ifinput='0'thennext_state<=s0;endif;endcase;endprocessp1;p2:process(clk,clr)--时钟进程beginifclr='1'then--状态机复位current_state<=s0;elsif(clk'eventandclk='1')thencurrent_state<=next_state;endif;endprocessp2;p3:process(current_state)--组合进程begincasecurrent_stateiswhens0=>output<="0010";whens1=>output<="1001";whens2=>output<="1100";whens3=>output<="1110";endcase;endprocessp3;endart;方案三：用时钟同步输出信号的Moore状态机用时钟同步输出信号的Moore状态机，能很好的消除“毛刺”现象，但是输出端得到的信号值的时间要比普通的Moore状态机晚一个时钟周期。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymoore_stateisport(clk,clr,input:instd_logic;output:outstd_logic_vector(3downto0));end;architectureartofmoore_stateistypestate_typeis(s0,s1,s2,s3);--状态说明signalstate:state_type;beginprocess1:process(clk,clr)--时钟进程beginifclr='1'then--状态机复位state<=s0;output<=(others=>'0');elsif(clk'eventandclk='1')thencasestateiswhens0=>ifinput='0'thenstate<=s1;endif;output<="0010";whens1=>ifinput='1'thenstate<=s2;endif;output<="1001";whens2=>ifinput='1'thenstate<=s3;endif;output<="1100";whens3=>ifinput='0'thenstate<=s0;endif;output<="1110";endcase;endif;endprocess;endart;6.9Mealy状态机的设计针对有限Mealy状态机采用了不同方案，其源程序分别如下：方案一：双进程Mealy状态机的源程序如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymealy_stateisport(clk,clr,input:instd_logic;output:outstd_logic_vector(3downto0));end;architectureartofmealy_stateistypestate_typeis(s0,s1,s2,s3);--状态说明signalstate:state_type;beginprocess1:process(clk,clr)--时钟进程begin