小区电动车自动充电系统的研究-翻译

小区电动车自动充电系统的研究- 翻译 阿房宫赋翻译下载德汉翻译pdf阿房宫赋翻译下载阿房宫赋翻译下载翻译理论.doc 苏州大学本科生毕业 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 (论文)附件:外文文献资料与中文翻译稿 外文文献资料 收集:苏州大学 应用技术学院 10 电子班级,学号1016405034, ,蔡林波, WA New Contact-less Smart Card IC Using an On-Chip Antenna and an Asynchronous Micro-controller This paper describes a new generation of Contact-less Smart Card Chip which an on-chip coil connected to a power reception system and an integrates emitter/receiver module compatible with the IS0 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit micro-controller. Beyond the Contact-less Smart Card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-- m technology from ST-Micro-electronics. 1. INTRODUCTION The Smart Card market enters a new era, with a booming number of applications in various domains and new countries willing to use this technology. Smart Cards are becoming more and more ubiquitous and the trend is to integrate a card reader in all kind of equipment (PCs,PDAs, mobile phones, etc.). E-commerce, citizen administration, and others could be, through the Internet, good vehicles to allow service providers to develop new services using the Smart Card as a high-security key element. In this context, contact-less Smart Cards should play an important part. The absence of contact induces lower maintenance cost, improves ease of use, reliability, and, therefore, end-user satisfaction. They are declined in several types according to the location of the antenna. It can be on the card, on the module,or integrated directly on the chip. This later technique significantly decreases card fabrication cost. Moreover, as the user still inserts his card in 第 1 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 a reader slot, transactions remain as safe as when using cards with contacts. Since most applications require low-cost low-power systems, the goal of this work is integrate on a single chip an antenna, an ISO14443 compliant radio-frequency to emitter/receiver, together with an asynchronous micro-controller. Integrating the whole system on silicon should pave the way to new reliable low-cost Contact-less Smart Card chips. These main key technologies used to design this new Smart Card chip are presented in Section II. The Smart Card chip de-sign is detailed in Section III, and the design methodology is briefly described in Section IV. Experimental results are given in Section V. 2. INNOVATION The innovation of this chip lies in the association on the same die of two key technologies [9]: an integrated power reception system with an on-chip coil -bit CISC QDI asynchronous micro-controller [8]. This association [5], and an 8 enables us to take advantage of the asynchronous logic properties in order to decrease the design constraints of the integrated power reception system and also to increase the working domain of the digital processing part. In fact, the asynchronous logic has three interesting advantages valuable for the Contact-less Smart Card application considered here [6], [7]. Instead of being clock driven, asynchronous circuits are data driven which results in a lower mean-power consumption. Instead of implementing a central control unit, asynchronous circuits implement a distributed control system which results in smaller current peaks and then lower electromagnetic emission because the electrical activity is spread over time. Finally, instead of being ―clock timed‖,asynchronous circuits are self-timed which enables an automatic regulation of the performance. Hence, QDI asynchronous circuits are not sensitive to voltage variations, and runs at their maximum speed with respect to the power received. Since the QDI 8-bit micro-controller is so robust with respect to the power supply variations (see Section III), the design of the power reception system is made easier: lower average power delivered, as well as the peak power, and 第 2 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 simplified regulation of the supply voltage. This not only makes the design easier, but also decreases the area (smaller VDD smoothing capacitance).Finally, because of its low current peaks the QDI asynchronous micro-controller does not interfere with the load modulation used in the ISO 14 443 standard for the communication between the card and the reader. This enables the micro-controller to run while the chip is transferring data to the reader which decreases the complexity of the software and then the memory space requirements. 3. SMART CARDCHIP DESIGN The Smart Card chip is composed of four main blocks(Fig. 1). The RF front-end recovers power from the integrated antenna, which forms a transformer with the external reader antenna. The recovered power is then stabilized and supplies the whole chip: the asynchronous micro-controller and a synchronous dedicated interface between the RF block and the asynchronous circuit.Fig. 1. Chip architecture. This interface is driven by a reception-enable signal (REN)controlled by the micro-controller. In reception mode, the RF interface demodulates data sent by the reader. In emission mode,data are sent to the reader using a load modulation. The system is ISO14443-B compliant [10]. When the Smart Card is inserted in the reader slot, as soon as the stabilized supply reaches a sufficient level, reset is activated by the RF interface. The micro-controller executes the boot program contained in ROM and then waits for data coming from the reader. The communication between the reader and the Smart Card is functionally asynchronous. The combination of the REN signal and the start 第 3 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 and stop bits (the communication between the reader and the chip is made on an asynchronous mode, with start and stop bits), encapsulating the transmitted byte implements a half-duplex communication. A. Analog Block Design Since there are no contacts, power and data are recovered from RF signals emitted by the reader. The analog block is in charge of 1) powering the chip; 2) demodulating/modulating data from/to the reader; 3) recovering the clock used in the synchronous/asynchronous interface. Compared to other contact-less technologies [7], the card is inserted in a slot which ensures that the distance chip reader is kept constant and small: the variations in distance are within millimeters. This enables the integration of the coil on-chip. Then,there is no need for the voltage which is recovered from the RF power to be very well regulated,as it is the case for contact-less cards touch and go basis.‖ The design of the power management and which operate on a ― analog block circuitry is accordingly simplified. The block diagram of the RF front-end is described in Fig. 2.It is built of the following parts. 1) The full wave rectifier (FWR) is a bridge composed of nMOS and pMOS transistors. The electro-motive-force(EMF) induced in the on-chip antenna is applied to the FWR inputs. The negative output is connected to the bulk and the positive output is connected to a 500 pF smoothing capacitor. It delivers the nonregulated voltage NRV to the chip. Fig. 2. RF front-end block diagram 2) The clock recovery block extracts the 13.56-MHz clock from the RF carrier signal. For this purpose, the input of a Schmidt trigger is connected to one of the two antenna terminals. 第 4 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 3) The power-on detector. This block is composed of a voltage reference, a differential comparator and filters to reject modulation parasitics. It triggers a RESET when the NRV reaches a given level. 4) The data demodulator is based on NRV amplitude transitions due to NRZ coded transmission from reader to chip.The data demodulator extracts the data mixed with NRV,by detecting negative and positive transitions. The two outputs drive the inputs of an RS latch which makes the data available to the interface. 5)The load modulator is built of a resistor (Rmod, see Fig. 3)switched by an nMOS transistor controlled by the data to be sent to the reader. It induces an amplitude modulation in the inductor antenna. In emission, the modulator has to modulate the power absorbed by the chip at an 847-kHz BPSK rhythm. This is made by a modulation of I(NRV), I2. This induces an EMF in the reader solenoid. Fig. 3. Interface block diagram. B. Synchronous/Asynchronous Interface The block diagram of the interface is presented in Fig. 5. It is composed of a divider, a BPSK modulator and a block which formats the data coming from the external reader and from the micro-controller.The RF 13.56-MHz carrier is recovered and divided to provide a 847-kHz signal used to clock the interface. On the RF interface side, bytes are encapsulated with start and stop bits which are then received or emitted sequentially at the 847-kHz bit rate. On the micro-controller side, an asynchronous four-phase bundle-data protocol is used (8-bit data, request and acknowledge signals) to control data exchange with the QDI asynchronous micro-controller. This interface implements two types of conversion: protocol conversion and serial/parallel or parallel/serial conversions. It is designed as a synchronous finite state machine and therefore, some timing assumptions are made when sampling 第 5 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 asynchronous control signals like P5req and P4ack. When a data has to be emitted from the card, the REN signal is disabled by the micro-controller which asks for writing into the interface by asserting the P5req signal. The interface answers by asserting P5ack. The four-phase handshake protocol then completes with two return-to-zero phases as soon as the one byte buffer is empty. When receiving data from the reader, the REN signal is driven high and the micro-controller is ready to receive an input byte by asserting the P4ack signal. The interface answers rising the P4req signal as soon as a byte is available from the receiver. The handshake then completes with the return-to-zero phase. handshake protocol ensures that both the micro-controller and the interface The are available to accept and transmit a byte in emission or reception. Thus, the micro-controller will be idled as long as the interfacedoes not grant its request. program execution will resume when the data byte is finally sent or received. The A one-byte buffer allows the micro-controller and the interface to run concurrently. Failure may only occur in reception if the micro-controller does not read the byte in time. In that case, the interface overwrite the non-read byte. incoming This type of communication failures can be solved using software error-checking. C. QDI Asynchronous 8-bit Micro-controller The QDI asynchronous 8-bit micro-controller is a CISC machine, based on a dedicated ―luxurious‖ micro-architecture(Fig. 6). In order to facilitate the design of a ―C‖ compiler and also to limit memory accesses, we decided to integrate two different register-files: eight 8-bit registers are devoted to data, and eight 16-bit registers are devoted to pointers (including the program counter and the stack pointer). Specific arithmetic units are associated with each register files enabling concurrent computations of data and addresses. A dedicated unit is managing the standard status bits Z, N, V, and C. A peripheral unit is also included, supporting six 8-bit parallel ports (one input, four outputs, and 1 bidirectional used to control external flash memories and the synchronous/asynchronous interface) and four serial links (using a two-phase delay insensitive protocol compatible with our high-performance RISC asynchronous Aspro processor [4]). Moreover, the micro-controller integrates 16 kB RAM and 2 kB ROM.. The ROM includes a Built-In-Self-Test (BIST) program which is executed at reset according to the boot mode selected (eight modes are available). It is a 350 第 6 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 assembly instruction routine which performs a stuck-at-fault test which computes a signature written, on the fly, on one of the parallel port to report on self-test progress. The QDI asynchronous logic used is self-testable because a stuck-at fault on any input of any gate will cause a handshake to stop for ever (no ―premature firing‖ [2]). As a result, the BIST program will never produce a complete signature. Fig.6. Micro-controller architecture. • Instruction set The eight 8-bit data registers are named r0 to r7, and the eight 16-bit index registers i0 to i7, where i6 and i7 are the stack-pointer and the program-counter respectively. The controller implements the common arithmetic and logic instructions. All instructions are encoded within one word (16 bits).Four basic addressing modes are available (immediate, register, indexed with displacement, indexed post-incremented or pre-decremented) which can be used in conjunction with data or index register operands. Lastly, the controller implements a maskable interrupt mechanism and a ―wait for interrupt‖ instruction (Wfi). Table I summarizes the instruction set, note the ―copy‖ (Cp) and the ―Puch&Load‖ (Pl) instructions. A complete software development suite of tools is currently under development including a ―C‖ compiler, an assembler, a linker and a simulator. • Architecture design The micro-controller core is designed using the so-called quasi-delay insensitive 第 7 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 (QDI) logic [1], [8] . A four-phase protocol is used in conjunction with an n-rail encoding. This micro-controller, named MICA, has been a vector for developing new skills in the design of standard-cell based QDI asynchronous circuits. The design of MICA was focused on two correlated concerns: designing distributed asynchronous finite state machine and designing for low power. In order to reduce the power consumption of the micro-controller we have worked on minimizing the number and the energy cost of communication actions occurring during the execution of each instruction, and minimizing the number of sequential steps to perform each instruction. In other words, instead of designing the architecture around a large central sequencer, we have tried to distribute the sequencing implementation all over the architecture as much as possible. The asynchronous logic is particularly well suited to satisfy such a design approach since by nature the sequencing of an asynchronous circuit is performed by multiple local sequencers implementing handshaking communications and local treatments. 4. D ESIGN METHODOLOGY The Smart Card chip represents a complex system on chip with several different design styles. The analog has been designed in full custom. The synchronous/asynchronous interface between the analog 8block and the micro-controller has been modeled using VHDL as a synchronous finite state machine and synthesized with standard CAD tools. As regards to the asynchronous logic, the micro-controller was first described in CHP [1], a high-level language well suited to model asynchronous circuits. The model was then refined to obtain the final distributed architecture. Model validation was performed by VHDL simulation, thanks to a CHP to VHDL translator [3]. The synthesis of the CHP model into QDI logic was performed by hand and the schematic manually captured in a standard design framework. The micro-controller is thus built of 1) founder standard cells plus some specific cells (Muller gates) and of 2) founder synchronous low-power memories with additional specific interfaces. Gate-level and CHP co-simulation was then performed in VHDL to validate 第 8 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 each block after synthesis. After place & route, the complete system (excluded the analog block) was validated by simulating a VHDL back-an-notated gate level netlist. Finally, a switch level simulation was performed to estimate the core power consumption and thus determine the Smart Card power reception system characteristics. Fig. 7 describes the complete design flow we have set up. 5. E XPERIMENTAL RESULTS The chip was fabricated at the STMicroelectronics Crolles plant using a 6 metal-layer 0.25- m CMOS process. Pads are included in this first prototype in order to test the chip and perform measurements on both the digital and analog parts. The total chip area is 16 mm2 including these pads. The on-chip-coil is surrounding the chip . The coil is made of six turns implemented with the upper five metal layers. Its area is 1.5 mm The CISC micro-controller with its memory represents one million transistors. Fig. 4 shows the stabilization of the NRV current with respect to the VDD current variation. For validating the chip in a system environment, a reader connected to a PC via an RS232 port was designed. The reader includes the RF oscillator, the 10% ASK modulator, the BPSK detector, and provides 1 W under 6-V conditions. The chip was integrated on a prototype card. When inserting the card into the reader magnetic field (11 gauss, with load), a program is downloaded into the micro-controller RAM and data are exchanged between the external PC and the card. The circuit has been successfully validated using several program downloading, like dumping the micro-controller ROM or identifying a pin number. 6. CONCLUSION The chip presented in this paper is the first prototype that fully integrates a Contact-less Smart Card (antenna, power reception, RF communication and digital processing). It demonstrates that the design of such System-On-Chip is feasible using the latest industrial technologies. Future investigations will focus on the benefits of the use of an asynchronous micro-controller with respect to area gain (VDD smoothing capacitor), design complexity reduction and software 第 9 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 simplification. Another very interesting and promising perspective is to investigate the ability of asynchronous circuits to improve Smart Card circuits resistance against well known attacks such as DPA analysis, fault and glitch attacks [11]. REFERENCES [1] A. J. Martin, ―Synthesis of asynchronous VLSI circuits,‖ Caltech,CS-TR-93–28, 1993. [2] H. Hulgaard, S. M. Burns, and G. Borriello, ―Testing asynchronous circuits: A survey,‖ Integration: the VLSI Journal, vol. 19, pp. 111–131,1995. [3]M. Renaudin, P. Vivet, and F. Robin, ―A design framework for asynchronous/synchronous circuits based on CHP to HDL translation,‖ in Proc. ASYNC, Barcelona, Spain, Apr. 1999, pp. 135–144. [4] , ―ASPRO: an 16-bit RISC asynchronous microprocessor with DSP capabilities,‖ in ESSCIRC ,Duisburg, Germany, Sept. 1999, pp.428–431. [5] J. Bouvier, Y. Thorigne, S. A. Hassan, M. J. Revillet, and P. Senn, ― in A Smart Card CMOS circuit with magnetic power and communications interface,‖ Proc. ISSCC, San Francisco, CA, Feb. 1997, pp. 296–297. [6] A. Abrial, J. Bouvier, M. Renaudin, and P. Vivet, ―A contactless Smart-Card chip based on an asynchronous 8-bit microcontroller,‖ in Asynchronous Circuits Design (ACiD) Workshop, Grenoble, France,Jan./Feb. 2000. [7] J. Kessels, T. Kramer, G. den Besten, and V. Timm, ―Applying asynchronous circuits in Contactless Smart Cards,‖ in Proc. ASYNC,Tel Aviv, Israel, Apr. 2000, pp. 36–44. [8] M. Renaudin, ―Asynchronous circuits and systems: a promising design alternative ,‖Microelectronics for Telecommunications: Managing High Complexity and Mobility , vol. 54, no. 1-2, pp. 133–149, Dec. 2000. [9] ―Composant micro-électronique intégrant des moyens de traitement numé rique asynchrone et une interface de couplage électromagnétique sans contact,‖ French Patent 9 908 485. [10] Identification cards—contactless integrated circuits cards—proximity cards, Standard ISO/IEC FCD 14 443–2. [11] D. P. Maher, ―Fault induction attacks, tamper resistance, and hostile reverse engineering in perspective,‖ in Proc. LNCS 1318, Financial Cryptography , 第 10 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 1997. 第 11 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 中文翻译稿 翻译:苏州大学 应用技术学院 10 电子班级,学号1016405034, ,蔡林波, 一种新的非接触式智能IC卡，使用片上天线和一个异步微控制器 本文介绍了新一代非接触式智能卡芯片，它集成了一个片上线圈，连接到一个电源接收系统和发射/接收模块符合ISO 14443标准兼容，异步准延迟敏感(QDI)8位微控制器。这种新的芯片以外的非接触式智能卡的应用领域，演示了该系统的芯片集成功率接收和管理、射频通信和信号处理是可行的。它综合了模拟/数字以及同步/异步逻辑器件，并安装了一个意法半导体公司的0.25微米、CMOS六金属层的半导体。。 1. 介绍 智能卡市场进入了一个新时代,不断增长的应用于各种领域，新国家愿意使用这种技术。 智能卡越来越无处不在,这一趋势是将读卡器整合在所有类型的设备(电脑、掌声电脑、手机等等)。公民管理，电子商务，以及其他可以通过互联网，良好的车辆，使服务提供商能够开发新的服务，使用智能卡的高安全性的关键因素。 在这种背景下,非接触式智能卡扮演一个重要的角色。非接触诱导降低维护成本,提高了易用性、可靠性和终端用户的满意度。他们根据天线的位置减少了几种类型。它可以是上网卡,模块,或直接集成芯片上。后来的技术大大降低了卡的制造成本。此外，由于用户仍然将卡插在读卡器插槽，交易保持接触卡使用时的安全。由于大多数应用程序需要低成本的低功耗系统,这项工作的目标是在单个芯片上集成天线，符合ISO14443标准的射频发射器/接收器，异步微控制器。整个系统集成在硅片上，是一种新的可靠的低成本非接触式智能卡芯片的方式。 设计这个新智能卡芯片的主要关键技术在第二部分给出。智能卡芯片设计的详细刊登在第三节,设计方法在第四节进行了简要评述。在第五部分给出了实验结果。 2. 创新 该芯片的创新在于该协会位于同一芯片上的两个[9]的关键技术:一个带有片上线圈的集成接收系统[5]，和一个8位异步微控制器]。这会使我们采取利用异步逻辑性能的方 第 12 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 式，减少设计接收系统的集成功率的约束条件，并增加工作领域的数字处理部分。 事实上,异步逻辑对非接触式智能卡片的应用有三个有趣的优点[6]、[7]。而不是被时钟驱动，异步电路是数据驱动导致一个较低的平均功率消耗。而不是实现一个中央控制单元,异步电路实现分布式控制系统,形成较小的电流峰值,进而降低电磁辐射, 由于电活动随时间分布。最后,而不是被‖时钟定时―,异步电路计时自动调节性能。因此,异步电路QDI电压变化是不敏感的,并且在接收功率上运 行最大的速度。 由于QDI 8位微控制器对电力供应的变化是有力的(见第三节)，电力接收系统的设计变得更加容易:较低的平均功率交付,以及峰值功率,简化了供应电源的监管。这不仅使设计更简单,也减少了地区(更小的VDD平滑电容)。最后，因为它的低电流峰值QDI的异步单片机不会干扰负载调制，这种调制用于ISO14443标准之间的卡和读者的通信。这使得单片机运行而芯片是将数据传输到读者从而降低软件的复杂性和内存空间需求。 3. 智能CARDCHIP设计 这种智能卡由四个主要模块组成(图1)。射频前端从集成天线恢复电力，这形成了一个具有外部天线的变压器。这种复原的电力是稳定的，供应整个芯片:异步单片机和一个连接射频模块与异步电路的同步专用接口。 一个由微控制器控制的可接收信号驱动这个接口。在接收模式下，射频接口解调发送给读者的数据。在发射模式下，数据被发送给使用负载调制的读者。这个系统兼容ISO14443-B[10]。 当智能卡被插入阅读器槽中,一旦稳定供应达到足够的水平,射频接口激活重置。单片机执行包括ROM的引导程序包，然后等待来自读者的数据。读者与智能卡之间的通信在功能上是异步的。结合的信号,启动和停止位(读者与芯片的通信是一种以开始和停止位的异步模式),封装传输字节实现了一半双通信。 第 13 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 A 模拟块的设计 由于没有联系,通过读者发射的射频信号来恢复权力和数据。模拟块负责 1)驱动芯片; 2)调制/解调读者发送的或接收的数据; 3)恢复应用于同步/异步接口的时钟。 与其他的非接触式技术[7]相比,卡被插入一个插槽中,这确保距离芯片读者保持不变和变小:在不同的毫米距离内。这增强了芯片上的线圈的集成。然后,非常良好的恢复电压功率的监管是没有必要,因为它是如此的非接触式智能卡，运行于―触摸和基础‖。电源管理和模拟块电路的设计是相对的简化。射频前端的方框图如图2。它由以下几个部分构建。 1)完整的波整流器(FWR)是一座由nMOS和pMOS晶体管组成的桥。EMF的感应芯片上的天线被应用于FWR输入。负极的输出连接到体积与正极的输出连接到一个500pF平滑电容器。这能给芯片提供无规则的电压。 图2 射频前端框图 2)时钟恢复模块从射频载波信号中提取13.56MHz时钟。为了这个目的,施密特触发器的输入连接到两个天线终端的一端。 3)加电探测器。这个模块由一个参考电压源,比较器和过滤器，用于抵制寄生调制。当达到给定水平，它会引发重置。 4)由于来自读者芯片的NRZ编码传输，数据解调是基于NRV振幅转换的。通过检测的正电平和负电平的转换，数据解调提取混合NRZ的数据。这两个的输出驱动RS门闩的输入，使数据可用于接口。 5)负载调制器是建立一个电阻器(Rmod,见图3)，通过一个nMOS晶体管组成的开关控制数据发送给读者。它包括振幅调制的电感天线。在排放中,调制器已经以调整功率吸收847千赫芯片BPSK节奏。这由一位调制(NRV)组成。这包括EMF的读者电磁阀。EMF值是相互电感和载波频率。 第 14 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 B .同步/异步接口 接口框图如图5。它由一个护栏,一块BPSK调制器和来自外部的读者和微控制器的 格式 pdf格式笔记格式下载页码格式下载公文格式下载简报格式下载 化数据模块。 RF 13.56MHz被恢复和分裂，用于提供用于时钟接口的847KHz信号。就RF接口方面而言,字节以启动和停止位的方式被封装,然后按顺序发出或接收847KHz/s。就单片机而言,异步四段 协议 离婚协议模板下载合伙人协议 下载渠道分销协议免费下载敬业协议下载授课协议下载 被使用(8位数据、请求和承认的信号)，用来控制数据交换与QDI异步微控制器。这个接口实现了两种类型的转换:协议转换和串行或并行的或并行/连环转换。它被设计成一个同步的有限状态机,因此，通过抽样时异步控制信号P5req和P4ack，做出一些时间的假设。当一个数据必须通过卡发送时,REN 14信号是禁用的单片机要求编写接口中断P5req信号。接口通过P5ack回答。一旦一个字节缓冲区为空时，四段握手协议完成两个归0段。当从读者那收到数据时,REN信号通过P4ack被驱使为高和单片机准备重新接收输入字节。当P4ack上升，一旦一个字节可用时，接口做出应答。握手就完成归0阶段。握手协议保证单片机和接口在发射和接收时能够接受和传递一个字节。因此,只要接口并没有赋予请求，单片机将闲置。执行程序将恢复到数据字节最后发送或接收时的状态。一个1字节缓冲区允许单片机和接口中并发地运行。如果单片机不能及时读传入的字节，失败可能会发生在接收时。在这种情况下,接口重写未读的字节。这种类型的通信失败可以通过使用软件错误检查来解决。 C. QDI异步的8位微控制器 异步的8位微控制器的QDI是CISC机,基于一个专用的―豪华‖微结构(图6)。为了C编译器设计的方便和有限内存的访问,我们决定将两种不同的寄存器文件:用于数据的8位寄存器和8个用于指针(包括程序计数器和堆栈指针)的16位寄存器。特定的算术单元与相关各注册文件启用并发送计算的数据和地址。一个专门的部门负责管理标准状态位Z,N,V,C .周边单元也包括支持六个8位并行端口(一个输入,四个输出,而1双向用来控制外部闪存和同步/异步接口)和四个串行链接(使用符合我们的高性能异步Aspro RISC处理器[4])的两阶段延迟不敏感协议。此外,在单片机集成16 kB的RAM和2 kB ROM。 第 15 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 所谓的准延迟敏感(广辉)逻辑设计以单片机为核心[1]，[8]。一个四阶段的协议是n轨编码一起使用。该微控制器，名为云母，开发新的技能一直是基于标准单元的异步电路设计的一个向量。云母的设计侧重于两个相关的问题:设计分布式异步有限状态机和低功耗设计。 为了减少微控制器的功耗，我们一直在减少数量和每个指令的执行过程中发生的通信行动的能源成本，减少执行每条指令的顺序步骤的数量。换句话说，我们周围的一大片中央序设计的架构，而不是试图分发到各处尽可能的顺序执行。异步逻辑特别适合满足这样的设计方式，因为异步电路的执行顺序由多个本地时序实施握手通信和局部治疗。因此，云母结构被设计成一个分布式系统，每个部分提供特定的服务。例如，两个寄存器文件，状态寄存器和内存集成管理内存资源的地方单元。这些模块实现的功能，如―读‖，―写‖，―读，然后写‖，或更复杂的功能，如:读一个字节，递增/递减指针/地址，读取相应的字节(例如使用CP和PL指令这些功能)。采用这种方法大大简化了主程序像云母CISC微处理器的设计。然后，它最大限度地减少了主程序，其直接形象的复杂性与每个指令相关的运作所消耗的功率。事实上，复杂指令的执行不是在主序水平简单的指令执行。此外，这种分布式的方法，最大限度地减少以来最低交易数量，通过总线(例如内存访问)发生通信消耗的功率。 由于低功耗约束，以计算能力为优先级的目标应用程序，介绍了流水线阶段的最低数量。这并不妨碍并行执行指令的子部分，它仅仅意味着不支持并行执行指令。但是在某些情况下，后续的指令可能会部分重叠。最后，在信号电平，沟通渠道，使用低功耗的数据编码。使用双轨编码，而不是我们已经实施的N线的N-导轨编码(也称为―一热‖)，即，一个活跃的交易(而不是一个两个双轨)。架构的不同部分都通过使用5轨至12轨数据的 第 16 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 编码，最大限度地减少过渡行动，每通信通道由主序控制，从而最大限度地减少动态功耗。4轨编码数据的数据路径(8位和16位)是要求基数为4的逻辑/算术处理单元的设计。寄存器文件的设计也是4轨编码数据。而位寄存器，是他们建立的两位数的寄存器，每个数字代 表 关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf 四个值。 微控制器的性能 测试芯片已经设计、制造和测试，在整合微控制器的智能卡芯片。微控制器的BIST测试已经很容易，功能齐全的首个硅在3 V至0.8 V(0.25米CMOS技术应用于额定电压2.5伏)。表二给出了在不同的电压(根据总电流消耗的核心，内存和垫)的MIPS(每秒执行指令数的BIST程序运行时)，电源和MIPS /瓦的数字。值得注意的是，在1V情况下，该芯片只消耗800瓦，仍然提供4.3 MIPS的运算能力。在0.8 V时，芯片功耗小于400W。 4. 设计方法 智能卡芯片上复杂的系统芯片具有几个不同的设计风格。模拟已在全定制设计。模拟模块和微控制器之间的同步/异步接口已同步有限状态机的VHDL建模和标准的CAD 工具. 关于异步逻辑合成，首先选单片机描述[1]，热电联产高级语言，非常适合模型异步电路。对该模型改进以获得最后的分布式体系结构。 VHDL仿真模型验证，以VHDL的翻译[3]。广辉逻辑合成CHP模型在一个标准的框架设计中进行手工和原理手动捕获，因此，将微控制器内置1)标准的细胞，再加上一些特定的细胞(穆勒盖茨)2)同步与额外的特定接口的低功耗的记忆。在VHDL门级和热电联产的协同仿真，然后每块合成后进行验证。 布局布线后，完整的系统(不包括模拟模块)进行了验证，模拟的VHDL背记谱门级网表。最后，一个开关级仿真进行核心功耗的估计，从而确定智能卡电源接收系统的特点。 5. 实验结果 该芯片是意法半导体的Crolles厂使用6金属层0.25米CMOS工艺制造。垫在这第一个原型以测试芯片和执行上的数字和模拟部分的测量。芯片总面积为16毫米，其中包括这些垫。芯片上的线圈周围的芯片。线圈上的五个金属层实施的6个转弯。它的面积是1.5毫米的CISC微控制器，其内存代表100万个晶体管。图4到VDD的电流变化的营养素参考值电流的稳定。 为验证系统环境中的芯片设计，通过RS232端口连接到PC的读者。读者包括射频振荡器，10,的ASK调制，BPSK的探测器，并提供6 V条件下1瓦。该芯片集成在一个原型卡。当插入卡进入读卡器磁场(11高斯，带负荷)，程序下载到微控制器RAM和外部PC卡之间交换数据。该电路已成功验证使用多个程序下载，像倾倒的单片机ROM或确定一个PIN 第 17 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 号码。 6. 结论 本文提出的芯片是第一个原型，充分整合接触式智能卡(天线，接收功率，射频通信 和数字信号处理)。它表明，如片上系统的设计采用了最新的工业技术是可行的。今后的 调查将集中在使用面积增益(VDD平滑电容器)，减少设计的复杂性和软件简化异步微控制 器的好处。另一个非常有趣的、有前途的角度来探讨异步电路的能力，提高对智能卡电路 的电阻，如德新社分析，故障和故障攻击[11]这是众所周知的攻击。 参考文献 [1] A. J. Martin, ―Synthesis of asynchronous VLSI circuits,‖ Caltech,CS-TR-93–28, 1993. [2] H. Hulgaard, S. M. Burns, and G. Borriello, ―Testing asynchronous circuits: A survey,‖ Integration: the VLSI Journal, vol. 19, pp. 111–131,1995. [3]M. Renaudin, P. Vivet, and F. Robin, ―A design framework for asynchronous/synchronous circuits based on CHP to HDL translation,‖ in Proc. ASYNC, Barcelona, Spain, Apr. 1999, pp. 135–144. [4] , ―ASPRO: an 16-bit RISC asynchronous microprocessor with DSP capabilities,‖ in ESSCIRC ,Duisburg, Germany, Sept. 1999, pp.428–431. [5] J. Bouvier, Y. Thorigne, S. A. Hassan, M. J. Revillet, and P. Senn, ― A Smart Card CMOS circuit with magnetic power and communications interface,‖ in Proc. ISSCC, San Francisco, CA, Feb. 1997, pp. 296–297. [6] A. Abrial, J. Bouvier, M. Renaudin, and P. Vivet, ―A contactless Smart-Card chip based on an asynchronous 8-bit microcontroller,‖ in Asynchronous Circuits Design (ACiD) Workshop, Grenoble, France,Jan./Feb. 2000. [7] J. Kessels, T. Kramer, G. den Besten, and V. Timm, ―Applying asynchronous circuits in Contactless Smart Cards,‖ in Proc. ASYNC,Tel Aviv, Israel, Apr. 2000, pp. 36–44. [8] M. Renaudin, ―Asynchronous circuits and systems: a promising design alternative ,‖Microelectronics for Telecommunications: Managing High Complexity and Mobility , vol. 54, no. 1-2, pp. 133–149, Dec. 2000. [9] ―Composant micro-électronique intégrant des moyens de traitement numé rique asynchrone et une interface de couplage électromagnétique sans contact,‖ 第 18 页 苏州大学本科生毕业设计(论文)附件:外文文献资料与中文翻译稿 French Patent 9 908 485. [10] Identification cards—contactless integrated circuits cards—proximity cards, Standard ISO/IEC FCD 14 443–2. [11] D. P. Maher, ―Fault induction attacks, tamper resistance, and hostile reverse engineering in perspective,‖ in Proc. LNCS 1318, Financial Cryptography , 1997. 第 19 页