逐次逼近型模数转换器中的失配校准技术英文

逐次逼近型模数转换器中的失配校准技术英文 Mismatch CalibrationTechniquesinSuccessiveApproximation 2012-07-19#############2012-07-19######2#0#12-07-19######## Analog2to2Digital Converters †Wang Pe, i L ong Sh nali , and W iau n hJu i ( )N at i onal A S I C S y ste m En gi nee ri n g Cent e r , S out heast U ni ve rsi t y , N an j i n g 210096 , Chi na Abstract : C o mp a r a t o r of f s e t c a ncell a t i o n a n d c ap a ci t o r s elf2c ali b r a t i o n t e c h ni ques use d i n a s ucc essi ve ap p r o xi m a2 ( ) t i o n a nal og2t o2di gi t al c o n ve r t e r SA2A D C a r e desc ri be d . Th e c ali b r a t i o n ci r c ui t w o r ks i n p a r allel wi t h t h e SA2 A D C b y a d di ng a d di t i o n al c ali b r a t i o n cl oc k c ycles t o p urs ue hi g h a cc ur a c y a n d l ow p ow e r c o ns u mp t i o n , a n d t he c ali b r a t e d r es ol ut i o n c a n be up t o 14bi t . This ci r c ui t is us e d i n a 10bi t 3Msp s s ucc essi ve ap p r o xi m a t i o n A D C . This 2 μc hip is r e aliz e d wi t h a n SM I C 01 18m 1 . 8V p r oc ess a n d occ up i es 01 25 m m. I t c o ns u mes 31 1 m W w h e n op e r a t i ng a t 11 8M Hz . Th e me as ur e d S I N A D is 551 9068dB , S FD R is 641 5767dB , a n d T H D is - 741 8889dB w h e n s a mp li n g a 320 k Hz si ne w a ve . Key words : a nal og2t o2di gi t al c o n ve r t e r ; s ucc essi ve ap p r o xi m a t i o n ; s elf2c ali b r a t i o n t ec h ni q ues EEACC : 2220 CLC number : TN 432 Document code : A ( ) Article ID : 025324177 20070921369206 [ 4 ] p ut si gnal . L e ung et a l . me r ged small cap acito r s 1 Introduct ion f ro m t he bi gge r cap acito r s i n se rie s. The cali bratio n i s ba se d o n a ddi ng o r re mo vi ng small cap acito r s to a nd op erati ng volt a ge A s device di me n sio n s get a goo d mat ch i n t he a r ra y. B ut it p ro vi de s o nl y co nti nue to be scaled do w n ,a nalo g ci rcuit s a re be2 a re sol utio n of 1/ 8 of t he unit cap acit a nce val ue C i ng p u she d to t hei r op e ratio nal li mit s. Perfo r ma nce de gra datio n such a s sa mp li ng li nea rit y a nd si gnal2 a nd ma ke s t he de si gn of t he la yo ut mo re diffic ult . ( )Thi s p ap er p re se nt s self2cali bratio n met ho d s to2noi se ratio SN R due to li mit ed si gnal swi ng fo r SA2ADCs , wit h t he cali bratio n mo dule , a nd met ho d s a re needed to i m2 e xi st s , so cali bratio n bo t h co mp a rato r off set volt a ge a nd cap acito r mi s2 p ro ve t he acc uracy of a nalo g ci rc uit s. ( ) The acc uracy of a nalo g2to2di git al A/ Dco n2 mat che s ca n be eff ectivel y eli mi nat e d , t h u s i mp ro2 ve r t er s i s of t e n li mit e d by t he mi smat ch of bo t h vi ng t he p e rfo r ma nce s of SA2ADCs. The ci rcuit p a ssive co mpo ne nt s a nd i deall y i de ntical t ra n si sto r s r un s i n p a rallel wit h t he p ropo sed SA2ADC by of t he ci rcuit s. Co mp a rato r off set volt a ge a nd ca2 a ddi ng a dditio nal cali bratio n clock cycle s. The p acito r mi smat ch ca n ca u se ha r mo nic di sto rtio n a nd block dia gra m of t he p ropo sed SA2ADC i s sho w n i n t h u s great l y i nf l ue nce t he acc uracy of SA2ADCs. Fi g1 1 ,i n w hich t he cali bratio n mo dule i s i ndicat ed [ 1 ] by t he da shed li ne . A p se udo2diff e re ntial i np ut Inp ut a nd o utp ut sto ra geca n eli mi nat e t he off set st a ge i s a dop t ed fo r bo t h i mp ro vi ng po wer supp l y volt a ge of co mp a rato r s ,but t hi s requi re s a dditio nal rejectio n a nd rejecti ng co mmo n mo de noi se . cap acito r s o n t he si gnal p at h , t h u s reduci ng t he ba ndwi dt h . F ur t her mo re , e r ro r s due to cha nnel [ 2 ] cha r ge i njectio n ca nno t be o ve rco me eit he r . Fo r 2 Comparator off set cancellat ion cap acito r mi smat c h , la se r t ri mmi ng ca n gua ra nt ee t he re sol utio n ,but it i s a n e xp e n sive a nd ti me2co n2 To ac hieve hi ghe r sp eed , a re ge ne ratio n co m2 [ 3 ] su mi ng p rocedure . Ta n et al . a dop t ed a sub2ca2 [ 5 ] p a rato r i s u sed . In o r der to ma xi mize t he sp ee d , p acito r a r ra y to cali brat e t he e r ro r of t he cap acito r [ 6 ] t he number of p re2a mp s sho ul d be 6. Co n si deri ng a r ray . Ho weve r ,t hi s met ho d i s li mit e d by t he p a ra2 t he t radeoff amo ng speed ,power and area ,2 stage p re2 sitic a nd off set s of t he sub2cap acito r a r ra y it self , amp s are used in t his design . In order to co mpensate w hile al so i ncrea si ng t he cap acitive loa d of t he i n2 2012-07-19#############2012-07-19######2#0#12-07-19######## Fig1 1 Block diagram of p ropo sed SA_ADC t he di sa dva nt a ge s of t he off set ca ncellatio n t ech2 Q′C1 a nd QNM16 a re t he cha r ge s sto red o n C1 w here nique s me ntio ne d a bo ve ,negative f eedback i s i nt ro2 a nd N M16 af t er cha r ge redi st ri butio n . Beca u se t he val ue of t he cap acito r fo r me d by duce d. By a dj u sti ng t he loa d of t he fi r st st a ge p re2 ( ) a mp t h ro ugh ne gative f ee dback , t he i np ut off set N M16 i s W L C, t he volt a ge va riatio n of NM16 o x volt a ge ca n be eff ectivel y reduced. Fi gure 2 i s t he t ra n si sto r N M16 i s give n by ci rc uit of t he co mp a rato r . Q C1Δ)( 2 V N M16 =Duri ng cali bratio n p erio d s , a ref e re nce volt a ge ( ) 1 C + WL N M16 CoxV i s app lied to bo t h i np ut s V IN a nd V IN R . Wit h2 ref B y p rop erl y bia si ng t he fi r st st a ge p re2a mp , o ut off set ,t he o utp ut of co mp a rato r sho ul d be 0 o r t ra n si sto r N M4 op e rat e s i n it s t rio de re gio n . Af t e r 1 of all rat e equalit y ; ho wever ,if off set occ ur s , t he cali bratio n , t he a b sol ut e re si st a nce va riatio n of o utp ut will be st a ble at 0 o r 1 . Whe n C K3 i s 1 ,t he N M4 ca n be w rit t e n a s C, a nd o utp ut si gnal c ha r ge s cap acito r t he n C K3 1 1 Δ = - |RNM4|beco me s 0 a nd C K4 i s 1 . The n t he c ha r ge sto red o n W ( Δ)μ CVGSNM4 +VNM16 - VTHNM4 n O XCi s redi st ri but ed bet wee n Ca nd N M16 , w ho se 1 1 NM4 L so urce a nd drai n a re co nnect ed to fo r m a cap acito r . 1 ( )3 Fo r si mp licit y , t he i nitial volt a ge s o n bo t h cap aci2 W ( ) μ V GSN M4 - V T HN M4 Cn O XN M4 L 2 redi st ri buto r s a re a ssumed to be 0 . Af t e r c ha r ge ( ) ( ) Eqs. 2a nd 3, by decrea si ng Acco r di ng to tio n ,we ha ve : Δ C1 o r i ncrea si ng W L of N M16 , bo t h V NM16 a ndQ = Q′ C1 C1+ Q N M16Δ | R| ca n be re duced ,t h u s i ncrea si ng t he acc ura2NM4 ( )1 Q′ C1Q N M16= cy of t he calibratio n , but at t he exp e n se of lo wer CC 1N M16 SA2ADC to realize a n eco no mically f ea si ble die [ 8 ] sizea s sho w n i n Fi g1 4 . ) ( ) ( In Fi g1 4 , DA1 Ra nd DA2 Ra re co nt rolled by bit s 1～4 a nd bit s 5～9 of t he SA2ADC , re sp ec2 ) ( ) ( tivel y ,w hile DA3 Ra nd DA4 Ra re co nt rolled by t he lo we r bit 10 a nd bit 11 . The cap acito r s a nd have t he great e st CC 12 wei ght s a nd a re t he mai n li miti ng f acto r s of t he re sol utio n of t he SA2ADC. Mi smat ch bet wee n t he m Fig1 3 Simulated wavefo r m of off set calibratio n will ca u se la r ge ha r mo nic di sto r tio n a nd t h u s de2 ( )gra de t he sp urio u s2f ree dyna mic ra nge S FD R of cali bratio n sp eed. A si mila r co ncl u sio n ca n be 1 [ 9 ] t he SA2ADC. Bit 1 i s t he M SB wei ght e d by draw n fo r N M17 a nd N M2 . The cali bratio n met ho d 2 do e s no t a dd a ny cap acito r s o n t he si gnal p at h ,a nd V . The wei ght of each of t he o t her bit s i s reduced FS [ 7 ] i s i mmune to p roce ss a nd t e mp erat ure va riatio n, succe ssivel y by a f acto r of 2 , e xcep t fo r bit 6 a nd t h u s i mp ro vi ng t he sp eed a nd accuracy greatl y . B y 1 bit 7 ,w ho se wei ght s a re bo t h V FS . Bit11 i s t he a ddi ng a 50 mV off set volt a ge to t he i np ut device s , 64 μt he mi smat ch ca n be cali brat ed wit hi n 100s. Fi g2 1 L SB , w hic h equal s FS , i n w hich V FS i s t he V 1024 ure 3 sho w s t he st atic re sult of t he cali bratio n a s f ull2scale i np ut volt a ge of t he SA2ADC. si mulat ed by H Spice . Whe n t here a re a ny mi smat c h a mo ng t he ca2 Whe n t he co mp a rato r wo r k s duri ng no r mal p acito r s ,t he volt a ge s of t he no de s V IN a nd V IN R co nver sio n cycle s , si mulatio n re sult s sho w t hat will no t be equal . In such a sit uatio n , t he cali bra2 w he n t he i np ut co mmo n mo de volt a ge i s 01 5V wit h tio n mo dule will cali brat e t he mi smat c h bet wee n C1 a 2 mV volt a ge swi ng , t he o utp ut volt a ge swi ng i s a nd Ct hro ugh t he cali bratio n cap acito r C) ,a nd( 2 cal R 103 mV af t e r a mp lificatio n , a nd t h u s t he to t al gai n t hi s a dj u st me nt will co nti n ue t hro ugh several cali2 i s a bo ut 52 . Whe n op erati ng at a cloc k f reque ncy of bratio n cycle s until t he net cha nge val ue at no de 10 M Hz ,t he mi ni mum si gnal det ect ed by t he lat ch ( ) V IN Rco me s to ze ro . A li nea r diff ere ntial at t e nu2 i s a bo ut 21 15 mV , divi ded by t he o ve rall gai n of ato r i s p ropo se d to co mp e n sat e fo r t he sli ght cap ac2 p re2a mp s , a nd t he co mp a rato r ca n get a re sol utio n ito r mi smat che s bet wee n t he a r bit ra r y o utp ut of ( ) of 14 bit wit h a 1Vpp i np ut diff ere ntial si gnal , DA1 a nd DA2 . w hich i s accurat e e no ugh fo r a 10 bit app licatio n . A s set fo r t h a bo ve ,t he volt a ge wei ght s of DA1 1 1 1 1 3 Ca pacitor self2cal ibrat ion ( ) ) ( R～ DA4 R a rea nd V FS , V FS , V FS16 64 32 64 V ,re sp ectivel y. The cap acito r s C, C, C, C, C FS 1 2 3 4 cal2 a nd caA co mbi natio n of a re si sto r net wo r k ha ve val ue sof 1 6 C , 1 6 C , C , C , a nd C , re sp ectivel y . p acito r a r ra y i s u sed to p erfo r m t he DA Cs i n t he Fig1 4 Circuit diagra m of DA C wit h capacito r calibratio n We have 4 1 i - 1 ( )D 2 V - A i n - A i n R i FSV I N - V I N R = × ? 16 1 5 C1 C2 i - 11 × D i + 4 2 V FS+ + ? C64 sum Cs um 1 1 C31 V V DD× FS+ 11 FS ×10 32 64 Csum CCcal4 ( - V ) × + V cal cal r C C s umsum4 5 1 i - 1 i - 1 St atic simulated result of capacito r mi smatch D 2D 2Fig1 5 V + i ×i + 4 ×FS = ?? 16 1 1 calibratio n 11 1 + V + D× V FS10FS D11 × V FS - 256 512 1024 volt a ge a dj u st me nt each ti me i s small , a nd t he ac2 16 11 2 c urat e a dj u st me nt of C a nd C t a ke s a lo ng ti me . ( )A i n - A i n R ( ) ×+× Vcal - Vcal r 23 23 Fi gure 5 i s t he st atic si mulat e d re sult of cap ac2 ( )4 ito r mi smat c he s cali bratio n wit h H Spice . w here D i s t he di git al o utp ut of bit i ; D, D, Di 7 8 9 2 3 4 rep re se nt 2,2,2,re sp ectivel y ,a nd C= C+ CSU M 1 2 4 Mea surement results + C+ C+ C= 23 C.3 4 cal () Whe n t he ADC wo r k s ,t he t e r m V - V × cal calr The SA2ADC ha s bee n f a bricat e d i n SM IC 1 μ 01 18m si ngle2pol y si x2met al CMO S a s a mo duleCmi smat c h bet wee n i s u se d to cali brat e t he 123 of t he So C syst e m Ga rfiel d4 Pl u s de si gne d by t he a nd C. 2 natio nal A S IC ce nt er , so ut hea st u nive r sit y . The Cwill be cha r ged o r The cap acito r s Ca nd8 7 c hip i s p acka ged i n PQ F P2176 L ea d. Fi gure 6 i s t he di scha r ged acco r di ng to t he re sult of t he volt a ge at la yo ut p at t er n ,a nd Fi gure 7 i s t he t e st boa r d of t he t he no de so a s to co nt rol t he po t e ntial at TA1 a nd p ropo sed SA2ADC. Whe n t he chip i s set to t he TA2 . A n a ve ra gi ng ci rc uit i s i ncl uded. Co unt e r _ 2 “Macro Te st ”mo de ,t he SA2ADC ca n be t e st e d sep2 M ( ) ha s a p erio d of 2 M = 4 i n t hi s ca se clock s. a rat el y . Co unt er _1 ,w hic h co unt s o nl y w he n t he co mp a rato r Fi gure s 8 ～ 10 a re t he mea sure d dyna mic a nd M - 1 o utp ut i s hi gh ,ha s a p e rio d of t he 2 cycle s. Bo t h st atic re sult s of t he p ropo sed SA2ADC , re sp ective2 of t he co u nt er s a ve ra ge t he nu mbe r s of hi gh s a nd l y. The SA2ADC i s drive n by a sa mp li ng clock of lo w s , sto re t he re sult i n a n SR Flip2Flop , a nd p a ss 11 8M Hz ge ne rat e d by PL L ,w hich i s al so i nt egrat2 it o n to C5 a nd C6 . The N M1～ N M4 co nt rolle d by e d o n t he c hip . The i np ut si gnal i s ge nerat e d f ro m a TA1 a nd TA2 wo r k i n t he deep t rio de re gio n j u st Hewlet t2Pac ka r d H P8648B f unctio n ge ne rato r , li ke volt a ge co nt rolle d re si sto r s , a nd t h u s t he gai n wit h a n a mp lit ude of - 1dB F S a nd a f reque ncy of ( ) of t he diff ere ntial a mp lifier A will be lo w . The V 320 k Hz. The o utp ut of SA2ADC i s buff e red by ( ) cali bratio n si gnal s V a nd V Ra re li nea r sum2 cal cal matio n s of t he po t e ntial s at TA1 a nd TA2 , dep e n2 di ng o n t he re si st a nce ratio s a mo ng N M1～N M4 : R N M16 ( )Vcal = D A 2 ×A V × 5 R R+ N M16N M17 R N M18 ( ) ( ) ( )6 Vcal R= D A 2 R×A V × RR+ N M18 MN19 Th u s t he mi smat ch bet wee n Ca nd Cca n be 1 2 cali brat ed by ge ne rati ng t he co nt rolled po t e ntial of ( ) t he cali bratio n cap acito r s Ca nd CR.cal cal If t he re a re no mi smat c h , t he fi nal volt a ge s of TA1 a nd TA2 a re a bo ut 11 3V . The volt a ge st ep - 5 bet wee n eac h cali bratio n p roce ss i s 7 ×10 V , Fig1 6 L ayo ut p at t er n of So C incl uding ADC Fig1 7 Te st boa r d of p ropo sed SA2ADC Fig1 10 Mea sured stati stic characteri stic : INL SN74AL V C H16244 ,a nd t he n go e s i nto a n A gile nt 16702B lo gic a nal yzer . The dat a cap t ured by t he lo gic a nal yzer i s sho w n i n Fi g1 11 . The mea sured ( )1 8/ DNL + 0diff e re ntial no nli nea rit y i s ( ) - 01 9L SB , a nd i nt e gral no nli nea rit y INL i s + 11 4/ - 11 1L SB. The 20482point fast Fo urier t rans2 ( ) form FF Tshows 551 9068dB signal2to2noise and dis2 ( ) tortio n SINAD,which correspo nds to a 91 003 effec2 ( ) tive number of bit s ENOB, 641 5767dB SFD R , a nd ( ) t he to t al ha r mo nic di sto r tio n T HD i s - 741 8889 dB . All mea sure me nt s a re p e rfo r med wit h a 11 8V supp l y at roo m t e mp e rat ure . Ta ble 1 summa2 rize s t he p erfo r ma nce of t he SA2ADC. Fig1 11 Dat a cap t ured by lo gic analyzer ( )A s a co mmo nl y u sed figure of merit FO M fo r ADCs co n si deri ng re sol utio n , ba ndwi dt h a nd SN R - 11 7 61 02 f 2samp [ 10 ,11 ] , co mp a redpo we r , we u se FO M = P di ss wit h AD S7843 f ro m T I a nd M C9328M X f ro m F R E ESCAL E. Thei r FO M a re 284L SB2Hz/ W a nd 560L SB2Hz/ W fo r t ypical val ue s , re sp ectivel y , w hile t he FO M of t hi s de si gn i s 660 L SB2Hz/ W fo r t ypical val ue s ,w hich sho w s a n i mp ro ve me nt of t he SA2ADC p e rfo r ma nce . Fig1 8 Mea sured dyna mic cha racteri stic s Table 1 Mea sured re sult s of t he ADC Pa ra met er Typical val ue Suppl y volt age 11 8 V Resol utio n 10 bit Po wer co nsu mp tio n 31 1 mW Sa mple rat e 3 M Hz ( )Inp ut ra nge diff 1 Vpp ( )DNL ma x 01 8L SB ( )INL ma x 11 4L SB SIN AD 551 9068dB T HD - 741 8889dB SFD R 641 5767dB 2( )A rea ref 01 25 mm Fig. 9 Mea sured stati stic characteri stic :DNL natio nal Editio ns ,2000 :470 Tan K S , Plano D. On boa r d self2cali bratio n of a nalo g2to2di g2 [ 3 ] 5 Concl usion it al a nd di git al2to2analo g co nvert er s. U nit ed St at e s Pat ent , Pat ent N u mber :4 ,399 ,426 ,1983 . 8 . 16 Li nea r a nalo g cali bratio n t ec h nique s to reduce [ 4 ] L eung K Y , Hol ber g D R , L eung K. Capacito r cali bratio n i n SA R co nvert er . U nit ed St at es Pat ent , Pat ent N umber :6 ,891 , t he co mp a rato r off set volt a ge a nd cap acito r mi s2 487 B2 ,2005 . 5 . 10 mat ch i n a n SA2ADC ha ve bee n p ropo se d i n t hi s Fayo mi C J B , Ro bert s G W. Lo w po wer/ lo w volt age high [ 5 ] p ap e r . The cali bratio n mo dule ca n wo r k i n p a rallel sp eed CMO S diff erential t rack a nd lat ch co mp a rato r wit h rail2 wit h t he SA2ADC co nve r sio n . It a voi d s t he requi re2 to2rail i np ut . ISCA S ,2000 me nt s of p reci se mat c hi ng a nd t ri mmi ng of co mpo2 Allen P E , Hol ber g D R. CMO S a nalo g ci rcuit de sign . Pub2 [ 6 ] li shi ng Ho u se of Elect ro nics Indust r y ,2002 :465 ne nt s a s no r mall y e xp ect ed wit h ADC signal co n2 [ 7 ] J a me s H , At herto n H , Tho ma s S. A n off set reductio n t ech2 ve r sio n . The ADC i s i mp le me nt ed i n a si gnal2pol y nique fo r use wit h CMO S i nt egrat ed co mp a rato r s a nd a mpli2 si x2met al CMO S p roce ss. Wit h t he cali bratio n ( ) fier s. I E EE J Solid2St at e Ci rcuit s ,1992 ,27 8:1168 mo dule , mea sure me nt re sult s sho w t hat t he ADC [ 8 ] Razavi B . Pri nciple s of dat a co nver sio n syst e m de sign . I E EE Pre ss ,1995 2 p erfo r mca n yiel d bo t h goo d st atic a nd dyna mic [ 9 ] L eger G , Peralia s E J , Rueda A . Imp act of ra ndo m cha nnel a nce . mi smat ch o n t he SN R a nd SFDR of ti me2i nt erleaved ADCs. ( ) I EE E Tra ns Ci rcuit s Syst ,2004 ,51 1:140 Ref erences [ 10 ] Wal den R H . A nalo g2to2digit al co nvert er sur vey a nd a nal ysi s. ( ) I EE E J Sele A rea s i n Co mmun ,1999 ,17 4: 539 [ 11 ] Do ndi S , Vecchi D ,Bo ni A . A 62bit 11 2 GHz i nt erleaved SA R [ 1 ] L e H P , Zayegh A , Si ngh J . Perfo r ma nce a nal ysi s of op ti2 a nd ADC i n 90 n m CMO S. Resea rch i n Microelect ro nics ( ) mized CMO S co mp a rato r . Elect ro n L et t ,2003 ,39 11:833 Elect ro nics , 2006 :301 Razavi B . De sign of a nalo g CMO S i nt egrat ed ci rcuit . Int er2 [ 2 ] 逐次逼近型模数转换器中的失配校准技术 †王龙善丽 吴建辉 沛 ( )东南大学国家专用集成电路系统工程技术研究中心 , 南京 210096 摘要 : 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 了一种用于逐次逼近型模数转换器中的比较器失调和电容失配自校准电路. 通过增加校准周期 ,该电 容自校准结构即可与原电路并行工作 ,实现高精度与低功耗. 校准精度可达 14bit . 采用该电路设计了一个用于逐 μ次逼近型结构的 10bit 3 M sp s 模 数 转 换 器 单 元 , 该 芯 片 在 SM IC 01 18m 11 8V 工 艺 上 实 现 , 总 的 芯 片 面 积 为 2 01 25 m m. 芯片实测 , 在采样频率为 11 8M Hz , 输入 320 k Hz 正弦波时 , 信号噪声失真比为 551 9068 dB , 无杂散动态 范围为 641 5767 dB , 总谐波失真为 - 741 8889dB , 功耗为 31 1 m W . 关键词 : 模数转换器 ; 逐次逼近 ; 自校准技术 EEACC : 2220 A ( ) 文章编号 : 025324177 20070921369206 中图分类号 : TN 432 文献标识码 : † 通信作者. E mail : yezi w o n g001 @163 . c o m 2007202202 收到 , 2007205212 定稿2007 中国电子学会 Your requestcould not be processed becauseof a configurationerror: "Could not connect to LDAPserver." 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