计算机组成与系统结构 习题答案,上海交大陈泽宇著（Computer composition and system structure, exercises, answers, Chen Zeyu, Shanghai Jiaotong University）

计算机组成与系统结构 习题答案,上海交大陈泽宇著（Computer composition and system structure, exercises, answers, Chen Zeyu, Shanghai Jiaotong University） 计算机组成与系统结构 习题答案,上海交大陈泽宇著(Computer composition and system structure, exercises, answers, Chen Zeyu, Shanghai Jiaotong University) C1: Which of the following devices do not belong to the five major components of the von Neumann architecture computer? Register, buffer The adapter is to ensure the sending _____ with features of the computer system in the required form or receive information. The correct answer is: I/O device On 1966, Flynn from the performance of parallel computer architecture of _____ according to different organization, the structure of the computer system is divided into SISD, SIMD, MISD and MIMD four. Instruction flow, data flow With the same _____ computer, we can use different _____. Computer architecture, computer composition Feng? Design of Neumann type computer is _____. The correct answer is to store programs and execute them in order of address The second generation of computers began to appear in 1958, the use of _____ as electronic devices. transistor In the hierarchical structure of the computer system, _____ using sign language. High language level, assembly language level The world's first general-purpose electronic digital computer using ENIAC _____ as electronic tube In the hierarchical structure of a computer system, which belongs to the hardware level is _____. Micro programming level, machine language level C2: In order to improve the precision of the floating point representation, when not _____ mantissa, by modifying the order code and move the decimal point, the mantissa domain MSB for _____, this is called a floating point representation specification. 0, 1 In China the use of computer operating platform Chinese characters, _____ character set is not included in traditional Chinese characters. GB2312 In _____ fixed-point operation, in order to determine whether the overflow occurs, a double symbol detection method. Whether or not the overflow, _____ always indicates the correct symbol symbol. Decimal, highest, integer, maximum In binary arithmetic unit, subtraction by _____ to achieve. Binary adder for complement operation In parity, only when the data contains 1 _____, parity bit =_____. Even numbers, 0, odd numbers, 1 Parity _____ cannot detect a mistake, more cannot recognize the error information _____. Even numbers, positions, even numbers, contents In PC, if using the extended ASCII code, Unicode UCS-2 and UCS-4 method to represent a character, the difference between the three is as follows: extended ASCII code with _____ bits, Unicode UCS-2 said in a _____, Unicode UCS-4 said in a _____. 8, 16, 32 In order to improve the precision of the floating point representation, when not _____ mantissa, by modifying the order code and move the decimal point, the mantissa domain MSB for _____, this is called a floating point representation specification. 0, 1 C3: Associative memory is to ______ to access memory. Key words, content The ______ composed by high-speed Cache. SRAM Cache memory in replacement, you can use the following replacement algorithm: ______. LFU algorithm, LRU algorithm, random replacement The function of Cache by ______, which is transparent to the programmer. Hardware MOS semiconductor memory, ______ peripheral circuit is simple, the speed ______, but the use of multiple devices, the integration degree is not high. SRAM, quick! EPROM refers to ______. Light erasable programmable read only memory The size of the virtual address space is actually ______ capacity limit. Auxiliary storage Associative memory is to ______ to access memory. Key words, content From the point of CPU, Cache increased, the performance of the ______ is the average reading time as much as possible the readout time close to Cache. Main memory Virtual address by ______ generation. Compiler MOS semiconductor memory, ______ can greatly improve the degree of integration, but due to ______ operation, the peripheral circuit complexity, slow speed. DRAM, refresh Virtual memory can be viewed as a ______ memory capacity is very large, with it, users do not need to consider whether the program put it down or put in question what position in the ______ in. Logical memory C4: The memory stack is set out by the programmer as a part of the stack using ______. Main memory Sequential addressing mode instruction, refers to the address of the next instruction given by ______. Program counter ______ field instruction format, operating characteristics and function of the operation code used to characterize the instruction In stack addressing, A is the accumulator, SP is the stack pointer, and MSP is the top cell of the SP instruction. If a push operation action sequence (A), MSP, -1, SP (SP), then the stack action sequence should be ______. (SP) +1 = SP, (MSP) A The structure is represented by the form of instruction format ______ binary code. Instruction word The jump instruction, refers to the address of the next instruction given by the direct instruction, therefore, ______ content must be changed, To keep track of the new instruction address. Program counter Instruction format address code in the field, usually used to specify its address or participate in the operation ______. Operand Register stack is ______ set in a group dedicated to the stack register. CPU An instruction operand address, can have a ______. : 0, 1, 2, 3 The function of program control is ______. Change the order in which the program is executed C5: In order to perform any given instructions must be tested to identify the operation instruction, the operation requested by the CPU, the ______ is completed this work. Instruction decoder In CPU, the program counter is used to preserve ______. The address of the next instruction In CPU, follow the instructions the subsequent address register is ______. Program counter _____ is the most basic unit of time processing operations. Clock cycle Broadly speaking, parallelism in time refers to two or more events occurred in ______. Same moment Pentium CPU with 2 instruction pipeline, can launch 2 simple integer instructions within 1 clock cycles, also can launch ______ floating-point instruction 1 The basic idea is: the micro program controller of micro operation control signal encoding, according to certain rules of the formation of ______, stored in a read-only memory; when the machine is running, and a read them, resulting in a variety of whole machine operation control signal required by the corresponding unit to perform prescribed operation. Micro instruction The central processor includes ______. ALU, controller, Cache Take out and implement the minimum time required for any one instruction for ______ CPU cycles. Two The key to SIMD in CPU is the simultaneous execution of multiple operations in 1 separate instructions to increase processor throughput. Which of the following techniques belong to SIMD technology? MMX, SSE, SSE2, SSE3 Synchronous control method of CPU is sometimes called ______. Fixed sequence control mode without response control mode In CPU, the instruction register is used to preserve ______. Current instruction When executed, CPU can automatically ______ the contents of the program counter, keep it will execute the next instruction memory address, ready for the next instruction. Increasing In CPU, the main function unit is ______. Arithmetic operations, logical tests, logical operations C6: Bus characteristics include ______. Physical characteristics, functional characteristics, electrical characteristics, time characteristics In the bus arbitration, arbitration ______ ______. Centralized central arbiter In order to solve the multiple main equipment at the same time ______ ______ bus priority, bus arbitration unit must have, in some way, choose one of the main equipment as a main bus. Competition, control The following circumstances, should adopt the asynchronous transmission mode is ______. The I/O interface exchanges information with the printer The bus is a standard bus, and the pursuit of ______ independent development standards. Technology, structure, CPU, manufacturers C7: In the high-speed DMA data transmission mode, data transmission is ______. Completed under the control of the control signal issued by the DMA controller itself The request form channel of CPU is _____ interrupt In order to facilitate the implementation of multilevel interrupt, the most effective way to preserve the scene information is used ______. stack The request form channel of CPU is ______. interrupt Using DMA transmission of data, each data transmission of a will occupy a ______ time. Storage cycle Input and output interface of a computer system is the interface between the ______. Host and peripheral C8: To achieve ______ level parallel array processor. instructions To achieve ______ level parallel multiprocessor. A task or process, job, or program From the perspective of parallel program execution, the highest level is ______ parallel. Job level, program level Multi classification, does not belong to a tightly coupled system is ______. MPP (massively parallel processor) The architecture of the array processor belongs to ______ computer. SIMD From the perspective of parallel program execution, the lowest level is ______ parallel. Instruction interior