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]用verilog编写的32位超前进位加法器代码
//超前进位加法器
`define word_size 32
`define word [`word_size-1:0]
`define n 4
`define slice [`n-1:0]
`define s0 (1*`n)-1:0*`n
`define s1 (2*`n)-1:1*`n
`define s2 (3*`n)-1:2*`n
`define s3 (4*`n)-1:3*`n
`define s4 (5*`n)-1:4*`n
`define s5 (6*`n)-1:5*`n
`define s6 (7*`n)-1:6*`n
`define s7 (8*`n)-1:7*`n
module c_adder (a,b,cin,s,cout); //顶层模块
input`word a,b;
input cin;
output`word s;
output cout;
wire[7:0] gg,gp,gc; //
wire[3:0] ggg,ggp,ggc; //
wire gggg,gggp; //
//first level
bitslice i0(a[`s0],b[`s0],gc[0],s[`s0],gp[0],gg[0]); bitslice i1(a[`s1],b[`s1],gc[1],s[`s1],gp[1],gg[1]); bitslice i2(a[`s2],b[`s2],gc[2],s[`s2],gp[2],gg[2]); bitslice i3(a[`s3],b[`s3],gc[3],s[`s3],gp[3],gg[3]); bitslice i4(a[`s4],b[`s4],gc[4],s[`s4],gp[4],gg[4]); bitslice i5(a[`s5],b[`s5],gc[5],s[`s5],gp[5],gg[5]); bitslice i6(a[`s6],b[`s6],gc[6],s[`s6],gp[6],gg[6]); bitslice i7(a[`s7],b[`s7],gc[7],s[`s7],gp[7],gg[7]); //second level
cla c0(gp[3:0],gg[3:0],ggc[0],gc[3:0],ggp[0],ggg[0]); cla c1(gp[7:4],gg[7:4],ggc[1],gc[7:4],ggp[1],ggg[1]); assign ggp[3:2]=2'b11;
assign ggg[3:2]=2'b00;
//third level
cla c2(ggp,ggg,cin,ggc,gggp,gggg);
assign cout=gggg|(gggp&cin);
endmodule
//求和并按输出a,b,cin分组
module bitslice(a,b,cin,s,gp,gg);
input`slice a,b; input cin;
output`slice s;
output gp,gg;
wire`slice p,g,c; pg i1(a,b,p,g);
cla i2(p,g,cin,c,gp,gg); sum i3(a,b,c,s); endmodule
//计算传播值和产生值的PG模块
module pg(a,b,p,g);
input`slice a,b;
output `slice p,g;
assign p=a|b;
assign g=a&b;
endmodule
//计算sum值的sum模块
module sum(a,b,c,s); input`slice a,b,c; output`slice s;
wire`slice t=a^b;
assign s=t^c;
endmodule
//n-bit 超前进位模块
module cla (p,g,cin,c,gp,gg);
input`slice p,g; //输出的propagate bit (传送值)和generate bit(生
成值)
input cin; //进位输入
output`slice c; //为每一位产生进位 output gp,gg; //传播值和进位制
function [99:0] do_cla; //该函数内将为每个位计算其进位值 input `slice p,g;
input cin;
begin: label
integer i;
reg gp,gg;
reg`slice c;
gp=p[0];
gg=g[0];
c[0]=cin;
for (i=1;i<`n;i=i+1)
begin
//C0=G0+P0C_1
//C1=G1+P1C0=(G1+P1G0)+P1P0C_1
gp=gp&p[i];
gg=(gg&p[i])|g[i];
c[i]=(c[i-1]&p[i-1])|g[i-1];
end
do_cla={c,gp,gg};
end
endfunction
assign {c,gp,gg}=do_cla(p,g,cin);
endmodule
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