布局参考：（具体尺寸根据实际情况而定）(可编辑)

布局参考：（具体尺寸根据实际情况而定）(可编辑) 布局参考:(具体尺寸根据实际情况而定) 5 4 3 2 1 REV DESCRIPTION DATE APPROVED NOTES,UNLESS OTHERWISE SPECIFIED: Initial schematic 10/7/04 Yao Yuan 0.1 1. RESISTANCE VALUES IN OHMS Ready for Layout 10/10/04 Yao Yuan 0.9 2. CAPACTITANCE VALUES IN FARADS. 3. ALL 0.1uF and 0.01uF CAPACITORS ARE Add EA15 Signal 11/10/04 Yao Yuan 1.1 D D DECOUPLING CAPS UNLESS OTHERWISE NOTED. Add VGA,LCD and USB2.0; Change 2/19/05 Yao Yuan THEY ARE SHOWN ON THE PAGE WITH THE ICs 1.9 SRAM number AND SHOULD BE PLACED NEAR. 4.BOARD PROPERTIES: AROUTE TO WITHIN 10% OF MANHATTAN DISTANCE B50 +/- 5 OHM MATCHED INPEDANCE COUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING DINNER LAYERS 1.0 OZ CU EFR4 BOARD MATERIAL 布局参考:(具体尺寸根据实际情况而定) FMIMIMUM TRACE WIDTH/SPACING 6 MILS C C GMINIMUM VIA SIZE 12/20 MILS RESET ALTERA_AS HLAYER STACKUP: POWER LT1085-3.3V ,LT1585-1.5V CLOCK 1TOP - SIGNAL ROUTING ALTERA_JTAG 2GROUND PLANE1 EXT PORT 33.3V POWER PLANE 4BOTTOM - SIGNAL ROUTING SDRAM CYCLONE FPGA USB CHIP EP1C6/EP1C12 PQ240 B PAGE 04 B EXT PORT 3232 SCHEMATIC INDEX: LEDs SWITCH EP1C1/4 AD/DA PORT 00 NOTESPS/2 LCD PORT 16Pin 01 CONNECTORS,UART,LED & OTHERS 02 CYCLONE CLOCK,PLL & RESET 03 CYCLONE CONFIG : 说明 04 CYCLONE IO 1. 采用四层板 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 ,SDRAM的信号处理要注意等长原则,FPGA的管脚定义可 以适当调整,但是SDCLK的位置不能动; 05 CYCLONE POWER 2. 蓝色边框的 单元 初级会计实务单元训练题天津单元检测卷六年级下册数学单元教学设计框架单元教学设计的基本步骤主题单元教学设计 为接插件,注意与周围器件的间距;右侧为扩展区域,不 能有高过8mm的器件; 06 SYSTEM POWER 07 SDRAM A A 08 SRAM Red Cyclone MainBoard Title 09 FLASH Size Document Number Rev 10 USB A4 2004001 B IF Date: Monday, March 07, 2005 Sheet11 of0 5 4 3 2 1 DB9 VGA SRAM FLASH USB2.0 USB1.15 4 3 2 1 3.3V CB10 D D RB6 NO POP U2 0.1uF 1 8 A0 VCC RB7 0 2 7 A1 WP SCL 3 6 A2 SCL SDA 4 5 VSS SDA 3.3V FBB1 24LC02 CB1 CB2 CB3 CB4 CB5 CB6 ECB1 + CB7 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF UB1 40 USB_INT0# JB1 PA0/INT0# 10 41 AVCC PA1/INT1# C 1 42 C USB_SLOE PA2/SLOE D- 2 43 PA3/WU2 D+ D+ 3 15 44 DPLUS PA4/FIFOADR0 D- 4 16 45 DMINUS PA5/FIFOADR1 5 46 USB_PKTEND# PA6/PKTEND 6 47 USB_FLAGD# PA7/FLAGD SYS_RST# 49 RESET# UD[15:0] USB2.0 UD[15:0] UD0 25 PB/FD0 UD1 26 PB/FD1 CB8 22pF UD2 27 PB/FD2 UD3 11 28 XTALO PB/FD3 UD4 12 29 XTALI PB/FD4 UD5 30 PB/FD5 UD6 RB1 YB1 31 PB/FD6 UD7 32 PB/FD7 NO POP 24.000MHz 5 CLKOUT CB9 22pF 20 B USB_IFCLK IFCLK B UD8 52 PD0/FD8 UD9 53 PD1/FD9 UD10 54 PD2/FD10 3.3V UD11 55 PD3/FD11 UD12 RB2 2.2K 56 PD4/FD12 SCL UD13 RB3 2.2K 22 1 SCL PD5/FD13 SDA UD14 23 2 SDA PD6/FD14 RB4 10K UD15 3 PD7/FD15 21 RESERVED RB5 10K 38 CTL2/FLAGC# USB_FLAGC# 51 37 WAKEUP# CTL1/FLAGB# USB_FLAGB# 36 CTL0/FLAGA# USB_FLAGA# 9 USB_SLWR# RDY1/SLWR# 8 USB_SLRD# RDY0/SLRD# CY7C68013-56PVC A A 10 USB2.0 IF Title Red Cyclone MainBoard Size Document Number Rev A B Date: Monday, March 07, 2005 Sheet11 of1 5 4 3 2 1 2 1 13 AGND 4 6 GND1 VCC1 7 14 GND2 VCC2 17 18 GND3 VCC3 19 24 GND4 VCC4 33 34 GND5 VCC5 35 39 GND6 VCC6 48 50 GND7 VCC75 4 3 2 1 5V EA[20:0] EA[20:0] ED[15:0] ED[15:0] 5V 5V JE3 JE1 2 1 ECLKIN_P ECLKIN_N JE2 4 3 ECLKIN_N 1 2 ECLKIN_P EA0 EA1 6 5 3 4 1 2 D ECLKOUT_P ECLKOUT_N D EA6 EA5 ED7 ED6 8 7 ECLKOUT_N 5 6 3 4 ECLKOUT_P EA4 EA3 ED5 ED4 10 9 7 8 5 6 EGPIO0 EA2 EA16 ED3 ED2 EGPIO1 12 11 9 10 7 8 EGPIO2 EGPIO3 ED1 ED0 14 13 11 12 9 10 EGPIO4 EGPIO5 EA15 EA14 16 15 13 14 11 12 EGPIO6 EGPIO7 EA13 EA12 ED15 ED14 18 17 15 16 13 14 EA17 EA18 ED13 ED12 20 19 17 18 15 16 EA19 EA7 ED11 ED10 EGPIO8 EGPIO9 22 21 19 20 17 18 ED9 ED8 EGPIO10 EGPIO11 24 23 21 22 19 20 EGPIO12 EGPIO13 26 25 FLASH_OE# SYS_RST# 23 24 21 22 UD7 UD6 EGPIO14 EGPIO15 28 27 FLASH_RW# FLASH_CE# 25 26 23 24 UD5 UD4 30 29 27 28 25 26 EA9 UD3 UD2 EA8 32 31 29 30 27 28 UD1 UD0 LEDG0 LEDG1 34 33 31 32 29 30 EA10 LEDG2 LEDG3 EA11 36 35 33 34 31 32 EA20 UD15 UD14 SW0 SW1 38 37 SRAM_CE# 35 36 33 34 UD13 UD12 PB0 PB1 40 39 SRAM_WE# SRAM_OE# 37 38 35 36 UD11 UD10 39 40 37 38 UD9 UD8 39 40 EXT_ADDR AD/DA_PORT C EXT_DATA C EGPIO[15:0] EGPIO[15:0] 3.3V 3.3V UD[15:0] 3.3V CU1 0.1uF U100 CU2 0.1uF RS232 PORT 【D】 RD1 RD2 RD3 RD4 1 16 C1+ VCC 1 11 4.7K 4.7K 4.7K 4.7K 3 2 6 C1- V+ SW[1:0] RU3 100 TX TX SW1 SWITCH 11 14 2 UART_TX T1I T1O SW[1:0] SW0 RX RX RX RX RX RX RX RX 12 13 7 1 3 UART_RX R1O R1I SW1 TX_EXT TX_EXT 10 7 3 2 4 UART_TX_EXT T2I T2O RX RX_EX _EXT T B 9 8 8 B UART_RX_EXT R2O R2I PB[1:0] PD1 4 6 4 C2+ V- PB[1:0] RU4 100 PB0 9 PD2 5 15 5 10 - GND C2 PB1 CU3 0.1uF SP3232ECA CU4 0.1uF PU1 LEDG[3:0] RD5 510 DD1 GREEN LEDG[3:0] 3.3V LEDG0 2 1 RU1 510 DU1 GREEN UART_TX J100 RD6 510 DD2 GREEN 2 1 LEDG1 UART_EXT 2 1 RU2 510 DU2 GREEN UART_RX RD7 510 DD3 GREEN 2 1 LEDG2 2 1 RD8 510 DD4 GREEN LEDG3 2 1 3.3V RPS1 270 JPS2 RPS3 0 1 PS2_DATA 2 A A 3 01 CONNETORS 5V 4 Red Cyclone MainBoard 5 Title PS2_CLK 6 RPS2 270 RPS4 NO POP PS/2 Size Document Number Rev A4 2004001 A 【PS】 Date: Monday, March 07, 2005 Sheet21 of0 5 4 3 2 1 3 2 15 4 3 2 1 U1C ECLKIN_P MCLKIN 28 153 ECLKIN_P CLK0LVDSCLK1p CLK2LVDSCLK2p ECLKIN_N CLK_USER 3.3V 29 152 ECLKIN_N CLK1LVDSCLK1n CLK3LVDSCLK2n RX1 33 ECLKOUT_P SDCLK 38 144 ECLKOUT_P PLL1_OUTpIO PLL2_OUTpIO SDCLK ECLKOUT_N RR4 39 143 ECLKOUT_N PLL1_OUTnIO PLL2_OUTnIO D D DR1 VCCA_PLL1 VCCA_PLL2 SW2 RR5 47K 27 154 VCCA_PLL1 VCCA_PLL2 SYS_RST# RESET 100 ECR1 + 10uF 30 151 RR4-47K; RR5-100; RR6-0 GNDA_PLL1 GNDA_PLL2 31 150 ECR1-10uF GNDD_PLL1 GNDD_PLL0 EP1C12Q240C8 【R】 放在显著位置 3.3V 3.3V X1 X2 MCLKIN CLK_USER 4 3 4 3 VCC OUT VCC OUT CX1 CX2 RX2 33 RX3 NO POP 2 1 2 1 GND NC GND NC C 0.1uF 0.1uF C 50.000MHz NO POP 【X】 PV1 RV1 270 CYCLONE PLLs 1 VGA_R 1.5V RV2 270 5V 9 PS2_CLK 2 VGA_G PS2_DATA FBL1 RV3 270 10 VCCA_PLL1 3 VGA_B R2 11 JL1 10K 4 12 1 ECL1+ CL1 CL2 CL3 5 2 ADJ B 13 3 B VGA_HS 1uF 2.2uF 0.1uF 0.01uF 6 4 LCD_RS 14 5 VGA_VS LCD_RW R3 7 6 LCD_E EGPIO0 512 15 7 EGPIO1 8 8 EGPIO2 9 EGPIO3 10 EGPIO4 1.5V VGA-15 11 EGPIO5 12 EGPIO6 FBL2 13 EGPIO7 VCCA_PLL2 14 JB2 15 RV4 270 1 16 EGPIO[15:0] RV5 270 2 - USB_D ECL2+ CL4 CL5 CL6 LCD_IF 3 USB_D+ 4 1uF 2.2uF 0.1uF 0.01uF 5 LCD接口电路需要确认 6 FPGA USB 【L】 A A 02 CYCLONE CLOCK,PLL&RESET Red Cyclone MainBoard 这些元件靠近芯片相应的管脚,靠近摆放,尽量没有过孔 Title Size Document Number Rev A4 2004001 A Date: Monday, March 07, 2005 Sheet31 of0 5 4 3 2 1 2 1 2 1 2 1 1 25 4 3 2 1 3.3V D D 3.3V RC1 RC2 RC3 10K 10K 10K RC4 RC5 RC6 U1B T1 10K 10K 10K 3.3V ALT_CF_nCONFD 145 CONF_DONE ALT_CF_nSTATUS U1E JC1 146 nSTATUS ALT_CF_nCONF 26 147 1 4 nCONFIG TCK TCK VCC ALT_CF_nCE TR TRST ST 33 32 149 3 6 nCE nCEO TDO TDO NC1 3.3V 148 5 8 TMS TMS NC3 UC1 7 2 NC2 GND1 FPGA_CF_DATA0 3 2 25 155 9 10 VCC1 DATA DATA0 TDI TDI GND2 ALT_CF_DCLK 7 6 36 VCC2 DCLK DCLK MSEL1 ALT_CF_nCS EP1C12Q240C8 ALTERA_JTAG 8 1 24 35 VCC3 nCS nCSOIO MSEL1 MSEL0 ALT_CF_ASD RC7 4 5 37 34 GND ASDI ASDOIO MSEL0 10K C EPCS4 EP1C12Q240C8 C RC8 Configuration 10K device is 3.3V configured use AS mode. The JTAG CC1 download mode is 0.1uF JTAG下载座靠近FPGA also available. JC2 1 2 DCLK GND1 3.3V 3 4 CONF_DONE VCC 5 6 nCONFIG nCE 7 8 DATAOUT nCS 9 10 ASDI GND2 ALTERA_AS B B 这些器件放在一起,距离FPGA不要太远 如果采用扩展板的CPLD来配置FPGA,RC9和RC10应换成4.7K电阻 A A 03 CYCLONE CONFIG Red Cyclone MainBoard Title Size Document Number Rev A4 2004001 B Date: Monday, March 07, 2005 Sheet41 of0 5 4 3 2 15 4 3 2 1 UART_TX UART_RX SDDQM[3:0] SDBA[1:0] SDDQM[3:0] SDBA[1:0] D D SDD[31:0] SDA[11:0] SDD[31:0] SDA[11:0] PS2_CLK U1D SDD0 180 IO180LVDS51p SDD1 1 179 PS2_DATA IO1LVDS23pINIT_DONE IO179LVDS51n SDD2 2 178 LCD_RS IO2LVDS23n IO178LVDS52p SDD3 3 177 LCD_RW IO3LVDS22p IO177LVDS52n SDD4 4 176 LCD_E IO4LVDS22n IO176VREF0B3 SDD5 5 175 USB_D+ IO5VREF0B1 IO175 SDD6 LEDG[3:0] 6 174 LEDG[3:0] USB_D- IO6 IO174LVDS53p LEDG0 SDD7 7 173 IO7LVDS21p IO173LVDS53n LEDG1 8 170 C C IO8LVDS21n IO170DPCLK4 SDCKE LEDG2 SDDQM1 11 169 IO11DPCLK1 IO169LVDS54p LEDG3 SDD8 SW[1:0] 12 168 SW[1:0] IO12LVDS20p IO168LVDS54n SW0 SDD9 13 167 IO13LVDS20n IO167LVDS55p PB[1:0] SW1 SDD10 14 166 PB[1:0] IO14LVDS19p IO166LVDS55n PB0 SDD11 15 165 IO15LVDS19n IO165LVDS56p PB1 SDD12 16 164 IO16LVDS18p IO164LVDS56n EGPIO0 SDD13 17 163 IO163LVDS57p IO17LVDS18n EGPIO1 SDD14 18 162 IO18LVDS17p IO162LVDS57n EGPIO[15:0] EGPIO2 SDD15 19 161 EGPIO[15:0] IO19LVDS17n IO161LVDS58p EGPIO3 20 160 VGA_R IO20LVDS16p IO160LVDS58n EGPIO4 21 159 IO21LVDS16n IO159LVDS59p VGA_G EGPIO5 23 158 VGA_B IO23VREF1B1 GCLK0/1 GCLK2/3 IO158LVDS59n EGPIO6 41 156 IO41LVDS7n IO156 VGA_HS EGPIO7 42 141 VGA_VS IO42LVDS6p IO141LVDS68p EGPIO8 EA0 43 140 IO43LVDS6n PLL0 PLL1 IO140LVDS68n EGPIO9 44 139 FLASH_OE# IO44LVDS5p IO139LVDS69p EGPIO10 45 138 IO45LVDS5n IO138LVDS69n FLASH_CE# EGPIO11 46 137 USB_PKTEND# FLASH_RW# IO46LVDS4p IO137LVDS70p EGPIO12 47 136 USB_INT0# IO47LVDS4n IO136LVDS70n FLASH_RY_BY# EGPIO13 EA1 48 135 USB_FLAGD# IO48LVDS3p IO135LVDS71p EGPIO14 EA19 49 134 USB_SLOE IO49LVDS3n IO134LVDS71n EGPIO15 EA18 50 133 USB_IFCLK IO50DPCLK0 IO133LVDS72p EA17 RXB5 NO POP 53 132 USB_FLAGC# IO53LVDS2p IO132LVDS72n RXB1 NO POP SYS_RST# B 54 131 SYS_RST#的位置不能调整 B USB_FLAGB# IO131DPCLK5 SYS_RST# IO54LVDS2n EA2 RXB2 NO POP 55 128 USB_FLAGA# IO55VREF2B1 IO128 RXB3 NO POP EA3 56 127 USB_SLWR# IO56 IO127VREF2B3 EA4 RXB4 NO POP 57 126 USB_SLRD# IO57LVDS1p IO126LVDS73p EA5 UD0 58 125 IO58LVDS1n IO125LVDS73n UD1 EA6 59 124 IO59LVDS0p IO124LVDS74p UD2 60 123 IO60LVDS0n IO123LVDS74n SRAM_CE# ED0 122 IO122LVDS75p ED1 121 IO121LVDS75n EP1C12Q240C8 ED[15:0] ED[15:0] UD[15:0] UD[15:0] A A SRAM_OE# 04 CYCLONE FPGA IOs SRAM_BE[1:0] Red Cyclone MainBoard SRAM_BE[1:0] Title EA[20:0] EA[20:0] Size Document Number Rev B 2004001 A Monday, March 07, 2005 51 of0 Date: Sheet 5 4 3 2 1 UD3 61 240 IO61LVDS102p IO240LVDS24p UD4 62 239 IO62LVDS102n IO239LVDS24n UART_RX_EXT UD5 63 238 IO63LVDS101p IO238LVDS25p UART_TX_EXT UD6 64 237 IO64LVDS101n IO237LVDS25n UD7 65 236 IO65LVDS100p IO236LVDS26p UD8 SDD24 66 235 IO66LVDS100n IO235LVDS26n UD9 SDD25 67 234 IO67LVDS99p IO234LVDS27p UD10 SDD26 68 233 IO68LVDS99n IO233LVDS27n UD11 SDD27 73 228 IO73DPCLK7 IO228DPCLK2 UD12 SDD28 74 227 IO74VREF2B4 IO227VREF2B2 UD13 SDD29 75 226 IO75LVDS98p IO226LVDS28p UD14 SDD30 76 225 IO76LVDS98n IO225LVDS28n UD15 SDD31 77 224 IO77LVDS97p IO224LVDS29p ED8 SDDQM3 78 223 IO78LVDS97n IO223LVDS29n ED9 SDA3 79 222 IO79LVDS96p IO222LVDS30p ED10 SDA4 82 219 IO82LVDS95p IO219LVDS31p ED11 SDA5 83 218 IO83LVDS95n IO218LVDS31n ED12 SDA6 84 217 IO84LVDS94p IO217LVDS32p ED13 SDA7 85 216 IO85LVDS94n IO216LVDS32n SDA8 ED14 86 215 IO86LVDS93p IO215LVDS33p ED15 SDA9 87 214 IO87LVDS93n IO214LVDS33n EA11 SDD23 88 213 IO88LVDS92p IO213LVDS34p EA10 SDD22 93 208 IO93VREF1B4 IO208VREF1B2 EA9 SDD21 94 207 IO94LVDS87p IO207LVDS39p EA8 SDD20 95 206 IO95LVDS87n IO206LVDS39n EA7 SDD19 98 203 IO98LVDS86p IO203LVDS40p 18 SDD 99 202 SRAM_WE# IO99LVDS86n IO202LVDS40n ED7 SDD17 100 201 IO100LVDS85p IO201LVDS41p ED6 SDD16 101 200 IO101LVDS85n IO200LVDS41n ED5 SDDQM2 104 197 IO104LVDS80p IO197LVDS46p ED4 SDA2 105 196 IO105LVDS80n IO196LVDS46n EA12 SDA1 106 195 IO106 IO195 EA13 SDA0 107 194 IO107VREF0B4 IO194VREF0B2 EA14 SDA10 108 193 IO108DPCLK6 IO193DPCLK3 EA16 SDBA1 113 188 IO113LVDS79p IO188LVDS47p EA15 SDBA0 114 187 IO114LVDS79n IO187LVDS47n EA20 SDA11 115 186 IO115LVDS78p IO186LVDS48p SRAM_BE0 116 185 SDCS# IO116LVDS78n IO185LVDS48n SRAM_BE1 117 184 SDRAS# IO117LVDS77p IO184LVDS49p 118 183 SDCAS# IO118LVDS77n IO183LVDS49n ED3 119 182 SDWE# IO119LVDS76p IO182LVDS50p SDDQM0 ED2 120 181 IO120LVDS76n IO181LVDS50n5 4 3 2 1 3.3V EP1C12与EP1C6的管脚区别: U1A 9 10 VCCIO9 GND10 D D 22 40 VCCIO22 GND40 EP1C12EP1C6 51 52 VCCIO51 GND52 70 69 VCCIO70 GND69 VCCINT81IO 92 71 VCCIO92 GND71 112 80 VCCIO112 GND80 VCCINT97IO 130 89 VCCIO130 GND89 157 91 VCCIO157 GND91 VCCINT103 IO 172 96 VCCIO172 GND96 189 102 VCCIO189 GND102 VCCINT198 IO 209 109 VCCIO209 GND109 231 111 VCCINT204 IO VCCIO231 GND111 1.5V 129 GND129 142 GND142 VCCINT220 IO 72 171 VCCINT72 GND171 81 190 VCCINT81 GND190 90 192 VCCINT90 GND192 97 199 VCCINT97 GND199 103 205 VCCINT103 GND205 GND80 IO 110 210 VCCINT110 GND210 191 212 VCCINT191 GND212 GND96 IO C C 198 221 VCCINT198 GND221 204 230 VCCINT204 GND230 GND102IO 211 232 VCCINT211 GND232 220 VCCINT220 GND199IO 229 VCCINT229 GND205IO EP1C12Q240C8 GND221IO 3.3V 1.5V 如果采用EP1C6芯片,以上管脚应该全部置为输入。 EC1 + + EC2 EC3 + + EC4 10uF 10uF 10uF 10uF B B 3.3V C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 1.5V C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF A A 05 CYCLONE FPGA POWER Red Cyclone MainBoard Title Size Document Number Rev A4 2004001 A Date: Monday, March 07, 2005 Sheet61 of0 5 4 3 2 1 2 1 2 1 2 1 2 15 4 3 2 1 D D 5V UP1 LM1085 3.3V JP1 FBP1 1 3 2 IN OUT 3 2 RP1 + ECP1 ECP2+ CP1 ECP3+ CP2 POWER RP2 510 47uF 47uF 0.1uF 47uF 0.1uF NO POP C DP1 C RED RP3 0 UP2 LM1085 1.5V FBP2 3 2 IN OUT ECP4+ CP3 ECP5+ CP4 RP4 47uF 0.1uF 47uF 0.1uF B B NO POP RP5 0 【P】 A A 06 SYSTEM POWER Title Red Cyclone MainBoard Size Document Number Rev A4 2004001 A Date: Monday, March 07, 2005 Sheet71 of0 5 4 3 2 1 2 1 2 1 2 1 1 1 GND GND 2 1 2 15 4 3 2 1 3.3V SDD[31:0] D D UM1 SDBA[1:0] SDD31 SDBA1 56 23 DQ31 BA1 SDD30 SDBA0 54 22 DQ30 BA0 SDA[11:0] SDD29 53 DQ29 SDD28 SDA10 51 24 DQ28 AP A10 SDD27 SDA9 50 66 DQ27 A09 SDD26 SDA8 48 65 DQ26 A08 SDD25 SDA7 47 64 DQ25 A07 SDD24 SDA6 45 63 DQ24 A06 SDD23 SDA5 42 62 DQ23 A05 SDD22 SDA4 40 61 DQ22 A04 SDD21 SDA3 39 60 DQ21 A03 SDD20 SDA2 37 27 DQ20 A02 SDD19 SDA1 36 26 DQ19 A01 SDD18 HY57V283220T SDA0 34 25 DQ18 A00 SDD17 33 DQ17 SDD16 SDDQM3 31 59 DQ16 DQM3 SDD15 SDDQM2 85 28 DQ15 DQM2 3.3V C SDD14 SDDQM1 C 83 71 DQ14 DQM1 SDD13 SDDQM0 82 16 DQ13 DQM0 SDDQM[3:0] SDD12 80 DQ12 SDD11 79 DQ11 SDD10 77 14 DQ10 NC SDD9 76 73 DQ09 NC SDD8 RM1 RM2 RM3 RM4 74 30 DQ08 NC SDD7 13 57 DQ07 NC SDD6 11 70 DQ06 NC SDD5 10 69 DQ05 NC SDA11 SDD4 4.7K 4.7K 4.7K 4.7K 8 21 DQ04 NC SDD3 7 DQ03 SDD2 CLK 5 68 SDCLK DQ02 CLK SDD1 CKE CKE 4 67 SDCKE DQ01 CKE SDD0 CS# 2 20 SDCS# DQ00 /CS RAS# RAS# 19 SDRAS# /RAS CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# CAS# 18 SDCAS# /CAS WE# WE# 17 /WE SDWE# B B SDA11 的目的是为了扩展到128Mbit (4M×32Bit )应用的 ,如 HY57V283220T 等。 3.3V 【M】 CM1 CM2 CM3 CM4 CM5 CM6 CM7 CM8 CM9 CM10 CM11 CM12 A A 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 07 SDRAM Red Cyclone MainBoard Title Size Document Number Rev A4 2004001 A Date: Monday, March 07, 2005 Sheet81 of0 5 4 3 2 1 86 1 VSS VDD 72 15 VSS VDD 58 29 VSS VDD 44 43 VSS VDD 84 3 VSSQ VDDQ 6 81 VSSQ VDDQ 12 9 VSSQ VDDQ 32 75 VSSQ VDDQ 52 55 VSSQ VDDQ 38 35 VSSQ VDDQ 46 49 VSSQ VDDQ 78 41 VSSQ VDDQ5 4 3 2 1 D D 3.3V UM2 EA[20:0] ED[15:0] EA1 ED0 1 7 A0 IO0 EA2 ED1 2 8 A1 IO1 EA3 ED2 3 9 A2 IO2 EA4 ED34 10 A3 IO3 EA5 ED4 5 13 A4 IO4 EA6 ED5 18 14 A5 IO5 EA7 ED6 19 15 A6 IO6 C EA8 ED7 C 20 16 A7 IO7 EA9 ED8 21 29 A8 IO8 3.3V EA10 ED9 22 30 A9 IO9 EA11 ED10 23 31 A10 IO10 EA12 ED11 24 32 A11 IO11 EA13 ED12 25 35 A12 IO12 EA14 ED13 26 36 A13 IO13 RM5 RM6 RM7 EA15 ED14 27 37 A14 IO14 EA16 ED15 42 38 A15 IO15 EA17 43 A16 EA18 44 A17 4.7K 4.7K 4.7K SRAM_BE[1:0] SRAM_CE# SRAM_BE1 6 40 SRAM_CE# CE# UB# SRAM_WE# SRAM_BE0 17 39 SRAM_WE# WE# LB# SRAM_OE# 41 28 SRAM_OE# OE# NC ISSI25616 B B 3.3V CM13 CM14 CM15 0.01uF 0.1uF 0.1uF 【M】 A A 08 SRAM Red Cyclone MainBoard Title Size Document Number Rev A4 2004001 A Date: Monday, March 07, 2005 Sheet91 of0 5 4 3 2 1 12 11 GND VCC 34 33 GND VCC