数字秒
表
关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf
实验报告
---之数字秒表
通信工程
2009年12月
一:功能介绍
(1)精度应大于1/100s
(2 计时器的最长计时时间为1小时,在一般的短时间计时应用中,1小时应该足够了。为此需要一个6位显示器,显示最长时间为59分59.99秒。
(3 设置复位和启/停开关
复位开关用来使计时器清0,并作好清0准备。启/停开关的使用方法与传统的机械计时器相同,即按一下启/停开关,启动计时器开始计时,再按一下启/停开关计时终止。复位开关可以在任何情况下使用,即使在计时过程中,只要按一下复位开关,计时进程应立即终止,并对计时器清零。
二:设计
方案
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根据方案所有的功能~将整个工程分成五个模块~模块一为分频模块~将50MHZ分成100HZ和1000HZ分别计数时钟和势能时钟。模块二为计数模块~它由四个十进制和两个六进制组成。模块三为功能控制模块。模块四位为势能控制模块。模块五为显示输出模块。
三:系统框图
四:模块说明
1. 分频模块
该模块主要将输入的50MHZ的输入时钟信号clk_in分成100HZ计
数时钟信号clk_c和1000HZ势能时钟信号clk_c1。模块如下:
该模块的代码为:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt100 is
port(clk_in:IN STD_LOGIC;
clk_c: OUT STD_LOGIC;
clk_c1: OUT STD_LOGIC
);
end cnt100;
architecture rtl OF cnt100 IS
SIGNAL count: STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL clk1 : STD_LOGIC;
SIGNAL clk2 : STD_LOGIC;
SIGNAL clk3 : STD_LOGIC;
SIGNAL count1: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL count2: STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
c1:process(clk_in)
begin
if(clk_in'event and clk_in='1') then
if(count="110001") then
count<="000000";
clk1<='1';
else
clk1<='0';
count<=count+1;
end if;
end if;
clk_c1<=clk1;
end process c1;
c2:process(clk1)
begin
if(clk1'event and clk1='1') then
if(count1="1111100111") then
count1<="0000000000";
clk2<='1';
else
clk2<='0';
count1<=count1+1;
end if;
end if;
end process c2;
c3:process(clk2)
begin
if(clk2'event and clk2='1') then
if(count2="1001") then
count2<="0000";
clk3<='1';
else
clk3<='0';
count2<=count2+1;
end if;
end if;
clk_c<=clk3;
end process c3;
END rtl;
2. 计数模块
计数模块由四个十进制与两个六进制组成,模块如下:
该模块的代码为:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt10 IS
PORT (reset,en,clk:IN STD_LOGIC;
ca:OUT STD_LOGIC;
q :BUFFER STD_LOGIC_VECTOR(3 downto 0)
);
END cnt10;
ARCHITECTURE rtl OF cnt10 Is BEGIN
PROCESS(clk,reset,en)
BEGIN
iF(reset='1')THEN
q<="0000";
ELSIF(en='1') THEN
IF(clk'EVENT AND clk='1')THEN
IF(q="1001") THEN
q<= "0000";
ca<='1';
ELSIF(q="1000") THEN
q<= q+1;
ca<='0';
ELSE
q<=q+1;
ca<='1';
END IF;
END IF;
END IF;
END PROCESS;
END rtl;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt6 IS
PORT (reset,clk:IN STD_LOGIC;
ca:OUT STD_LOGIC;
q :BUFFER STD_LOGIC_VECTOR(3 downto 0)
);
END cnt6;
ARCHITECTURE rtl OF cnt6 Is BEGIN
PROCESS(clk,reset)
BEGIN
iF(reset='1')THEN
q<="0000";
ELSe
IF(clk'EVENT AND clk='1')THEN
IF(q="0101") THEN
q<= "0000";
ca<='1';
ELSIF(q="0100") THEN
q<= q+1;
ca<='0';
ELSE
q<=q+1;
ca<='1';
END IF;
END IF;
END IF;
END PROCESS;
END rtl;
3. 功能控制模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity xianshi is
port(a,b,c,d,e,f:in std_logic_vector(3 downto 0);
sel:in std_logic_vector(2 downto 0);
y:out std_logic_vector(3 downto 0)
);
end xianshi;
architecture one of xianshi is begin
process(sel)
begin
if(sel="000")then y<=a;
elsif(sel="001")then y<=b; elsif(sel="010")then y<=c;
elsif(sel="011")then y<=d; elsif(sel="100")then y<=e; elsif(sel="101")then y<=f; end if;
end process ;
end one;
4.势能控制模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sel is
port(clk:in std_logic;
q:out std_logic_vector(2 downto 0)); end sel;
architecture sel_arc of sel is begin
process(clk)
variable cnt:std_logic_vector(2 downto 0); begin
if clk'event and clk='1'then cnt:=cnt+1;
end if;
q<=cnt;
end process;
end sel_arc;
5.显示模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity yima1 is
port(
sel:in std_logic_vector(2 downto 0);
y1:out std_logic_vector(7 downto 0)
);
end yima1;
architecture one of yima1 is begin
process(sel)
begin
if(sel="000")then y1<="11111110"; elsif(sel="001")then y1<="11111101"; elsif(sel="010")then y1<="11111011"; elsif(sel="011")then y1<="11110111"; elsif(sel="100")then y1<="11101111";
elsif(sel="101")then y1<="11011111"; end if;
end process;
end one;
library ieee;
use ieee.std_logic_1164.all;
entity yima is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0)); end yima;
architecture abc of yima is
begin
process(d)
begin
case d is
when "0000"=>q<="1111110"; when "0001"=>q<="0110000"; when "0010"=>q<="1101101"; when "0011"=>q<="1111001"; when "0100"=>q<="0110011"; when "0101"=>q<="1011011"; when "0110"=>q<="1011111";
when "0111"=>q<="1110000"; when "1000"=>q<="1111111"; when "1001"=>q<="1111011"; when others=>q<="0000000"; end case;
end process;
end abc;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity yima1 is
port(
sel:in std_logic_vector(2 downto 0);
y1:out std_logic_vector(7 downto 0)
);
end yima1;
architecture one of yima1 is begin
process(sel)
begin
if(sel="000")then y1<="11111110"; elsif(sel="001")then y1<="11111101";
elsif(sel="010")then y1<="11111011";
elsif(sel="011")then y1<="11110111";
elsif(sel="100")then y1<="11101111";
elsif(sel="101")then y1<="11011111";
end if;
end process;
end one;
6.顶层模块部分为: