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[op07中文资料]KST5550中文资料_0[op07中文资料]KST5550中文资料_0 [op07中文资料]KST5550中文资料 篇一 : KST5550中文资料 元器件交易网 KST5550 KST5550 High Voltage Transistor 3 2 1 SOT-23 1. Base 2. Emitter 3. Collector NPN Epitaxial Silicon Transistor Absolute Maximum Ratings Ta=25?C unless otherwise noted Sy...

[op07中文资料]KST5550中文资料_0
[op07中文资料]KST5550中文资料_0 [op07中文资料]KST5550中文资料 篇一 : KST5550中文资料 元器件交易网 KST5550 KST5550 High Voltage Transistor 3 2 1 SOT-23 1. Base 2. Emitter 3. Collector NPN Epitaxial Silicon Transistor Absolute Maximum Ratings Ta=25?C unless otherwise noted SymbolVCBOVCEOVEBOICPCTSTG Collector-Base VoltageCollector-Emitter VoltageEmitter-Base VoltageCollector Current Collector Power DissipationStorage Temperature Parameter Value1601406600350150 UnitsVVVmAmW?C Electrical Characteristics Ta=25?C unless otherwise noted SymbolBVCBOBVCEOBVEBOICBOIEBOhFE Parameter Collector-Base Breakdown VoltageCollector-Emitter Breakdown VoltageEmitter-Base Breakdown VoltageCollector Cut-off CurrentEmitter Cut-off CurrentDC Current Gain Test Condition IC=10μA, IE=0IC=1mA, IB=0IE=10μA, IC=0VEB=4V, IC=0VCE=5V, IC=1.0mAVCE=5V, IC=10mA VCE=5V, IC=50mA IC=10mA, IB=1mAIC=50mA, IB=5mAIC=10mA, IB=1mAIC=50mA, IB=5mA IC=10mA, VCE=10Vf=100MHz VCB=10V, IE=0, f=1.0MHz Marking 100606020Min.1601406 502500.150.251.01.23006.0 VVVVMHzpF Max. UnitsVVVnAnA VCB=100V, IEVCE VBE fTCob Collector-Emitter Saturation VoltageBase-Emitter Saturation VoltageCurrent Gain Bandwidth ProductOutput Capacitance 1F ?2002 Fairchild Semiconductor CorporationRev. A2, November 2002 元器件交易网 KST5550 ?2002 Fairchild Semiconductor Corporation Rev. A2, November 2002 元器件交易网 KST5550 ?2001 Fairchild Semiconductor Corporation Rev. A2, November 2002 元器件交易网 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is notintended to be an exhaustive list of all such trademarks. ACEx?FACT?ActiveArray?FACT Quiet series?Bottomless?FAST? FASTr?CoolFET? CROSSVOLT?FRFET? GlobalOptoisolator?DOME? EcoSPARK?GTO?2CMOS?EHiSeC?EnSigna?I2C? Across the board. Around the world.?The Power Franchise? Programmable Active Droop?DISCLAIMER ImpliedDisconnect?ISOPLANAR?LittleFET?MicroFET?MicroPak?MICROWIRE?MSX?MSXPro?OCX?OCXPro?OPTOLOGIC?OPTOPLANAR?PACMAN?POP? Power247?PowerTrench?QFET?QS? QT Optoelectronics?Quiet Series?RapidConfigure?RapidConnect? SILENT SWITCHER?SMART START? SPM?Stealth? SuperSOT?-3SuperSOT?-6SuperSOT?-8SyncFET?TinyLogic? TruTranslation?UHC?UltraFET?VCX? FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANYPRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANYLIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTORCORPORATION.As used herein: 1. Life support devices or systems are devices or systemswhich, are intended for surgical implant into the body,or support or sustain life, or whose failure to performwhen properly used in accordance with instructions for useprovided in the labeling, can be reasonably expected toresult in significant injury to the user. 2. A critical component is any component of a life supportdevice or system whose failure to perform can bereasonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONSDefinition of Terms Datasheet IdentificationAdvance Information Product StatusFormative or In DesignFirst Production Definition This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign. This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only. Preliminary No Identification NeededFull Production ObsoleteNot In Production 扩展:ks8028焊线机资料 / 韩国 ksnet中文 / ks8028pps编程资料 ?2002 Fairchild Semiconductor CorporationRev. I1 扩展:ks8028焊线机资料 / 韩国ksnet中文 / ks8028pps编程 资料 篇二 : CA4211-000中文资料 元器件交易网 扩展:74hc000 中文资料 / 7550 1中文资料 / mv3581中文资 料 篇三 : CA3310中文资料 元器件交易网 CA3310, CA3310A August 1997 CMOS, 10-Bit, A/D Converterswith Internal Track and Hold CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143 | Copyright ? Intersil Corporation 1999 File Number 3095.1 6-6 元器件交易网 CA3310, CA3310A 6-7 元器件交易网 CA3310, CA3310A 6-8 元器件交易网 CA3310, CA3310A 6-9 元器件交易网 CA3310, CA3310A 6-10 元器件交易网 CA3310, CA3310A 6-11 元器件交易网 CA3310, CA3310A 6-12 元器件交易网 CA3310, CA3310A 6-13 元器件交易网 CA3310, CA3310A 6-14 元器件交易网 CA3310, CA3310A 6-15 元器件交易网 CA3310, CA3310A 6-16 元器件交易网 CA3310, CA3310A 6-17 元器件交易网 CA3310, CA3310A Other Accuracy Effects Linearity, offset, and gain errors are dependent on themagnitude of the full-scale input range, VREF+ - VREF-.Figure 11 shows how these errors vary with full-scale range.The clocking speed is a second factor that affects conversionaccuracy. Figure 12 shows the typical variation of linearity,offset, and gain errors versus clocking speed. Gain and offset drift due to temperature are kept very low bymeans of auto-balancing the comparator. The speci?cationsshow typical offset and gain dependency on temperature.There is also very little linearity change with temperature, onlythat caused by the slight slowing of CMOS with increasingtemperature. At 85oC, for instance, the lLE and DLE would betypically those for a 20% faster clock than at 25oC.Power Supplies and Grounding VDD and VSS are the digital supply pins: theyoperate all internal logic and the output drivers. Because theoutput drivers can cause fast current spikes in the VDD andVSS lines, VSS should have a low impedance path to digitalground and VDD should be well bypassed. Except for VDD+, which is a substrate connection to VDD, allpins have protection diodes connected to VDD and VSS:input transients above VDD or below VSS will get steered tothe digital supplies. Current on these pins must be limited byexternal means to the values speci?ed under maximumratings. The VAA+ and VAA- terminals supply the charge-balancingcomparator only. Because the comparator is autobalancedbetween conversions, it has good low frequency supplyrejection. It does not reject well at high frequencies, how-ever: VAA- should be returned to a clean analog ground, andVAA+ should be RC decoupled from the digital supply.There is approximately 50? of substrate impedancebetween VDD and VAA+. This can be used, for example, aspart of a low-pass RC ?lter to attenuate switching supplynoise. A 10pF capacitor from VAA+ to ground wouldattenuate 30kHz noise by approximately 40dB. Note thatback-to-back diodes should be placed from VDD to VAA+ tohandle supply to capacitor turn-on or turn-off currentspikes. Figure 16 shows VAA+ supply rejection versus frequency.Note that the frequency to be rejected scales with the clock:the 100Hz rejection with a 100kHz clock would be roughlyequivalent to the 1kHz rejection with a 1MHz clock. 扩展:ca3140中文资料 / smbj5.0ca中文资料 / smbj15ca中文资料 The supply current for the CA3310 is dependent on clockfrequency, supply voltage, and temperature. Figure 14shows the typical current versus frequency and voltage,while Figure 15 shows it versus temperature and voltage.Note that if stopped in auto-balance, the supply current istypicallysomewhat higher than if free-running. SeeSpeci?cations. Application Circuits Differential Input A/D System As the CA3310 accepts a unipolar positive-analog input, theaccommodation of other ranges requires additional circuitry.The input capacitance and the input energy also force usinga low-impedance source for all but slow speed use. Figure20 shows the CA3310 with a reference, input ampli?er, andinput-scaling resistors for several input ranges. The ICL7663S regulator was chosen as the reference, as itcan deliver less than 0.25V input-to-output voltageand uses very little power. As high a reference as possible isgenerally desirable, resulting in the best linearity andrejection of noise at the CA3310. The tantalum capacitor sources the VREF current spikesduring a conversion cycle. This relieves the response andpeak current requirements of the reference. The CA3140 operational ampli?er provides good slewingcapability for high bandwidth input signals and can quicklysettle the energy that the CA3310 outputs at its VlN terminal.It can also drive close to the negative supply rail. If system supply sequencing or an unknown input voltage islikely to cause the operational ampli?er to drive above theVDDsupply, a diode clamp can be added from pin 8 of theoperational ampli?er to the VDD supply. The minus drivecurrent is low enough not to require protection. With a 2MHz clock , Nyquist criteria wouldgive a maximum input bandwidth of 75kHz. The resistor valueschosen are low enough to not seriously degrade system band-width at that clock frequency.If A/D clock frequency and bandwidth requirements are lower,the resistor values can be madecorrespondingly higher. The A/D system would generally be calibrated by tying VlN- toground and applying a voltage to VIN+ that is 0.5 LSB above ground. The operational ampli?eroffset should be adjusted for an output code dithering between00016 and 00116 for unipolar use, or 10016 and 10116 for bipo-lar use. The gain would then be adjusted by applying a voltagethat is 1.5 LSB below the positive full scaleinput, and adjustingthe reference for an output dithering between 3FE16 and3FF16. Note that R1 through R5 should be very well matched, asthey affect the common-mode rejection of the A/D system.Also, if R2 and R3 are not matched, the offset adjust of theoperational ampli?er may not have enough adjustment rangein bipolar systems. The common-mode input range of the system is set by thesupply voltage available to the operational ampli?er. Therange that can be applied to the VIN- terminal can becalculated by: ?R4-------+1??R5??R4-------+1??R5? VIN- for the most negative, - VREF+ for the most positive. R5 R4 6-18 元器件交易网 CA3310, CA3310A 6-19 元器件交易网 CA3310, CA3310A 6-20 扩展:ca3140中文资料 / smbj5.0ca中文资料 / smbj15ca中文 资料 篇四 : LA3161中文资料 元器件交易网 元器件交易网 元器件交易网 元器件交易网 元器件交易网 元器件交易网 元器件交易网 扩展:la3161 / tl431中文资料 / ds18b20中文资料
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