8位加法器程序源代码及仿真波形

8位加法器程序源代码及仿真波形 1. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(a,b:in std_logic_vector(15 downto 0); sum:out std_logic_vector(15 downto 0)); end adder; architecture rtl of adder is begin sum<=a+b; end rtl; 仿真波形图 2. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux4 is port(a,b:in std_logic_vector(3 downto 0); sel:in std_logic; y:out std_logic_vector(3 downto 0)); end mux4; architecture rtl of mux4 is begin process(sel,a,b) begin if(sel='0') then y<=a; else y<=b; end if; end process; end rtl; 仿真波形图 3. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity seven is port(input:in std_logic_vector(2 downto 0); a,b,c,d,e,f,g:out std_logic); end seven; architecture rtl of seven is begin process(input) begin case input is when "000" => a<='1';b<='1';c<='1';d<='1';e<='1';f<='1';g<='0'; when "001" => a<='0';b<='1';c<='1';d<='0';e<='0';f<='0';g<='0'; when "010" => a<='1';b<='1';c<='0';d<='1';e<='1';f<='0';g<='1'; when "011" => a<='1';b<='1';c<='1';d<='1';e<='0';f<='0';g<='1'; when "100" => a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1'; when "101" => a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1'; when "110" => a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1'; when "111" => a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1'; end case; end process; end rtl; 仿真波形图 4. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shifter is port(input:in std_logic_vector(7 downto 0); cnt:in std_logic_vector(1 downto 0); result:out std_logic_vector(15 downto 0)); end shifter; architecture rtl of shifter is begin process(cnt,input) begin case cnt is when "00" => for i in 15 downto 0 loop if i>=8 then result(i)<='0'; else result(i)<=input(i); end if; end loop; when "01" => for i in 15 downto 0 loop if i>=12 or i<=3 then result(i)<='0'; else result(i)<=input(i-4); end if; end loop; when "10" => for i in 15 downto 0 loop if i>=8 then result(i)<=input(i-8); else result(i)<='0'; end if; end loop; when "11" => for i in 15 downto 0 loop if i>=8 then result(i)<='0'; else result(i)<=input(i); end if; end loop; end case; end process; end rtl; 仿真波形图 5.(1) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rega is port(in_reg:in std_logic_vector(15 downto 0); clk:in std_logic; clr:in std_logic; clken:in std_logic; out_reg:out std_logic_vector(15 downto 0)); end rega; architecture rtl of rega is begin process(clk,clr,clken) begin if(clk'event and clk='1' ) then if (clr='1' and clken='0') then out_reg<=in_reg; else out_reg<="0000000000000000"; end if; end if; end process; end rtl; 仿真波形图 5.(2) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk:in std_logic; clr:in std_logic; sum:out std_logic_vector(1 downto 0)); end counter; architecture rtl of counter is begin process(clk,clr) variable m:std_logic_vector(1 downto 0); begin if(clr='0') then m:="00"; elsif(clk'event and clk='1') then m:=m+1; end if; sum<=m; end process; end rtl; 仿真波形图 6. (1) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity control is port(clk,rst,start:in std_logic; count:in std_logic_vector(1 downto 0); in_sel,shift:out std_logic_vector(1 downto 0); state_out:out std_logic_vector(2 downto 0); done,clken,regclr:out std_logic ); end entity control; architecture rtl of control is type states is(idle,lsb,err,mid,msb); signal current_state,next_state:states; begin reg:process(rst,clk ) is begin if rst='1' then current_state<=idle; elsif(clk='1' and clk'event) then current_state<=next_state; end if; end process reg; com:process(current_state,count,start) is variable m,n:std_logic; variable r:std_logic_vector(1 downto 0); begin case current_state is when idle=>state_out<="000"; if start='1' then next_state<=lsb; m:='0'; clken<='1';n:='0'; else next_state<=idle; m:='0'; clken<='1';n:='1'; end if; when lsb=>state_out<="001"; if (start='0' and count="00") then next_state<=mid;r:="00";shift<="00"; m:='0'; clken<='0';n:='1'; else next_state<=err; m:='0'; clken<='1';n:='1'; end if; when mid=>state_out<="010"; if (start='0' and count="01") then next_state<=mid;r:="01";shift<="01"; m:='0'; clken<='0';n:='1'; elsif (start='0' and count="10") then next_state<=msb;r:="10";shift<="01"; m:='0'; clken<='0';n:='1'; else next_state<=err ; m:='0'; clken<='1';n:='1'; end if; when msb=>state_out<="011"; if (start='0' and count="11") then next_state<=idle;r:="11";shift<="10"; m:='1'; clken<='0';n:='1'; else next_state<=err ; m:='0'; clken<='1';n:='1'; end if; when err=>state_out<="100"; if start='1' then next_state<= lsb ; m:='0'; clken<='1';n:='0'; else next_state<= err ; m:='0'; clken<='1';n:='1'; end if; end case; done<=m; regclr<=n; in_sel<=r; end process com; end rtl; 6.(1)仿真波形图 6.(2) LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY mult4x4 IS PORT ( dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END mult4x4; ARCHITECTURE SYN OF mult4x4 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT lpm_mult GENERIC ( lpm_hint : STRING; lpm_representation : STRING; lpm_type : STRING; lpm_widtha : NATURAL; lpm_widthb : NATURAL; lpm_widthp : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN result <= sub_wire0(7 DOWNTO 0); lpm_mult_component : lpm_mult GENERIC MAP ( lpm_hint => "MAXIMIZE_SPEED=5", lpm_representation => "UNSIGNED", lpm_type => "LPM_MULT", lpm_widtha => 4, lpm_widthb => 4, lpm_widthp => 8 ) PORT MAP ( dataa => dataa, datab => datab, result => sub_wire0 ); END SYN; 6.(2)仿真波形图 6.(3)仿真波形图