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首页 第8章程序部分8.20 电子时钟VHDL程序与仿真

第8章程序部分8.20 电子时钟VHDL程序与仿真.doc

第8章程序部分8.20 电子时钟VHDL程序与仿真

。CYSTE,M
2018-09-08 0人阅读 举报 0 0 暂无简介

简介:本文档为《第8章程序部分8.20 电子时钟VHDL程序与仿真doc》,可适用于工程科技领域

电子时钟VHDL程序与仿真进制计数器设计与仿真()进制计数器VHDL程序文件名:countervhd。功能:进制计数器有进位C最后修改日期:libraryIEEEuseIEEESTDLOGICALLuseIEEESTDLOGICARITHALLuseIEEESTDLOGICUNSIGNEDALLentitycounterisPort(clk:instdlogicreset:instdlogicdin:instdlogicvector(downto)dout:outstdlogicvector(downto)c:outstdlogic)endcounterarchitectureBehavioralofcounterissignalcount:stdlogicvector(downto)begindout<=countprocess(clk,reset,din)beginifreset=''thencount<=dinc<=''elsifrisingedge(clk)thenifcount=""thencount<=""c<=''elsecount<=countc<=''endifendifendprocessendBehavioral()进制计数器仿真进制计数器设计与仿真()进制计数器VHDL程序文件名:countervhd。功能:进制计数器有进位C最后修改日期:libraryIEEEuseIEEESTDLOGICALLuseIEEESTDLOGICARITHALLuseIEEESTDLOGICUNSIGNEDALLentitycounterisPort(clk:instdlogicreset:instdlogicdin:instdlogicvector(downto)dout:outstdlogicvector(downto)c:outstdlogic)endcounterarchitectureBehavioralofcounterissignalcount:stdlogicvector(downto)begindout<=countprocess(clk,reset,din)beginifreset=''thencount<=dinc<=''elsifrisingedge(clk)thenifcount=""thencount<=""c<=''elsecount<=countc<=''endifendifendprocessendBehavioral()进制计数器仿真进制计数器设计与仿真()进制计数器VHDL程序文件名:countervhd。功能:进制计数器。最后修改日期:libraryIEEEuseIEEESTDLOGICALLuseIEEESTDLOGICARITHALLuseIEEESTDLOGICUNSIGNEDALLentitycounterisPort(clk:instdlogicreset:instdlogicdin:instdlogicvector(downto)dout:outstdlogicvector(downto))endcounterarchitectureBehavioralofcounterissignalcount:stdlogicvector(downto)begindout<=countprocess(clk,reset,din)beginifreset=''thencount<=dinelsifrisingedge(clk)thenifcount(downto)=""thencount(downto)<=""count(downto)<=count(downto)elsecount(downto)<=count(downto)endififcount=""thencount<=""endifendifendprocessendBehavioral()进制计数器仿真译码器设计()译码器VHDL程序文件名:decodervhd。功能:将bit二进制数译码在LED上显示相应数字。最后修改日期:libraryIEEEuseIEEESTDLOGICALLuseIEEESTDLOGICARITHALLuseIEEESTDLOGICUNSIGNEDALLentitydecoderisPort(din:instdlogicvector(downto)四位二进制码输入dout:outstdlogicvector(downto))输出LED七段码enddecoderarchitectureBehavioralofdecoderisbeginprocess(din)begincasediniswhen""=>dout<=""when""=>dout<=""when""=>dout<=""when""=>dout<=""when""=>dout<=""when""=>dout<=""when""=>dout<=""when""=>dout<=""when""=>dout<=""when""=>dout<=""whenothers=>dout<=""endcaseendprocessendBehavioral顶层设计与仿真()顶层设计VHDL程序文件名:clockvhd。功能:时钟的顶层设计。最后修改日期:libraryIEEEuseIEEESTDLOGICALLuseIEEESTDLOGICARITHALLuseIEEESTDLOGICUNSIGNEDALLentityclockisPort(clk:instdlogicHzreset:instdlogic复位信号dins:instdlogicvector(downto)秒钟预置dinm:instdlogicvector(downto)分钟预置dinh:instdlogicvector(downto)时钟预置secondl:outstdlogicvector(downto)秒钟低位输出secondh:outstdlogicvector(downto)秒钟高位输出minutel:outstdlogicvector(downto)分钟低位输出minuteh:outstdlogicvector(downto)分钟高位输出hourl:outstdlogicvector(downto)小时低位输出hourh:outstdlogicvector(downto))小时高位输出endclockarchitectureBehavioralofclockiscomponentcounterisPort(clk:instdlogicreset:instdlogicdin:instdlogicvector(downto)dout:outstdlogicvector(downto)c:outstdlogic)endcomponentcomponentcounterisPort(clk:instdlogicreset:instdlogicdin:instdlogicvector(downto)dout:outstdlogicvector(downto)c:outstdlogic)endcomponentcomponentcounterisPort(clk:instdlogicreset:instdlogicdin:instdlogicvector(downto)dout:outstdlogicvector(downto))endcomponentcomponentdecoderisPort(din:instdlogicvector(downto)dout:outstdlogicvector(downto))endcomponentsignalc,c,c,c:stdlogicsignaldoutsl,doutml:stdlogicvector(downto)signaldoutsh,doutmh:stdlogicvector(downto)signaldouth:stdlogicvector(downto)signalrdoutsh,rdoutmh:stdlogicvector(downto)signalrdouth:stdlogicvector(downto)beginrdoutsh<=''doutsh将秒钟高位数据变为位再进行译码rdoutmh<=''doutmh将分钟高位数据变为位再进行译码rdouth<=""douth将时钟高位数据变为位再进行译码u:counterportmap(clk=>clk,reset=>reset,din=>dins(downto),dout=>doutsl,c=>c)u:counterportmap(clk=>c,reset=>reset,din=>dins(downto),dout=>doutsh,c=>c)u:counterportmap(clk=>c,reset=>reset,din=>dinm(downto),dout=>doutml,c=>c)u:counterportmap(clk=>c,reset=>reset,din=>dinm(downto),dout=>doutmh,c=>c)u:counterportmap(clk=>c,reset=>reset,din=>dinh,dout=>douth)u:decoderportmap(din=>doutsl,dout=>secondl)秒的低位u:decoderportmap(din=>rdoutsh,dout=>secondh)秒的高位u:decoderportmap(din=>doutml,dout=>minutel)分的低位u:decoderportmap(din=>rdoutmh,dout=>minuteh)分的高位u:decoderportmap(din=>rdouth(downto),dout=>hourh)时的低位u:decoderportmap(din=>rdouth(downto),dout=>hourl)时的高位endBehavioral()顶层设计仿真第页共页

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第8章程序部分8.20 电子时钟VHDL程序与仿真

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