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首页 PCB设计中的串扰问题

PCB设计中的串扰问题.pdf

PCB设计中的串扰问题

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2017-09-26 0人阅读 举报 0 0 0 暂无简介

简介:本文档为《PCB设计中的串扰问题pdf》,可适用于IT/计算机领域

DesignConCrosstalkforPrintedCircuitBoardDesignersLynneGreenHyperLynxADivisionofPADSSoftware,IncHighPerformanceSystemDesignConferenceDesignConABSTRACTThistutorialpaperlookssymptoms,causes,andwaystopreventcrosstalkproblemsonprintedcircuitboardsAsdigitaldesignersusefasterICsanddenser,morecomplexboardlayouts,crosstalkbecomesasignalintegrityissuethatcannolongerbeignoredThesymptomscanincludetimingviolations,falseclocking,andintermittentdatafaultsTheunderlyingcausesarerelatedtotheboardstackup,routingrules,andedgeratesoftheICsExampleswillbepresentedtoshowtheuseofsimulationtoevaluatepotentialsolutions,fromchangingthestackuptoreroutingcriticalnets,changingICs,oraddingterminationcomponentsBIOGRAPHYLynneGreenCurrentActivitiesLynneGreenistheProductMarketingEngineerforHyperLynxSheisalsoanAffiliateFacultymemberoftheUniversityofWashington,wheresheworkswithamodelingresearchgroupBackgroundLynneGreenhasspentoveryearsindesignandconsulting,andsheholdsMSEEandPhDdegreesinElectricalEngineeringfromtheUniversityofWashingtonDesignConCrosstalkSymptomsAssystemspeedsandpackagepincountsincrease,boarddesignsbecomemorecomplex,androutingbecomesdenser,crosstalkbecomesanissueformoredesignersPerhapsthegreatestchallengeduringtestingisdeterminingwhenprototypefailuresareduetologicerrors,andwhentheymightbeduetocrosstalkThebestsolutionisprevention,usingsimulationduringdesigntoeliminatecrosstalkbeforeitoccursAnumberofsymptomscanbeusedtoidentifysignalintegrityandcrosstalkproblemsThesymptomsareshowninSlideaboveBecausecrosstalkproblemscanbeintermittent,theyareoftendifficulttodebuginthelabByusingsimulationforvirtualprototyping,thesesymptomscanbeidentifiedbeforeaprototypeisbuilt,savingdevelopmentcosts,prototypeturns,andtimetomarketSignalintegritysymptomsincludeovershoot(beyondpowersupplyrails),undershoot(whichcancausefalseclocksanddatafaults),andringingTheseareshowninSlidesandCrosstalkcancauseaquiescent(static)clockordatalinetocrossalogicthresholdwhenaneighboringnetswitchesWhenasignalisbetweenVILandVIH,thevalueonthereceiverinputmaybeinterpretedaseitheraoraThisisseeninFigure,wherethequiescentsignalhasahumpofVoltthisiswellabovetheVILofvoltsformanylogicfamiliesBothcrosstalkandtimingaresensitivetoICprocess,temperature,andpowersupplyvoltagevariationsCrosstalk,however,isalsosensitivetotheswitchingstateofneighboringnetsontheboardForexample,adatabusmayhaveerrorsononebitwhentheadjacentbitsareswitching,butnotwhentheyarestaticCrosstalkerrorsonclocklinesareparticularlydifficulttodebugForexample,thecrosstalkhumpseeninFigurecouldbeenoughtotriggeralatch,causingittocapturedataSeparatingaclockingproblemfromalogicortimingproblemrequiresagoodoscilloscope,inadditiontoahighspeedlogicanalyzerCrosstalkalsoimpactstimingoftransitions,asseeninFigureThetimingforanetonabusdependsonwhethertheothernetsonthebusarerising,falling,orstaticBecausethistimingvariationcanbelarge,crosstalkeffectsmustbeincludedwhenanalyzingworstcasetimingCrosstalkInPrototypesbullLogicStateDependentbullNeighborTransitionDependentbullVoltageTemperatureDependentbullIntermittentFaultsbullDifficulttoDebugSignalIntegritySymptomsOvershootUndershootRingingBoardSimLineSim,HyperLynxvoltsvoltsvoltsnsnsVdivnsecdivProbe:Probe:SignalIntegritySymptomsDelaySkewBoardSimLineSim,HyperLynxvoltsvoltsvoltsnsnsmVdivpsecdivProbe:Probe:Probe:Probe:CrosstalkSymptomsEdgescoupleQuietlineswiggleQuietlinesswitchBoardSimLineSim,HyperLynxvoltsvoltsvoltsnsnsVdivpsecdivProbeProbeProbeCrosstalkSymptomsTimingdependsoncrosstalkMiddlelineonabusDesignConPhysicalOriginsThephysicalcausesofcrosstalklieinthenatureofthephysicalroutingEachwiresegmentactsasaninductorandcapacitor,andalsoasanantennaTwowiresaddmutualinductanceandcapacitance,andarethereforecoupledantennasEachnetbecomesapotentialaggressor,capableofcouplingsignalsontovictimnetsCrosstalkisgreatestwhenthenetsareclosest,wherethemutualinductanceandcapacitancearegreatestCrosstalkdependsontheaggressorsignal#sedgerate,aswellasongeometryfactors(Figures)Byunderstandingoriginsofthesefactors,designerscanreducecrosstalkthoughappropriatechoicesforstackup,routingrules,andterminationstrategiesAsseeninFigure,fasterICedgeratesleadtosignificantincreaseincrosstalkEvenaveryslownet(MHzorless)maycreatecrosstalkduetoafastedgerateFigureshowsastackupcrosssection,withelectricandmagneticfieldscouplingtheaggressorandvictimnetstogetherFigureshowsthatcrosstalkincreaseswithedgerate,whileFigureshowsincreaseswithlinelengthItisdifficulttocalculatethecrosstalkamplitude,sincethedependenceonlinelength,width,anddistancetogroundplanesishighlynonlinearWhilerulesofthumbcanbeused,theyarenotreliableifthenewlayoutuseshigheredgeratesordenserroutingReducingCrosstalkCrosstalkcanbereducedbyselectingtheslowestICedgeratethatmeetsthesystemoperatingspeedrequirements,orbyselectingapartwithaloweroutputswing(bothofwhichlowerdVdt)FigurelistsothereffectsShorterparallelroutesegmentshavelesscrosstalk,solongroutesshouldbeeitherspacedfurtherapartorrunondifferentsignallayerswithagroundorpowerplanebetweenthemChangingstackup,suchasdecreasingthedielectricconstantoftheboardmaterialordecreasingthethickness,helpdecreasecrosstalkChangingroutingrules,suchasdecreasinglinewidthorincreasingspacingbetweenwires,alsohelpsDependencies:EdgeRateBoardSimLineSim,HyperLynxComment:FastandSlowEdgeRateEffectsvoltsvoltsvoltsnsnsVdivpsecdivProbeProbeProbeProbeFastedgeSlowedgeDependencies:LineLengthggBoardSimLineSim,HyperLynxComment:INCHANDINCHLINESvoltsvoltsvoltsnsnsmVdivnsecdivProbeProbeLonglineShortlinebullTwoormoreneighboringtracesbullCoupledthroughEMfieldsbullTheldquoaggressorrdquotraceswitches,causescrosstalkbullTheldquovictimrdquotracedevelopsanunintendedsignalbullNetcanbebothaggressorandvictimCrosstalkOriginsReducingCrosstalkbullShorterparallelrunsbullWiderspacingbullThinnerdielectricsbullLowerepsilonrdielectricmaterial($)bullChangelayersforsegmentsSensitivitiesofCrosstalkbullGeometryofroutingbullICProcessvariationsbullTemperaturebullPowersupplyvoltagebullAggressornetsswitchingbullEdgeratesofaggressornetdriversDesignConSometimesitissufficienttoreducethesharppeakontheleadingedgeofthecrosstalkpulseThissharppeak,causedbyforwardcrosstalk,canbereducedoreveneliminatedbychangingthestackupThisisbecausecapacitiveandinductiveeffectscancancel,sincetheyhaveoppositesignsThemagnitudeofforwardandespeciallybackwardcrosstalkcanbehardtoestimateBackwardcrosstalk,forexample,saturatesandceasestogrowatsomepoint(notetheflatportionofthecrosstalkresponse)Theamplitudedependsnotonlyonthestackupgeometry,butalsoonedgerateandlinelengthFigureandshowhowmovinganettothecenter(stripline)reducestheforwardcrosstalkbutdoesnotreducethebackwardcrosstalkTerminationThereareseveralwaystoreducecrosstalk(Figure)Oncethestackupandroutingruleshavebeenoptimizedforcrosstalkreduction,thedesignercandecidewhichaggressorandvictimnetsrequireterminationTerminationcanbedoneatthedriver(forsingleloadnets)oratreceivers(formultiloadnets)TerminatinganetusuallyreducesbothovershootandundershootTheterminationstrategymustbechosenbasedonthenettopology:seriesterminationforsingleloadnetsparallelACfordaisychains,parallelACateachloadforstarrouting,andbothdifferentialandcommonmodeterminationfordifferentialnets(Figure)ParallelACtermination,showninFiguresand,reducesreflectionsfromthereceiverItrequirestheuseoftwocomponentsSimulationshouldbeusedtooptimizetheRCtimeconstantforthedesignForwardandBackwardCrosstalkSignalAggressortraceVictimtraceforwardcrosstalkldquopilesuprdquoinfrontbackwardcrosstalkstretchesoutbehindggBoardSimLineSim,HyperLynxComment:inchlinecomparefwdbkwdeffectsvoltsvoltsvoltsnsnsmVdivnsecdivDtTdNTiProbe:U(C)Probe:U(B)EffectsofChangingLayersForwardBackwardCrosstalkMicrostrip(toplayer)Stripline(innerlayer)TheTerminationProcessbullTracetopologyndashPointtopoint,Tappedbus,StarbullDesignrequirementsndashSpeed,Connectivity,MatchingbullTerminationndashDriverReceivercharacteristicsndashTolerancesZZGoodterminationwhilereflectionsdieoutgraduallygoestohighimpedanceCParallelACTerminationBoardSimLineSim,HyperLynxComment:inchlinecomparefwdbkwdeffectsvoltsvoltsvoltsnsnsmVdivnsecdivProbe:U(A)Probe:U(C)Probe:U(B)EffectsofChangingLayersLongerLinesMicrostrip(toplayer)Stripline(innerlayer)ReducingCrosstalkbullRoutingtopologiesbullSlowerICedgeratesbullTerminationDesignConSeriestermination,whichusesaterminatingresistoratthedriver,dampsoutthebackwardcrosstalkbutdoesnotaffecttheforwardcrosstalkWhiletheresistorvaluehasonlyasmallimpactontiming,itdoeshaveanimpactonovershootandundershoot(Figures)Becauseseriesterminationusesasinglecomponent,ithasasmallerimpactonboardspacethandoesanACparallelterminationHowever,whentherearemultipleloads,theseriesresistordoesnotdampthereflectionsbetweentheloads,butonlythosethatcomebacktothedriverAtappedbusisanexampleofmultidroploadingwithdaisychainrouting(Figure)Thistypeofbusisalmostimpossibletoterminateproperly,sinceeachtaponthebusputsanotherreflectionpointintotheroutingWhenadaisychainisunavoidable,itshouldbeterminatedwithanACloadatthelastreceiverHowever,becausetheringingmaynotbeadequatelydamped,crosstalkandsignalintegritymaynotmeetrequirementsThisisparticularlyaproblemforwidebussesDifferentialnets(Figure)needtoberoutedandterminatedwithcareThiswillimprovesignalintegrityandhelpreducecrosstalkwithnearbynetsSimilarly,starroutednets(Figure)shouldbeterminatedateachindividualreceivertoimprovesignalintegrityandreducecrosstalkbullParallelACadvantagesndashBurnslesspowerthanDCparallelbullDisadvantagesndashTwocomponentsrequiredndashNoteasytochoosecapacitorvaluebullExampleofusendashMultireceivernetsParallelACTerminationbullAdvantagesndashOnlyonecomponentrequiredndashBurnsaminimumofpowerbullDisadvantages:ndashHardtochooseresistorvaluendashHardtousewithmultiplereceiversbullExampleofusendashAnyoneloadtraceSeriesTerminationPickingtheRightSeriesTerminatorΩ(Blueovershoot,underdampedRtoolow)Ω(Greengoodmatch)Ω(Redoverdamped,Rtoohigh)BoardSimLineSim,HyperLynxComment:PickingtherightseriesterminatvoltsvoltsvoltsnsVdivnsecdivRs=ZoRDHavingagoodsimulatorgivesyouZRDispartofthedriverICmodelSeriesTerminatorCalculationRsPCBTraceZoRDTappedBusTerminationbullUnequaldelaysguaranteedbullDiscontinuityateverytapbullStubsmakeldquoechochambersrdquobullImpossibletoterminateperfectlyDifferentialTerminationbullDifferentialsignalsusetwotracesbullTracesequallength(ideally)bullDifferentialmodesignalbullCommonmodenoisebullRequiresresistorsforfullterminationStarTerminationbullKeeplengthsmatchedifpossiblebullDrivernearcenterifpossiblebullEachlegofstarisldquoechochamberrdquobullMultiplereflectionshardtodampbullTerminateatloadsDesignConCrosstalkAnalysisSimulationcanbeusedtoevaluatetheamplitudeofthecoupledcrosstalk(bothforwardandbackwardeffects)Comparisonstodesignrequirementscanbedonevisually(egusingavirtualscopedisplay),orusingaspreadsheetapproachSimulationcanalsobeusedtoquicklyevaluatevariousterminationandroutingoptionsForexample,youcancomparetheeffectsoftermination(Figuresand)andchangingterminationstrategy(Figuresand)PickingtheoptimalterminationcanbedoneusingtrialanderrororbyusingansoftwaretoselecttheterminationstrategyandcomponentvaluesSummaryBecausecrosstalksymptomsareoftenintermittentandthereforedifficulttodebuginthelab,simulationshouldbeintegratedthroughoutthedesigncycletocatchthecrosstalkproblemsandidentifysolutions(Figure)ThecostofoverlookingasignalintegrityorcrosstalkproblemishighThereisnothingworsethandeterminingthattherightsolutionisanACloadatthereceiver,onlytodiscoverthatthereisnoroomanywherenearthereceiverfortherequiredcomponentsPrelayoutsimulationallowsthedesignertoselecttheoptimumterminationstrategy,andtospecifyrelativecomponentlocationonthelayoutSimulationafterthelayouthasbeencompletedallowsthedesignertoidentifyanyremainingcrosstalkrisks,andtomodifythedesignbeforeanexpensiveprototypeisbuiltByunderstandingthesymptomsandoriginsofcrosstalk,andhowcontrollingsignalintegrityhelpscontrolcrosstalk,theboarddesignercanimprovehisdesignwhilegettingtheproductoutthedoorquickly(Figure)BeforeAfterTerminationEffectoncrosstalkofterminationofhighspeedaggressorSeriesterminationofsingleloadlineBeforeAfterTerminationEffectoncrosstalkofterminationofhighspeedaggressorSeriesterminationofsingleloadlineBoardSimLineSim,HyperLynxvoltsvoltsvoltsnsnsmVdivnsecdivProbe:U(D)UnterminatedTerminatedDifferentTerminationStrategiesACSERIESDifferentTerminationStrategiesACDampsFasterSERIESLowerBoardSimLineSim,HyperLynxvoltsvoltsvoltsnsnsmVdivnsecdivDtTdNTiProbe:U(B)Probe:U(B)SummarybullIdentifyingCrosstalkndashLogicStateDependentndashNeighborTransitionDependentndashVoltageTemperatureDependentndashIntermittentFaultsbullSimulatetoIdentifyProblemAreasSummarybullCrosstalkPreventionndashCircuitDesignndashLayoutTopologyndashTerminationbullSimulatetoIdentifySolutions

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