250V Integrable Silicon Lateral Trench Power MOSFETs with Superior

Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs May 27-30, 2007 Jeju, Korea 250V Integrable Silicon Lateral Trench Power MOSFETs with Superior Specific On-Resistance K.R. Varadarajan, T.P. Chow, J. Wang', R. Liu', F. Gonzalez' Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180, U.S.A. Tel: +518-276-6044, Fax: +518-276-8761, e-mail: l Supertex, Sunnyvale, CA 94089, U.S.A. Abstract- A lateral trench power MOSFET in the 250V class, with a reduced specific on-resistance is proposed. Simulation results of an optimized device structure exhibits a low specific on-resistance of 7mf2-cm2, which is 2.5X lower than that of the conventional lateral DMOSFET. Effects of design parameters on the device performance are examined. An improved device structure with reduced sensitivity to process variations is also presented. I. INTRODUCTION Improvements in the on-resistance have been limited in the conventional design of lateral power MOSFETs because of the long drift region. RESURF technology has been successfully employed in improving the breakdown voltage vs. specific on-resistance tradeoffs in lateral power MOSFETs [1,2]. An LDMOS structure below 100V with an oxide filled trench region under the gate enabling a reduced cell pitch was proposed [3]. Implementing lateral power MOSFETs in a trench-based technology has been shown to reduce the specific on-resistance, mainly because of the reduced cell pitch [4,5]. These devices with an 80-1OOV breakdown voltage have a trench gated structure with the drift region formed along the trench sidewalls and cut down the specific on-resistance by about 50% over the conventional lateral power MOSFET. However, these structures are not suitable for extension to higher voltages owing to the deep trenches involved and the fabrication complexities associated with forming two electrodes inside the same trench. II. DEVICE STRUCTURE AND OPERATION The schematic cross-section of the proposed lateral trench power MOSFET is shown in Fig. 1. The device is built on a n-type epitaxial layer, which constitutes the drift region, on p- type substrate. It has two trenches, an oxide-filled trench employed in addition to the poly-Si-filled trench gate, with the source region being formed in between them. The DMOS channel region formed vertically along the source pillar is identical to that of conventional vertical trench MOSFETs. This work was supported primarily by the ERC Program of the National Science Foundation under Award Number EEC-9731677. Drain ematic cross-section of tne propose MOSFET The drift region can be considered to be 'wrapped' around three sides of the oxide spacer. The dimensions (depth and width) of the oxide spacer determine the length of the drift region. The width of the drain and source pillars together with the thickness of the epi layer beneath the oxide spacer determine the RESURF dose in the drift region. In the ON-state, electrons flow from the source, through the channel into the n-epi layer, and travel around the oxide spacer before getting collected at the drain. In the OFF state, the presence of the oxide spacer reshapes the electric field in the drift region enabling an efficient voltage support capability. The equi-potential profile of the device in OFF state close to breakdown (250V) is shown in Fig. 2. Good RESURF action can be observed along the drain pillar and underneath the oxide spacer while the large separation between the p-body/n-epi and the n-epi/p-substrate junctions and the deep gate trench prevents optimal RESURF action along the source pillar. It can be observed that it is possible to compact a drift length of about 16ptm around an oxide trench 7.0ptm deep and 3.0ptm wide, enabling a half-cell pitch of only 6.5ptm. This compact footprint in turn results in a significantly reduced specific on-resistance enabling smaller die size, lower costs and improved die yield as compared to a conventional lateral power MOSFET. 1-4244-1096-7/07/$25.00 ©2007 IEEE 233 Authorized licensed use limited to: Jiangnan University. Downloaded on October 18, 2008 at 04:22 from IEEE Xplore. Restrictions apply. * BV Oxide trench w idth =3.0tm Oxide trench depth =7.0tm Epi doping =7.5e15/cm3 Epi thickness =7.5ptm Fig. 2 Simulated equi-potential lines in the off state, at an applied bias of 250V It is critical to have the depth of the gate trench to match that of the oxide trench in order to have proper field shielding. A shallower gate trench would expose a larger charge region to the gate leading to high electric field at the trench corner and causing device breakdown. The simulated equi-potential lines at breakdown for the case with a shallower gate trench depth of 6ptm are shown in Fig.3. The sensitivity of the device breakdown voltage to the trench depth mismatch was studied and is shown in Fig. 4. The breakdown voltage becomes stable for increasing gate trench depths as the exposed charge at the trench corner gets reduced improving the field shielding. 5.8 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 Gate trench depth (prm) Fig. 4 Breakdown voltage dependence on the gate trench depth for a fixed oxide trench depth of 7.0ptm Having established the need to maintain matching depths for both the trenches, device performance was then simulated and optimized for a combination of trench depths and epi layer doping. Since the epi layer doping effectively controls the RESURF dose in the various regions of the drift layer, it is a key parameter in determining the device breakdown voltage. Figs. 5 and 6 illustrate the BV vs Ron,sp trade-offs for different epi layer doping (7.5el5/cm3 and 8.5el5/cm3) at varying trench depths. The specific on-resistance has been computed at VGS=I5V. 300 > 250 a) < s 200 0 > 150 0 ° 100 m) L50 co + BV - Ron,sp Oxide trench width =3.0tm Epi doping =7.5e1 5/cm3 Epi thickness = 7.5ptm 12 10 E 8 Y E 6 0 E 4 cn 0 2 0 6.4 6.6 6.8 7 Trench depth (p1m) Fig. 3. Simulated equi-potential lines at breakdown (80V) Fig. 5. BV vs. Ron,sp tradeoff for an epi layer doping of 7.5el5/cm3 as a function of trench depth For a given epi layer doping, BV can be seen to flatten out at large trench depths, while collapsing when moving in the opposite direction. This can be explained by considering the amount of charge present in the region underneath the oxide spacer. A shallow trench depth means a greater charge in the region, which diminishes the field shielding at the gate trench corner causing premature device breakdown. This effect is 234 Source Drain Gt Gate !1 300 2. 250 a) X 200 > 150 0 -° 100 a)L 50 o 0 7.2 7.4 Authorized licensed use limited to: Jiangnan University. Downloaded on October 18, 2008 at 04:22 from IEEE Xplore. Restrictions apply. seen to get worse at higher epi-doping, as expected. Specific on-resistance increase with increasing trench depths is due to the pinching of the drift region under the oxide trench. 300 1 0 - 250 a) X 200 m > 150 o 100 (0 a) 50 m 0 * BV - Ron,sp *. 6 EC4E Oxide trench width =3.0mt n Epi doping =8.5e1 5/cm3 2r° Epi thickness = 7.5ptm 6.4 6.6 6.8 7 Trench depth (p1m) 0 7.2 7.4 Fig. 6. BV vs. Ron,sp tradeoff for an epi layer doping of 8.5el5/cm3 as a function of trench depth III. IMPROVED DEVICE STRUCTURE From the previous discussion, it can be observed that the device breakdown voltage is highly sensitive to the trench depths. Due to the weak RESURF action along the source pillar, the charge in the region around the gate trench bottom is very critical for proper device operation. The performance of vertical trench MOSFETs have been shown to improve by use of the RESURF effect based on field plate action in the gate trench [6,7,8]. These devices have a field plate connected to the gate that extends along the entire drift region towards the substrate and is isolated from the drift region by a thick oxide layer. Based on this concept, a modified structure has been developed, incorporating a field plate in the gate trench as shown in Fig .7. Fig. 7 Schematic cross-section of the Lateral Trench Power MOSFET with a gate field plate Simulations were performed to study the effect of the structural modification on the device performance. Fig. 8. illustrates the BV vs Ron,sp trade-offs for an epi layer doping of 7.5el5/cm3 at varying trench depths. When compared with Fig. 5, it can be observed that the sharp fall in breakdown voltage at lower trench depths has been significantly improved. The modified structure thus illustrates greater robustness in breakdown voltage over the range while exhibiting a similar specific on-resistance tradeoff. The equi- potential lines in the OFF state for a structure with trench depth 6.7ptm are shown in Fig. 9. This device structure has a breakdown voltage of 250V, which is significantly higher than the 190V supported by the original device of corresponding dimensions. 300 > 250 a) X 200 0 > 150 0 - 100 a) m 50 12 + -- - - + , . * BV - Ron,sp Oxide trench width =3.0tm Epi doping =7.5e15/cm3 Epi thickness = 7.5ptm 0 6.4 6.6 6.8 7 Trench depth (pim) 10 E 8 Y E 6 0 E 4 U- 0 2 0 7.2 7.4 Fig. 8. BV vs. Ron,sp tradeoff for an epi layer doping of 7.5el5/cm3 as a function of trench depth for the modified device structure Source Drain / Gate AD 2 x 3AC COO Fig. 9 Simulated equi-potential lines in the off state, at an applied bias of 250V 235 Authorized licensed use limited to: Jiangnan University. Downloaded on October 18, 2008 at 04:22 from IEEE Xplore. Restrictions apply. The key to the superior specific on-resistance of the proposed lateral trench power MOSFETs is the significantly reduced cell pitch enabled by trench technology, coupled with effective RESURFing that permits a greater charge in the drift region. Specific on-resistance of the optimized device plotted together with the junction-isolated lateral RESURF limit is shown in Fig. 10. Significant reduction in the specific on-resistance is obtained for the proposed devices at 250V, and is also compared with a simulated lateral DMOSFET. 1.E-01 E 0 E 0 CU 1.E-02 cn, Silicon JI RESURF Limit Lateral Trench MOSFET0 - , * Lateral Trench MOSFET with a Gate Field Plate (D . A Lateral DMOSFETU) 1.E-03 100 [3] M. Zitouni, F. Morancho, P. Rossel, H. Tranduc, J. Buxo and I.Pages, "A new concept for lateral DMOS transistor for smart power IC's", in Proc. International Symposium on Power Semiconductor Devices and ICs, pp. 73-76, 1999. [4] N. Fujishima and C. A. T. Salama, " A trench lateral power MOSFET using self-aligned trench bottom contact holes", in International Electron Device Meeting Tech Digest, pp. 359-362, 1997. [5] N.Fujishima, A.Sugi, T. Suzuki, S.Kajiwara, K.Matsubara, Y.Nagayasu, and C.A.T. Salama, "A High Density, Low On-resistance Trench lateral Power MOSFEt with a Trench Bottom Source Contact," in IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1462- 1468, August 2002. [6] Y. Baba, N. Matsuda, S. Sangiya, S. Hiraki and S. Yasuda, "A study on a high blocking voltage UMOS-FET with a double gate structure", in Proc. International Symposium on Power Semiconductor Devices and ICs, pp. 300-302, 1992. [7] G.E.J. Koops, E.A. Hijzen, R.J.E. Hueting, and M.A.A. in't Zandt, "Resurf Stepped Oxide (RSO) MOSFET for 85V having a record-low specific on-resistance", in Proc. International Symposium on Power Semiconductor Devices and ICs, pp. 185-188, 2004. [8] M. Kodama, E. Hayashi, Y. Nishibe and T. Uesugi, "Temperature characteristics of a new 100V rated power MOSFET, VLMOS (Vertical LOCOS MOS)", in Proc. International Symposium on Power Semiconductor Devices and ICs, pp. 463-466, 2004. 1000 Breakdown Voltage (V) Fig. 10. Specific on-resistance plotted along with the silicon limit IV. SUMMARY Integrable lateral trench power MOSFETs with a breakdown voltage of 250V and reduced specific on- resistance are reported. Simulation results of the optimized device structure exhibit a low specific on-resistance of 7mQ- cm2, which is a 2.5X reduction on the conventional lateral DMOSFET. An improved device structure with reduced sensitivity to process variations is also presented. ACKNOWLEDGMENT This work was supported primarily by the ERC Program of the National Science Foundation under Award Number EEC- 973 1677. REFERENCES [1] T. Efland, S. Malhi, W. Bailey, Oh Kyong Kwon, Wai Tung Ng, M. Torreno, and S. Keller, "An optimized RESURF LDMOS power device module compatible with advanced logic processes", in International Electron Device Meeting Tech Digest, pp. 237-240, 1992. [2] T. Efland, P. Mei, D. Mosher and B. Todd, "Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent Rsp vs BV performance", in Proc. International Symposium on Power Semiconductor Devices &ICs, pp.147-150, 1996. 236 Authorized licensed use limited to: Jiangnan University. Downloaded on October 18, 2008 at 04:22 from IEEE Xplore. Restrictions apply.