redrawn-4004-schematics-2006-11-12

BBBB ADDRESS REGISTER BBBBBBBB REGISTER INDEX B D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D1 D2 D3 GND CLK1 CLK2 SYNC POC TEST CM ROM VDD CM RAM3 CM RAM2 CM RAM1 CM RAM 0 PIN CONFIGURATION GATE PROTECTION TO OR FROM PAD GND VDD = = REFRESH COUNTER REFRESH COUNTER ADDRESS REGISTER4004 EFFECTIVE ADDRESS COUNTER Re-drawn schematics based on Revision G of the original Intel 4004 schematics by Intel Corporation (August 6, 1976). Schematic capture and design verification by Fred Huettig, Brian Silverman and Barry Silverman (February 2, 2006). ------------------------------------------------------------- You are free: Under the following conditions: * to make derivative works * to copy, distribute, display, and perform this work Attribution. You must attribute the work in the manner specified by the author or licensor. Noncommercial. You may not use this work for commercial purposes. Share Alike. If you alter, transform, or build upon this work, you may distribute the resulting work only under a license identical to this one. * For any reuse or distribution, you must make clear to others the license terms of this work. * Any of these conditions can be waived if you get permission from the copyright holder. Your fair use and other rights are in no way affected by the above. This is a human-readable summary of the Legal Code (the full license) available at: http://creativecommons.org/licenses/by-nc-sa/2.5/legalcode Intel is a registered trademark of the Intel Corporation INCREMENTER AND INDEX REGISTER Sheet 1 of 3 O 2 O 1 O 2 & S C { A 1 2 + M 1 2 } ~ P O C & O 2 & S C { A 3 2 + X 1 2 } R R A B 0 R R A B 1 D 0 INCREMENTER ~ I N H { X 1 1 + X 3 1 } O 1 O 2 O1 S C & M 2 2 & O 2 S C { A 2 2 + M 2 2 } O 2 S C & A 2 2 F I N & X 1 2 ~INH&X32&O2 VDD D 3 D 2 D 1 O 1 W R A B 0 W R A B 1 O1 SC&A12&O2 X32 X12 W A D B 2 R A D B 2 W A D B 1 R A D B 1 W A D B 0 R A D B 0 ~ P O C & O 2 { X 1 2 + X 3 2 } ~ I N H ~ { D C { J I N + F I N } } O 1 { M 1 1 + X 2 1 } ~ I N H M 1 2 + M 2 2 + O 1 ~ { M 1 1 + M 1 2 } A 1 2 A 2 2 A 3 2 O2{JMS&DC&M22+BBL{M22+X12+X22}} O1 Re-drawn schematics based on Revision G of the original Intel 4004 schematics by Intel Corporation (August 6, 1976). Schematic capture and design verification by Fred Huettig, Brian Silverman and Barry Silverman (February 2, 2006). ------------------------------------------------------------- You are free: Under the following conditions: * to make derivative works * to copy, distribute, display, and perform this work Attribution. You must attribute the work in the manner specified by the author or licensor. Noncommercial. You may not use this work for commercial purposes. Share Alike. If you alter, transform, or build upon this work, you may distribute the resulting work only under a license identical to this one. * For any reuse or distribution, you must make clear to others the license terms of this work. * Any of these conditions can be waived if you get permission from the copyright holder. Your fair use and other rights are in no way affected by the above. This is a human-readable summary of the Legal Code (the full license) available at: http://creativecommons.org/licenses/by-nc-sa/2.5/legalcode Intel is a registered trademark of the Intel Corporation TO ADDER / ACCUMULATOR CONTROL MEMORY CONTROL ADDRESS Sheet 2 of 3 T E S T O 1 O 2 M 2 2 W R A B 1 X 3 2 SC INC+ISZ+XCH FIN+FIM+SRC+JIN SC M 1 2 W R A B 0 JIN+FINJUN+JMS JCN+ISE CN INH INH P O C A 2 2 A 3 2 X 1 2 S C & M 2 2 & O 2 FIM+SRC IO OPE ~ { D C { J I N + F I N } } O 1 { M 1 1 + X 2 1 } ~ I N H A 1 2 FIN+FIM O P E I / O D 3 D 0 OPA_REGISTER OPR_REGISTER L CONDITION_F/F SINGLE_CYCLE_F/F R A D B 0 S C { A 2 2 + M 2 2 } O 2 O 2 { J M S & D C & M 2 2 + B B L { M 2 2 + X 1 2 + X 2 2 } } ~ P O C & O 2 { X 1 2 + X 3 2 } ~ I N H ~ I N H & X 3 2 & O 2 ~ I N H { X 1 1 + X 3 1 } O 1 O 2 & S C { A 1 2 + M 1 2 } ~ P O C & O 2 & S C { A 3 2 + X 1 2 } F I N & X 1 2 S C & A 2 2 S C & A 1 2 & O 2 I O R JUN+JMS INC+ISZ+ADD+SUB+XCH+LD I N C / I S Z X C H X 2 2 JMSBBLJCNISZ M 1 2 + M 2 2 + O 1 ~ { M 1 1 + M 1 2 } M12 I O W O2O1 R R A B 0 R R A B 1 R A D B 1 R A D B 2 A C C _ 0 C Y _ 1 S R C K B P LDM/BBL X21&/O2 A D D5 S U B L D12 A D M C L B3 C L C I A C 46 D A C C M C S T C C M A R A L R A R D A A T C S O - I B D C L O1 O2 W A D B 2 W A D B 1 W A D B 0 OPA-IB T C C S B M A D D _ 0 D 2 D 1 B B BB B B B O I O I Re-drawn schematics based on Revision G of the original Intel 4004 schematics by Intel Corporation (August 6, 1976). Schematic capture and design verification by Fred Huettig, Brian Silverman and Barry Silverman (February 2, 2006). ------------------------------------------------------------- You are free: Under the following conditions: * to make derivative works * to copy, distribute, display, and perform this work Attribution. You must attribute the work in the manner specified by the author or licensor. Noncommercial. You may not use this work for commercial purposes. Share Alike. If you alter, transform, or build upon this work, you may distribute the resulting work only under a license identical to this one. * For any reuse or distribution, you must make clear to others the license terms of this work. * Any of these conditions can be waived if you get permission from the copyright holder. Your fair use and other rights are in no way affected by the above. This is a human-readable summary of the Legal Code (the full license) available at: http://creativecommons.org/licenses/by-nc-sa/2.5/legalcode Intel is a registered trademark of the Intel Corporation /O2 /O2 /O2 /O2 /O2 /O2 A12 M12 X12 X22 /O2 Sheet 3 of 3 ROM0 POC SYNC VDD GND D0 D1 D2 D3 RAM3RAM2RAM1RAM0 D3 X21&/O2 O-IB D0 O2 X12 X22 POC O1 X31&/O2 M12 6 ADSL ADD-ACC ADSR ADC-CY CY_1 CY-ADAC CY-ADA CARRY_F/F ACC-ADAC ACC-ADA D2 5 TIMING IO_BUFFER_0 IO_BUFFER_1 ACB-IB D1 L 4 6 ADD-IB ACC_0 IO_BUFFER_3 ADD_0 2 CY-IB O1 O1 INC/ISZ IO_BUFFER_2 POC O2 RAR RAL X12 A12 IOR X31&/O2 IOR O2 IOW XCH DAA COM TCS KBP M12A22 S R C I / O DCL A12 M22 X32 A32 COM OPE CMA 3 1 O2 O1