Chapter5:ConfigurationDetailsiMPACTAccesstoDeviceIdentifierTheiMPACTsoftwareinISE10.1(andlater)toolscanalsoreadthedeviceDNAvalue.readDna-p
isthebatchcommandthatreadsthedeviceDNAfromtheFPGA.BitstreamCompressionBydefault,FPGAbitstreamsareuncompressed.However,Spartan-6FPGAssupportbasicbitstreamcompression.Thecompressionisfairlysimple,yeteffectiveforsomeapplications.TheISEbitstreamgeneratorsoftwareexaminestheFPGAbitstreamforanyduplicateconfigurationdataframes.Theseduplicatesoccurofteninthesesituations:•FPGAdesignswithunusedblockRAMorhardwaremultipliers.•FPGAdesignswithlowlogicutilization,suchaswhenmostoftheFPGAarrayisempty.TheISEsoftwarecanthengenerateacompressedFPGAbitstream.AstheFPGAconfigures,theinternalconfigurationcontrollercopiestheredundantdataframetomultiplelocations.Compressionisnotsupportedforencryptedbitstreams.Theamountofcompressionisnon-deterministic.ChangestothesourceFPGAdesigncancausethesizeofthecompressedbitstreamtogrow.Sparse,mostlyemptyFPGAdesignshavethegreatestoverallcompressionfactor.Similarly,FPGAdesignswithanemptycolumnofblockRAMhaveahighcompressionfactor.Theoverallbenefitsofacompressedbitstreamare:•Smallermemoryfootprint.•Fasterprogrammingtimefornonvolatilememory.•Fasterconfigurationtime.CompressionisenabledusingtheBitGenoption-gcompress.ParallelPlatformFlashPROMsoffertheirowncompressionmechanisms.Formoredetails,seethe“XCFxxPDecompressionandClockOptions”chapterinUG161,PlatformFlashPROMUserGuide.Spartan-6FPGAConfigurationUserGuideUG380(v2.11)March22,2019VerifyingReadbackDataVerifyingReadbackDataThereadbackdatastreamcontainsconfigurationframedatathatareprecededbyoneframeofpaddata,asdescribedintheConfigurationMemoryReadProcedure(SelectMAP).ThereadbackstreamdoesnotcontainanyofthecommandsorpacketinformationfoundintheconfigurationbitstreamandnoCRCcalculationisperformedduringreadback.ThereadbackdatastreamisshowninFigure6-3.X-RefTarget-Figure6-3ReadbackDataPadFrame1Frame(6516-BitWords)Type0-CLBFrameDataTotalNumberofDeviceFramesPadFrame(6516-BitWords)Type1-BlockRAMFrameDataPadFrame(116-BitWord)Type2-IOBFrameDataUG380_c6_03_062911Figure6-3:ReadbackDataStreamThereadbackdatastreamisverifiedbycomparingittotheoriginalconfigurationframedatathatwereprogrammedintothedevice.Certainbitswithinthereadbackdatastreammustnotbecompared,becausethesecancorrespondtousermemoryornullmemorylocations.Thelocationofdon'tcarebitsinthereadbackdatastreamisgivenbythemaskfiles(MSKandMSD).Thesefileshavedifferentformatsalthoughbothconveyessentiallythesameinformation.Oncereadbackdatahavebeenobtainedfromthedevice,eitherofthefollowingcomparisonprocedurescanbeused:1.ComparereadbackdatatotheRBDgoldenreadbackfile.MaskbyusingtheMSDfile(seeFigure6-4).ThesimplestwaytoverifythereadbackdatastreamistocompareittotheRBDgoldenreadbackfile,maskingreadbackbitswiththeMSDfile.Thisapproachissimplebecausethereisa1:1correspondencebetweenthestartofthereadbackdatastreamandthestartoftheRBDandMSDfiles,makingthetaskofaligningreadback,mask,andexpecteddataeasier.Spartan-6FPGAConfigurationUserGuideUG380(v2.11)March22,2019Chapter6:ReadbackandConfigurationVerificationSpartan-6FPGAConfigurationUserGuideUG380(v2.11)March22,2019Chapter7:ReconfigurationandMultiBootWatchdogTimerTheSpartan-6FPGAwatchdogtimerisusedtomonitordetectionofthesyncword.Whenthewatchdogtimertimesout,theconfigurationlogicincrementsthestrikecountandattemptstoreconfigureiftheBitGenoption-gReset_On_ErrisYesandthemaximumstrikelimithasnotbeenreached.TheFallbackMultiBootsectionprovidesmoredetails.Thewatchdogtimerusesthesameclocksourceastheconfigurationclock.ThewatchdogcounterlimitisconfigurablebysettingtheConfigurationWatchDogTimer(CWDT)registerorsettingtheBitGenoptionTIMER_CFG.Thedefaultis64kclockcycles,andtheminimumvalueis16h'0201.Thewatchdogtimercannotbedisabledbytheuser.Thewatchdogtimerisdisabledduringandafterfallbackreconfiguration.RequiredDataSpacingbetweenMultiBootImagesSpartan-6FPGAMultiBootaddressingisflexibleenoughtoallowabitstreamtobeginatanybyteboundary.However,thereareafewpracticallimitations,basedonspecificapplicationrequirements.FlashSector,Block,orPageBoundariesSpartan-6FPGAsloadMultiBootconfigurationimagesfromanexternalflash.Allflashmemorieshaveaninternalmemoryarchitecturethatarrangesthememoryintosectors,blocks,orpages.Nearlyallhavemultiplesectors.Somearchitecturesprovideadditionalgranularity,splittingasectorintosmallerblocks,orevensmallerstill,pages.Ideally,aSpartan-6FPGAMultiBootconfigurationimageshouldbealignedtoasector,block,orpageboundary.Thespecificrequirementdependsontheflasharchitecture.Ifthesmallesterasableelementintheflashisasector,thentheFPGAbitstreammustbealignedtoasectorboundary.Thisway,oneFPGAbitstreamcanbeupdatedwithoutaffectingothersintheflash.AdditionalMemorySpaceRequiredforLCK_CycleASpartan-6FPGAapplicationcancontainoneormoredigitalclockmanagers(DCMs)orphase-lockedloops(PLLs).TheLCK_CycleBitGensettingdeterminesif,duringconfiguration,theFPGAwaitsforalloftheclockelementstoacquireandlocktotheirrespectiveinputclockfrequencybeforeallowingtheFPGAtofinishtheconfigurationprocess.Thelocktime,whichisspecifiedinDS162,Spartan-6FPGADataSheet:DCandSwitchingCharacteristics,dependsontheDCMorPLLmode,andtheinputclockfrequency.EveniftheFPGAiswaitingforoneormoreclockelementstolockbeforecompletingconfiguration,theFPGA’sconfigurationcontrollercontinuessearchingforthenextsynchronizationword.IftwoadjacentMultiBootimagesareplacedwithoneimmediatelyfollowingtheotherandthefirstFPGAbitstreamcontainsaDCMorPLLwiththeLCK_Cycleoptionset,thenpotentialconfigurationproblemscanoccur.IfthecontrollerseesthesynchronizationwordinthesecondFPGAbitstreambeforecompletingthecurrentconfiguration,itstartsinterpretingdatafromthesecondbitstream.However,theFPGA’sconfigurationlogiccancompletethecurrentconfigurationeventhoughtheFPGAhasreaddatafromthesecondbitstream.Ifthisconditionappliestoadesign,sufficientspacingmustexistbetweenbitstreams.Spartan-6FPGAConfigurationUserGuideUG380(v2.11)March22,2019RequiredDataSpacingbetweenMultiBootImagesSpartan-6FPGAConfigurationUserGuideUG380(v2.11)March22,2019
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