布局布线流程

null深亚微米后端设计 流程 快递问题件怎么处理流程河南自建厂房流程下载关于规范招聘需求审批流程制作流程表下载邮件下载流程设计 深亚微米后端设计流程 许可敬 2009-12-21Digital Flow OverviewDigital Flow Overview准备工作准备工作工具准备 Soc-encounter Voltagestorm Celtic fire_ice virtuso Dracula or calibre primetime 文件准备 Verilog LEF LIB 时序约束文件 IO文件 DRC，LVS rule 文件 Library Exchange Format (LEF) Library Exchange Format (LEF) Timing libraryTiming librarycell (INVX1) {         cell_footprint : “inv”;         area : 36.000000;         cell_leakage_power : 6.883686e+01;         leakage_power () {             when : “A”;             value : “60.524918”;}         leakage_power () {             when : “!A”;             value : “68.836860”;}         pin (A) {             direction : “input”;}         pin (Y) {             direction : “output”;             function : “(!A)”;             max_capacitance : 0.510000;             internal_power () {                 related_pin : “A”;                 rise_power (“power_outputs_1”) { …;                 }                 fall_power (“power_outputs_1”) { ……“);                 }             }                         timing () {                 related_pin : ”A“;                 timing_type : ”combinational“;                 timing_sense : ”negative_unate“;                 cell_fall ("del_1_7_7") {                     index_1("0.05, 0.1, 0.3, 0.8, 1.3, 1.9, 2.6");                     index_2("0.0006, 0.03, 0.06, 0.15, 0.27, 0.39, 0.51");                     values("0.025, 0.088, 0.149, 0.333, 0.578, 0.827, 1.070", \                         "0.026, 0.096, 0.157, 0.340, 0.586, 0.835, 1.077", \                         "0.015, 0.118, 0.191, 0.373, 0.618, 0.860, 1.104", \                         "-0.031, 0.117, 0.221, 0.456, 0.706, 0.946, 1.187", \                         "-0.084, 0.092, 0.217, 0.496, 0.790, 1.040, 1.278", \                         "-0.153, 0.051, 0.193, 0.515, 0.849, 1.132, 1.389", \                         "-0.235, -0.006, 0.155, 0.517, 0.887, 1.207, 1.487");                 }                 fall_transition ("del_1_7_7") {                     index_1("0.05, 0.1, 0.3, 0.8, 1.3, 1.9, 2.6");                     index_2("0.0006, 0.03, 0.06, 0.15, 0.27, 0.39, 0.51");                     values("0.026, 0.118, 0.223, 0.518, 0.920, 1.332, 1.755", \                         "0.035, 0.120, 0.218, 0.518, 0.935, 1.345, 1.756", \                         "0.065, 0.173, 0.251, 0.519, 0.938, 1.321, 1.722", \                         "0.130, 0.291, 0.387, 0.632, 0.951, 1.322, 1.721", \                         "0.181, 0.382, 0.509, 0.784, 1.079, 1.391, 1.742", \                         "0.238, 0.485, 0.626, 0.930, 1.263, 1.566, 1.866", \                         "0.304, 0.595, 0.755, 1.109, 1.464, 1.790, 2.093");                 }            }        }    } 时序约束文件时序约束文件create-clock - period ＄EXTCL K- PERIOD - name exclk＄EXTCL K- PORT set-min-pulse-width [ expr 0. 4 3 ＄EXTCL K- PERIOD] [ getclocks exclk] set- drive 0 ＄EXTCL K- PORT set-clock- uncertainty ＄EXTCL K- SKEW [get-clocks exclk] set-clock-latency2source 1 exclk set-max- delay 502from [get-ports EXTRST- P] set-input- delay2max 22clock exclk [get-ports AASPE- P] ⋯ set-output- delay2max 12clock exclk [get-ports RPO 3 ] ⋯ create-clock2period ＄BUSCL K- PERIOD2name baclk [ get-ports BACL K- P] set-min-pulse-width [ expr 0. 4 3 ＄BUSCL K- PERIOD] [ getclocks baclk] set-propagated-clock baclk set- dont- touch- network [get-clocks baclk] ⋯ set-false-path from [get-clocks bdclk] to [get-clocks exclk] set- dont- touch- network Top-Core/ cpu-interface1/ reset-int Set_clock_gating_check –rise –setup 0.1 Set_clock_gating_check –rise –hold 0.2 IO location fileIO location fileVersion: 2 Offset: 19.4700 Pin: address[14] N 0.4200 0.2800 Offset: 39.2700 Pin: address[10] S 0.5600 0.2800soc encounter 一般流程soc encounter 一般流程Design After input Design After input Top-Level Implementation StepsTop-Level Implementation StepsRun timing analysis. Analyze timing with the Common Timing Engine (CTE) using zero net loading to determine whether the initial design meets timing requirements. Place I/O, power, and ground pads. If you provide an I/O assignment file, you are not required to specify the exact location of allI/O pads. Place JTAG (boundary scan)cells. Specify and place JTAG cells near the I/O cells. Once placed, they will not be moved in subsequent placement runs. Place the blocks in the design if you have an all-block. You can use the Encounter block placer or manually place blocks. Critical cell placement. we must plase some crital cell manually after “JTAG cell placement” this cell like the buffers. Power plan. Define the power rings and stripes. Top-Level Implementation StepsTop-Level Implementation StepsRun Amoeba placement. Use the Amoeba placer to place cells in the design. The placer places cells according to module guide and fence constraints. Running placement and analyzing the congestion lets you quickly gauge the feasibility of the design in meeting timing and placement density goals. Congestion Analysis Can evaluate the design’s congestion ,if its results can be acceptable, we can go to next step, othewise must re-do placement optimization. Reorder scan chains. Refine the initial scan-chain order based on Amoeba placement results. Although changes made at this step are not used after the initial floorplanning, this step is still recommended for reducing wire length for a more accurate analysis of congestion. Refine the initial scan-chain order based on the most recent Amoeba placement results. After place and power planAfter place and power planTop-Level Implementation StepsTop-Level Implementation StepsBuild clock tree Define clock tree constraints, such as insertion delay and skew limits. Synthesize the clock tree. Analyze the clock tree reports to determine if timing constraints have been met. At this stage, netlist changes are not passed forward. A clock tree is generated to determine clock and timing issues with the current floorplan. Run in-place optimization (IPO). Run in-place optimization, which adds buffer cells, resizes gates, and fixes design rule violations. Although netlist changes made at this stage are not kept, in-place optimization is necessary for assessing potential timing issues with the current floorplan. 静态时序分析静态时序分析静态时序分析技术是一种穷尽分析 方法 快递客服问题件处理详细方法山木方法pdf计算方法pdf华与华方法下载八字理论方法下载 ,用以衡量电路性能。它提取整个电路的所有时序路径,通过计算信号沿在路径上的延迟传播,找出违背时序约束的错误,主要是检查建立时间和保持时间是否满足 要求 对教师党员的评价套管和固井爆破片与爆破装置仓库管理基本要求三甲医院都需要复审吗 ,而它们又分别通过对最大路径延迟和最小路径延迟的分析得到。 Setup Timing Arc：定义序向组件（Sequential Cell，如Flip-Flop、Latch等）所需的Setup Time，依据Clock上升或下降分为2类。 Hold Timing Arc：定义序向组件所需的Hold Time，依据Clock上升或下降分为2类。Top-Level Implementation StepsTop-Level Implementation Steps Run trial routing. Use the trial router to route the design. Examine the congestion map and the report to identify congested areas. Use the prototyping option of Trial Route to gauge the routability of the design. Extract RCs. Fire & Ice QX Extraction—Creates Standard Parasitics Extraction File (SPEF). Analyze timing to find timing violations. Although timing at this stage is likely to have many violations, you can still discover useful information. Analyze the timing to determine how to alter the floorplan.Top-Level Implementation StepsTop-Level Implementation StepsAnalyzing Crosstalk Encounter uses either native or standalone CeltIC to perform crosstalk analysis. CeltIC calculates delay to cross-coupling effects on each net and produces delays in the form of a standard delay format (SDF) file. This delay is backannotated to Encounter to incorporate delay due to crosstalk effects. Encounter uses NanoRoute to repair noise-on-delay violations using the following techniques: wire spacing, net ordering, layer selection, minimization of long parallel wires, and shielding. Run power analysis. Assuming that the netlist is clean, use the Encounter engine to run a power analysis, and then use the VoltageStorm power analyzer to run an IR drop analysis. At this point, the block is essentially complete and the rest of the steps involve creating various representations of the block to use during top-level implementation and chip assembly.Top-Level Implementation StepsTop-Level Implementation StepsAdding Filler Cells You can add filler cells at the end of the design cycle to fill all the gaps between standard cell instances. Filler cells can also provide decoupling capacitance to complete the power connections in the standard cell rows and extend N-well and P-well regions. Outputs of Chip Assembly and Sign-off Top-level GDSII Verilog SPEFPhysical verificationPhysical verificationGDS导入 将布局布线输出的gds导入virtoso工具，给出对应工艺所需的map文件及标准单元的版图库 Label标注 VDD VSS 等其他电源一一标注 单独供电需手工处理 PLL PDIODE连接关系需手工加入 GDS导出 使用dracula or calibre验证 Physical verificationPhysical verificationDRC(design rule check) 设计 规则 编码规则下载淘宝规则下载天猫规则下载麻将竞赛规则pdf麻将竞赛规则pdf 检查 设计规则是集成电路版图各种几何图形尺寸的规范，drc是按设计规则对版图几何形状的宽度间距及层与层之间的相对位置等进行检查。 ERC(electrical rule check)电学规则检查 主要检查是否有短路开路和悬空的节点，以及与工艺有关的错误。 LVS(layout versus schematic)版图与电路图一致性比较 LVS 是把设计的版图和电路图进行对照和比较，要求两者达到完全一致。 ANT天线效应检查 这也是和电路制造过程有关的问题，为了防止太多的电子在铺金属层的过程中集中到导线上击穿栅极，必须保证同层的导线长度不能太长。解决天线效应问题有两种方法，一是在产生天线效应的走线上添加反向二极管，这样可以保护栅极；二是采用向更高层的金属进行跳线连接，这样在加工过程中就可以避免过多电子的积聚。 Dummy 插入 为了解决芯片制造时平坦度问题，必须在芯片layout设计时加入dummy pattern /cell Chip FinishingChip Finishing