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CC253x System-on-Chip Solution.pdf

CC253x System-on-Chip Solution.…

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简介:本文档为《CC253x System-on-Chip Solutionpdf》,可适用于电子通讯领域,主题内容包含CCxSystemonChipSolutionforGHzIEEEandZigBeeApplicationsACCSystemonChipSolut符等。

CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications A CC2540/41 System-on-Chip Solution for 2.4- GHz Bluetooth low energy Applications User's Guide Literature Number: SWRU191E April 2009–Revised January 2014 Contents Preface ...................................................................................................................................... 14 1 Introduction ...................................................................................................................... 17 1.1 Overview .................................................................................................................... 18 1.1.1 CPU and Memory ................................................................................................ 21 1.1.2 Clocks and Power Management ................................................................................ 21 1.1.3 Peripherals ........................................................................................................ 21 1.1.4 Radio ............................................................................................................... 23 1.2 Applications ................................................................................................................ 23 2 8051 CPU .......................................................................................................................... 24 2.1 8051 CPU Introduction .................................................................................................... 25 2.2 Memory ..................................................................................................................... 25 2.2.1 Memory Map ...................................................................................................... 25 2.2.2 CPU Memory Space ............................................................................................. 27 2.2.3 Physical Memory ................................................................................................. 28 2.2.4 XDATA Memory Access ......................................................................................... 33 2.2.5 Memory Arbiter ................................................................................................... 33 2.3 CPU Registers ............................................................................................................. 34 2.3.1 Data Pointers ...................................................................................................... 34 2.3.2 Registers R0–R7 ................................................................................................. 35 2.3.3 Program Status Word ............................................................................................ 35 2.3.4 Accumulator ....................................................................................................... 36 2.3.5 B Register ......................................................................................................... 36 2.3.6 Stack Pointer ...................................................................................................... 36 2.4 Instruction Set Summary ................................................................................................. 36 2.5 Interrupts .................................................................................................................... 40 2.5.1 Interrupt Masking ................................................................................................. 41 2.5.2 Interrupt Processing .............................................................................................. 45 2.5.3 Interrupt Priority ................................................................................................... 47 3 Debug Interface ................................................................................................................. 50 3.1 Debug Mode ............................................................................................................... 51 3.2 Debug Communication ................................................................................................... 51 3.3 Debug Commands ........................................................................................................ 53 3.3.1 Debug Configuration ............................................................................................. 55 3.3.2 Debug Status ...................................................................................................... 55 3.3.3 Hardware Breakpoints ........................................................................................... 56 3.4 Flash Programming ....................................................................................................... 57 3.4.1 Lock Bits ........................................................................................................... 57 3.5 Debug Interface and Power Modes ..................................................................................... 57 3.6 Registers .................................................................................................................... 59 4 Power Management and Clocks .......................................................................................... 60 4.1 Power Management Introduction ........................................................................................ 61 4.1.1 Active and Idle Modes ........................................................................................... 62 4.1.2 PM1 ................................................................................................................ 62 4.1.3 PM2 ................................................................................................................ 62 2 Contents SWRU191E–April 2009–Revised January 2014 Submit Documentation Feedback Copyright 2009–2014, Texas Instruments Incorporated www.ti.com 4.1.4 PM3 ................................................................................................................ 62 4.2 Power-Management Control ............................................................................................. 62 4.3 Power-Management Registers .......................................................................................... 63 4.4 Oscillators and Clocks .................................................................................................... 66 4.4.1 Oscillators ......................................................................................................... 66 4.4.2 System Clock ..................................................................................................... 66 4.4.3 32-kHz Oscillators ................................................................................................ 67 4.4.4 Oscillator and Clock Registers .................................................................................. 67 4.5 Timer Tick Generation .................................................................................................... 69 4.6 Data Retention ............................................................................................................. 69 5 Reset ............................................................................................................................... 70 5.1 Power-On Reset and Brownout Detector .............................................................................. 71 5.2 Clock-Loss Detector ....................................................................................................... 71 6 Flash Controller ................................................................................................................ 72 6.1 Flash Memory Organization .............................................................................................. 73 6.2 Flash Write ................................................................................................................. 73 6.2.1 Flash-Write Procedure ........................................................................................... 73 6.2.2 Writing Multiple Times to a Word ............................................................................... 74 6.2.3 DMA Flash Write ................................................................................................. 74 6.2.4 CPU Flash Write .................................................................................................. 75 6.3 Flash Page Erase ......................................................................................................... 75 6.3.1 Performing Flash Erase From Flash Memory ................................................................ 76 6.3.2 Different Flash Page Size on CC2533 ......................................................................... 76 6.4 Flash DMA Trigger ........................................................................................................ 76 6.5 Flash Controller Registers ................................................................................................ 76 7 I/O Ports ........................................................................................................................... 78 7.1 Unused I/O Pins ........................................................................................................... 79 7.2 Low I/O Supply Voltage ................................................................................................... 79 7.3 General-Purpose I/O ...................................................................................................... 79 7.4 General-Purpose I/O Interrupts .......................................................................................... 79 7.5 General-Purpose I/O DMA ............................................................................................... 80 7.6 Peripheral I/O .............................................................................................................. 80 7.6.1 Timer 1 ............................................................................................................. 81 7.6.2 Timer 3 ............................................................................................................. 81 7.6.3 Timer 4 ............................................................................................................. 82 7.6.4 USART 0 ........................................................................................................... 82 7.6.5 USART 1 ........................................................................................................... 82 7.6.6 ADC ................................................................................................................ 83 7.6.7 Operational Amplifier and Analog Comparator ............................................................... 83 7.7 Debug Interface ............................................................................................................ 83 7.8 32-kHz XOSC Input ....................................................................................................... 83 7.9 Radio Test Output Signals ............................................................................................... 84 7.10 Power-Down Signal MUX (PMUX) ...................................................................................... 84 7.11 I/O Registers ............................................................................................................... 84 8 DMA Controller ................................................................................................................. 92 8.1 DMA Operation ............................................................................................................ 93 8.2 DMA Configuration Parameters ......................................................................................... 95 8.2.1 Source Address ................................................................................................... 95 8.2.2 Destination Address .............................................................................................. 95 8.2.3 Transfer Count .................................................................................................... 95 8.2.4 VLEN Setting ...................................................................................................... 96 8.2.5 Trigger Event ...................................................................................................... 96 3SWRU191E–April 2009–Revised January 2014 Contents Submit Documentation Feedback Copyright 2009–2014, Texas Instruments Incorporated www.ti.com 8.2.6 Source and Destination Increment ............................................................................. 96 8.2.7 DMA Transfer Mode .............................................................................................. 97 8.2.8 DMA Priority ....................................................................................................... 97 8.2.9 Byte or Word Transfers .......................................................................................... 97 8.2.10 Interrupt Mask .................................................................................................... 97 8.2.11 Mode 8 Setting ................................................................................................... 97 8.3 DMA Configuration Setup ................................................................................................ 97 8.4 Stopping DMA Transfers ................................................................................................. 98 8.5 DMA Interrupts ............................................................................................................. 98 8.6 DMA Configuration-Data Structure ...................................................................................... 98 8.7 DMA Memory Access ..................................................................................................... 98 8.8 DMA Registers ........................................................................................................... 101 9 Timer 1 (16-Bit Timer) ....................................................................................................... 103 9.1 16-Bit Counter ............................................................................................................ 104 9.2 Timer 1 Operation ........................................................................................................ 104 9.3 Free-Running Mode ..................................................................................................... 104 9.4 Modulo Mode ............................................................................................................. 105 9.5 Up-and-Down Mode ..................................................................................................... 105 9.6 Channel-Mode Control .................................................................................................. 105 9.7 Input Capture Mode ..................................................................................................... 106 9.8 Output Compare Mode .................................................................................................. 106 9.9 IR Signal Generation and Learning .................................................................................... 111 9.9.1 Introduction ...................................................................................................... 111 9.9.2 Modulated Codes ............................................................................................... 111 9.9.3 Non-Modulated Codes ......................................................................................... 112 9.9.4 Learning .......................................................................................................... 113 9.9.5 Other Considerations ........................................................................................... 113 9.10 Timer 1 Interrupts ........................................................................................................ 113 9.11 Timer 1 DMA Triggers ................................................................................................... 113 9.12 Timer 1 Registers ........................................................................................................ 114 9.13 Accessing Timer 1 Registers as Array ................................................................................ 119 10 Timer 3 and Timer 4 (8-Bit Timers) ..................................................................................... 120 10.1 8-Bit Timer Counter ...................................................................................................... 121 10.2 Timer 3 and Timer 4 Mode Control .................................................................................... 121 10.2.1 Free-Running Mode ........................................................................................... 121 10.2.2 Down Mode ..................................................................................................... 121 10.2.3 Modulo Mode ................................................................................................... 121 10.2.4 Up-and-Down Mode ........................................................................................... 121 10.3 Channel Mode Control .................................................................................................. 121 10.4 Input Capture Mode ..................................................................................................... 122 10.5 Output Compare Mode .................................................................................................. 122 10.6 Timer 3 and Timer 4 Interrupts ......................................................................................... 122 10.7 Timer 3 and Timer 4 DMA Triggers ................................................................................... 123 10.8 Timer 3 and Timer 4 Registers ......................................................................................... 123 11 Sleep Timer ..................................................................................................................... 128 11.1 General .................................................................................................................... 129 11.2 Timer Compare ........................................................................................................... 129 11.3 Timer Capture ............................................................................................................ 129 11.4 Sleep Timer Registers ................................................................................................... 130 12 ADC ............................................................................................................................... 132 12.1 ADC Introduction ......................................................................................................... 133 12.2 ADC Operation ........................................................................................................... 133 4 Contents SWRU191E–April 2009–Revised January 2014 Submit Documentation Feedback Copyright 2009–2014, Texas Instruments Incorporated www.ti.com 12.2.1 ADC Inputs ...................................................................................................... 133 12.2.2 ADC Conversion Sequences ................................................................................. 134 12.2.3 Single ADC Conversion ....................................................................................... 1

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