6455_dsk_schematic

Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: B SPECTRUM DIGITAL INCORPORATED 508552-0001 Monday, March 06, 2006 1 34 B TMS320C6455 DSK Title Block SCHEMATIC CONTENTS: 1 COVER SHEET 2 USER OPTIONS 3 Clock Inputs 4 645X DDR2 Interface 5 DDR2 Memories 6 645X EMIF A 7 BOOT Options 8 CPLD 9 FLASH MEMORY 10 645X MII INTERFACE 11 MCBSP INTERFACE 12 645X HOST PORT INTERFACE 13 645X SRIO INTERFACE 14 DSK DAUGHTERCARD BUFFERS 15 DSK DAUGHTERCARD INTERFACE 16 645X POWER PINS I 17 645X POWER PINS II 18 645X EMULATION 19 645X EMULATION INTERFACE 20 EMULATION INTERFACE 21 HIERARCHICAL BLOCKS 22 645X RGMII INTERFACE 23 645X DECOUPLING CAPS I 24 645X DECOUPLING CAPS II 25 POWER INPUT 26 AIC23 CODEC 27 ETHERNET PHY 28 DSK POWER SUPPLIES I 29 DSK POWER SUPPLIES II A A A A A A A A DATE DATE DATE DATE RLSE ENGR-MGR USED ON QA DATE NEXT ASSY APPLICATION MFG CHK DATE ENGR DATE DWN R.R.P. R.R.P. T.M.K. C.M.D. R.R.P. J.T.C. SEPT 15,2005 SEPT 15,2005 SEPT 15,2005 SEPT 15,2005 SEPT 15,2005 SEPT 15,2005 SEPT 15,2005 C.M.D. REV SH REV SH SH REV 15 A 1 2 3 4 5 6 7 9 10 11 12 13 14 A A A A A A A A A A A A A A 16 17 18 19 20 21 23 24 25 26 27 28 29 8 A A A 22 A A A REVISION STATUS OF SHEETS B Beta Release RRP10/15/05 A Initial schematic ready for layout - Alpha Release DESCRIPTIONREV APPROVEDDATE 09/15/05 RRP 4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED CIRCUITS THEY SHOULD BE PLACED NEAR. NOTES, UNLESS OTHERWISE SPECIFIED: 1. RESISTANCE VALUES IN OHMS. 2. CAPACTITANCE VALUES IN MICROFARADS. 3. REFERENCE DESIGNATORS USED: 5. OBSERVE THE FOLLOWING LAYOUT NOTES: 6. BOARD PROPERTIES B. General layers 50 +/- 5 OHM MATCHED IMPEDANCE C. OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING D. INNER LAYERS 1.0 OZ CU E. FR4 BOARD MATERIAL F. MINIMUM TRACE WIDTH/SPACING 4 MILS G. MINIMUM VIA SIZE 10/19 MIL H. LAYER STACKUP: A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE DDR2 ROUTING PER APPLICATION NOTE SRIO ROUTING PER APPLICATION NOTE USER_LED1 USER_LED0 USER_LED3 USER_LED2 PWB_REV2 PWB_REV1 PWB_REV0 DSP_RSn_LED 3.3V DGND 3.3V DGND 3.3V DGND 3.3V DGND USER_LED28 USER_LED08 USER_LED18 USER_LED38 DSP_RSn_LED8 USER_SW3 8 USER_SW1 8 USER_SW0 8 USER_SW2 8 PWB_REV2 8 PWB_REV1 8 PWB_REV0 8 OPT_CLK1 8 Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: A SPECTRUM DIGITAL INCORPORATED 508552-0001 Wednesday, January 25, 2006 2 34 B TMS320C6455 DSK Title Block PADDLE SWITCH R79 150 R82 150 SW1 SW DIP-4/SM 1 2 3 4 8 7 6 5 R81 150 R80 150 D6 YELLOW L8 BLM21P221SN D7 GREEN D8 GREEN D9 GREEN RN25 RPACK4-10K 1 2 3 4 5 6 7 8 D10 GREEN R78 150 U29 8 MHz OFFn1 GND2 VCC 4 CLK 3 R404 100 C130 0.1uF R33 NO-POP R36 1K R37 1K R54 1K R34 NO-POP R53 NO-POP DSPA.CLKIN2 DSPA_EMIFA_CLK DSPA.CLKIN1 DSP_EMU13 DSP_EMU12 DSP_EMU14 DSP_EMU15 DSP_EMU16 DSP_EMU17 DSP_EMU18 DSP_EMU2 DSP_EMU5 DSP_EMU9 DSP_EMU3 DSP_EMU4 DSP_EMU6 DSP_EMU7 DSP_EMU8 DSP_EMU11 DSP_EMU10 DSP_EMU1 DSP_EMU0 DSPA_I2C_SDA DSPA_I2C_SCL DGND 3.3V DGND DGND DGND 3.3V 3.3V 3.3V DGND 3.3V DGND 3.3V DGND EMIF_PLL_CLK8 DSPA_EMIFA_CLK 6 CPU_PLL_CLK8 CPU_PLL_S08 CPU_PLL_S18 DSPA.GP0411 DSPA.GP0511 DSPA.GP0611 DSPA.GP0711 DSP_EMU1 19 DSP_EMU2 19 DSP_EMU3 19 DSP_EMU4 19 DSP_EMU5 19 DSP_EMU6 19 DSP_EMU7 19 DSP_EMU8 19 DSP_EMU9 19 DSP_EMU10 19 DSP_EMU11 19 DSP_EMU12 19 DSP_EMU13 19 DSP_EMU14 19 DSP_EMU18 19 DSP_EMU17 19 DSP_EMU16 19 DSP_EMU15 19 DSPA.TDO19,20 DSP_EMU0 19 DSPA_I2C_SCL 9,14,25 DSPA_I2C_SDA 9,14,25DSPA.RESETz8 DSPA.TDI19,20 DSPA.TMS19,20 DSPA.TRSTn19,20 HUR_TCK19,20 DSPA.CLKR111 DSPA.CLKX111 DSPA.DR111 DSPA.DX111 DSPA.FSR111 DSPA.FSX111 DSPA.TOUT0 11 DSPA.TOUT1 11 DSPA.TINP111 DSPA.TINP011 DSPA.RESETSTATn 8 DSPA.PORz8 HUR_TCKRTN19,20 Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: A SPECTRUM DIGITAL INCORPORATED 508552-0001 Monday, March 06, 2006 3 34 B TMS320C6455 DSK 6455 CLOCK INPUTS PLL2 -- X10 S1 S0 0 0 0 0 0 0 1 1 1 1 1 OPEN OPEN OPEN OPEN OPEN OPEN 1 100 MHz 125 MHz 133.25 MHz 62.5 MHz 50 MHz 83.25 MHz 150 MHz 75 MHz 200 MHz MULTIPLY OUTPUT 3X 5.33X 8X 2.5X 3.33X 6X 2X 4X 5X PLL1 -- X1 PLL1 -- X20 PLL1 -- X25 PLL1 -- X30 PLL1 -- X32 Run HUR_TCK to U10 ball and back as HUR_TCKRTN U30 ICS512 X1/CLK1 VDD2 GND3 REF4 CLK 5 S0 6 S1 7 X2 8 R95 NO-POP C133 0.1 C138 0.01 U28 25 MHz OFFn1 GND2 VCC 4 CLK 3 C126 NO-POP R405 33 R121 100 U10Ctmx320c6455ztz CLKR1/GP[0]AF4 EMU9 AH13 NMIAH4 EMU8 AF11 EMU7 AF12 EMU6 AG8 EMU5 AE12 CLKIN2G3 EMU4 AF9 CLKIN1N28 EMU3 AF10 EMU2 AG9 EMU1 AE11 EMU0 AF7 TRST*AH7 TDOAH8 TMSAJ10 GP[6]AG3 EMU18 AE13 EMU17 AH10 TDIAH9 EMU16 AH12 EMU15 AE9 EMU14 AF13 EMU13 AD8 EMU12 AE10 EMU11 AD12 EMU10 AD10 DR1/GP[8]AH5 FSR1/GP[10]AE5 POR*AF14 SDA AF26 CLKX1/GP[3]AF5 DX1/GP[9]AG5 TOUTL1L AG7 TOUTL0 AF8 GP[5]AJ2 TCKAJ9 RESET*AG14 FSX1/GP[11]AG4 SCL AG26 TINPL1AJ6 SYSCLK3/GP[1] AJ13 TINPL0AH6 RESETSTAT* AE14 GP[4]AH2 GP[7]AG2 C129 0.1uF C134 0.01 L10 Ferrite Chip R408 0 C137 0.1 R410 NO-POP R481 10K U31 ICS512 X1/CLK1 VDD2 GND3 REF4 CLK 5 S0 6 S1 7 X2 8 L9 Ferrite Chip R409 0 R412 33 R411 NO-POP L7 BLM21P221SN DSPA_TBECLKOUTP DSPA_TBECLKOUTN DSPA_TBEA10 DSPA_TBCEz DSPA_TBEA12 DSPA_TBEA13 DSPA_TBEA7 DSPA_TBEA8 DSPA_TBEA1 DSPA_TBEA2 DSPA_TBEA11 DSPA_GATE0_1 DSPA_GATE2_3 DSPA_TBSDCASz DSPA_TBEA6 DSPA_TBEA5 DSPA_TBEA4 DSPA_TBEA3 DSPA_TBEA0 DSPA_TBEA9 DSPA_TBSDCKEz DSPA_TBSDWEz DSPA_TBBA2 DSPA_TBBA1 DSPA_TBSDRASz DSPA_TBBA0 DSPA_TBSDDQM2 DSPA_TBSDDQM3 DSPA_TBSDDQM0 DSPA_TBSDDQM1 DSPA_TBED24 DSPA_TBED25 DSPA_TBED26 DSPA_TBED27 DSPA_TBED28 DSPA_TBED29 DSPA_TBED30 DSPA_TBED31 DSPA_TBED16 DSPA_TBED17 DSPA_TBED18 DSPA_TBED19 DSPA_TBED20 DSPA_TBED21 DSPA_TBED22 DSPA_TBED23 DSPA_TBED0 DSPA_TBED10 DSPA_TBED11 DSPA_TBED12 DSPA_TBED13 DSPA_TBED14 DSPA_TBED15 DSPA_TBED1 DSPA_TBED2 DSPA_TBED3 DSPA_TBED4 DSPA_TBED5 DSPA_TBED6 DSPA_TBED7 DSPA_TBED8 DSPA_TBED9 DSPA_TBED[0:31] DSPA_TBBA[0:2] 5 DSPA_TBCEz 5 DSPA_TBSDCASz 5 DSPA_TBSDWEz 5 DSPA_TBSDCKEz 5 DSPA_TBECLKOUTP 5 DSPA_TBECLKOUTN 5 DSPA_TBEA[0:13] 5 DSPA_TBSDRASz 5 DSPA_TBDDQM0 5 DSPA_TBDDQM1 5 DSPA_TBDDQM2 5 DSPA_TBDDQM3 5 DSPA_TBSDDQS0P5 DSPA_TBSDDQS3N5 DSPA_TBSDDQS1P5 DSPA_TBSDDQS2P5 DSPA_TBSDDQS3P5 DSPA_TBSDDQS0N5 DSPA_TBSDDQS1N5 DSPA_TBSDDQS2N5 DSPA_TBED[0:31] 5 Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: A SPECTRUM DIGITAL INCORPORATED 508552-0001 Wednesday, January 25, 2006 4 34 B TMS320C6455 DSK 6455 DDR Interface NOTE: Route DUT_BSDDQGATE0 signals needs to run to DDR memories near D15-D0 and back to DUT_TBSDDQGATE1. NOTE: Route DUT_BSDDQGATE2 signals needs to run to DDR memories near D31-D16 and back to DUT_TBSDDQGATE3. U10Btmx320c6455ztz DSDRAS* C13 DED21 B21 DED20 A21 DEA9 C16 DEA8 D16 DED9 D9 DEA7 B17 DEA6 C17 DED8 C9 DEA5 D17 DED7 D10 DEA4 E17 DED6 C10 DEA3 A18 DED5 B10 DEA2 B18 DED4 A10 DED3 D12 DEA1 C18 DEA0 D18 DED2 C12 DSDDQS1*D8 DED1 B12 DED0 A12 DSDWE* B13 DED19 D19 DSDDQGATE3F21 DED18 C19 DSDDQGATE2E21 DSDDQM3 C23 DSDDQGATE1B9 DED17 A19 DDR2CLKOUT* A14 DSDDQM2 C20 DSDDQGATE0A9 DED16 B19 DSDDQM1 C8 DED15 C7 DED14 D7 DSDDQM0 C11 DSDCKE D14 DSDDQS3E23 DED13 A7 DSDDQS2E20 DED12 B7 DED11 F9 DSDDQS1E8 DED10 E9 DSDDQS0E11 DDR2CLKOUT B14 DBA2 E15 DBA1 D15 DSDDQS0*D11 DBA0 C15 DSDDQS3*D23 DEA13 B15 DEA12 A15 DEA11 A16 DED31 B25 DEA10 B16 DED30 A25 DCE0* E14 DEODT1 A17 DEODT0 E16 DSDCAS* D13 DSDDQS2*D20 DED29 B24 DED28 A24 DED27 D22 DED26 C22 DED25 B22 DED24 A22 DED23 D21 DED22 C21 DSPA_TBEA[0:13] DSPA_TBBA[0:2] DSPA_TBSDDQS1P DSPA_TBSDDQS0N DSPA_TBSDDQS0P DSPA_TBSDDQS3N DSPA_TBSDDQS2P DSPA_TBSDDQS2N DSPA_TBSDDQS3P DSPA_TBSDDQS1N DSPA_TBDDQM2 DSPA_TBDDQM3 DSPA_TBDDQM1 DSPA_TBEA9 DSPA_TBEA2 DSPA_TBEA11 DSPA_TBSDCASz DSPA_TBEA7 DSPA_TBEA4 DSPA_TBEA10 DSPA_TBEA1 DSPA_TBCEz DSPA_TBSDWEz DSPA_TBEA8 DSPA_TBSDCKEz DSPA_TBECLKOUTN DSPA_TBEA2 DSPA_TBEA9 DSPA_TBEA3 DSPA_TBEA1 DSPA_TBBA1 DSPA_TBBA2 DSPA_TBSDRASz D S P A _ T B B A [ 0 : 2 ] DSPA_TBEA7 DSPA_TBEA10 DSPA_TBEA6 DSPA_TBEA0 DSPA_TBEA12 DSPA_TBEA6 DSPA_TBEA0 DSPA_TBEA5 DSPA_TBBA0 DSPA_TBEA3 DSPA_TBBA1 DSPA_TBEA11 DSPA_TBBA2 DSPA_TBEA12 DSPA_TBEA4 DSPA_TBDDQM0 DSPA_TBECLKOUTP DSPA_TBEA8 DSPA_TBEA5 DSPA_TBBA0 DSPA_TBED31 DSPA_TBED7 DSPA_TBED21 DSPA_TBED16 DSPA_TBED3 DSPA_TBED15 DSPA_TBED17 DSPA_TBED26 DSPA_TBED19 DSPA_TBED28 DSPA_TBED14 DSPA_TBED4 DSPA_TBED9 DSPA_TBED13 DSPA_TBED18 DSPA_TBED5 DSPA_TBED12 DSPA_TBED8 DSPA_TBED1 DSPA_TBED29 DSPA_TBED25 DSPA_TBED11 DSPA_TBED24 DSPA_TBED20 DSPA_TBED22DSPA_TBED6 DSPA_TBED27 DSPA_TBED2 DSPA_TBED[0:31] DSPA_TBED0 DSPA_TBED23 DSPA_TBED10 DSPA_TBED[0:31] D S P A _TB E D [0:31] DSPA_TBED30 D S P A _TB E D [0:31] DSPA_VREFSSTL DSPA_VREFSSTL DGND DGND DGND DGND DGND DVDD_1.8V DVDD_1.8V DVDD_1.8V DVDD_1.8V DVDD_1.8V DGND DGND DGND DGND DSPA_TBED[0:31] 4 DSPA_TBDDQM3 4 DSPA_TBSDDQS2P 4 DSPA_TBDDQM2 4 DSPA_TBEA[0:13] 4 DSPA_TBBA[0:2] 4 DSPA_TBDDQM04 DSPA_TBDDQM14 DSPA_TBSDDQS0P4 DSPA_TBSDCKEz4 DSPA_TBSDWEz4 DSPA_TBSDDQS0N4 DSPA_TBSDDQS1P4 DSPA_TBSDDQS1N4 DSPA_TBSDDQS2N 4 DSPA_TBSDDQS3N 4 DSPA_TBSDDQS3P 4 DSPA_TBSDRASz4 DSPA_TBSDCASz4 DSPA_TBCEz4 DSPA_VREFSSTL17 DSPA_TBECLKOUTP4 DSPA_TBECLKOUTN4 DSPA_TBED[0:31] 4 Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: A SPECTRUM DIGITAL INCORPORATED 508552-0001 Monday, March 06, 2006 5 34 B TMS320C6455 DSK DDR2 Memory Note 4.1: All R and RN components on this page should be placed close to U32/U33 C154 0.1uF C148 560pF C42 0.1uF R413 1K 1% C156 560pF C142 0.1uFC152 0.1uF R414 1K 1% C146 560pF C41 0.1uF + C150 33uF C147 560pF C139 0.1uF C149 560pF R20 0 U32 MT47H64M16BT NC10 A1 NC9 A2 NC8 A8 NC7 A9 VDD4D1 NC5 D2 VSS4D3 VSSQ3D7 UDQS#/NU D8 VDDQ7D9 DQ14E1 VSSQ5E2 UDM E3 UDQS E7 VSSQ8E8 DQ15E9 VDDQ8F1 DQ9F2 VDDQ1F3 VDDQ2F7 DQ8F8 VDDQ9F9 DQ12G1 VSSQ10G2 DQ11G3 DQ10G7 VSSQ1G8 DQ13G9 VDD2H1 NC11 H2 VSS3H3 VSSQ9H7 LDQS#/NU H8 VDDQ10H9 DQ6J1 VSSQ4J2 LDM J3 LDQS J7 VSSQ2J8 DQ7J9 VDDQ3K1 DQ1K2 VDDQ4K3 VDDQ5K7 DQ0K8 VDDQ6K9 DQ4L1 VSSQ7L2 DQ3L3 DQ2L7 VSSQ6L8 DQ5L9 VDDLM1 VREFM2 VSS5M3 VSSDLM7 CK M8 VDD1M9 CKE N2 WE# N3 RAS# N7 CK# N8 ODT N9 BA2 P1 BA0 P2 BA1 P3 CAS# P7 CS# P8 A10 R2 A1 R3 A2 R7 A0 R8 VDD3R9 VSS2T1 A3 T2 A5 T3 A6 T7 A4 T8 A7 U2 A9 U3 A11 U7 A8 U8 VSS1U9 VDD5V1 A12 V2 RFU1 V3 RFU2 V7 NC6 V8 NC4 AA1 NC3 AA2 NC2 AA8 NC1 AA9 C158 560pF C140 0.1uF C144 0.1uF C143 0.1uFC151 0.1uF U33 MT47H64M16BT NC10A1 NC9A2 NC8A8 NC7A9 VDD4 D1 NC5D2 VSS4 D3 VSSQ3 D7UDQS#/NUD8 VDDQ7 D9 DQ14 E1 VSSQ5 E2 UDME3 UDQSE7 VSSQ8 E8 DQ15 E9 VDDQ8 F1 DQ9 F2 VDDQ1 F3 VDDQ2 F7 DQ8 F8 VDDQ9 F9 DQ12 G1 VSSQ10 G2 DQ11 G3 DQ10 G7 VSSQ1 G8 DQ13 G9 VDD2 H1 NC11H2 VSS3 H3 VSSQ9 H7 LDQS#/NUH8 VDDQ10 H9 DQ6 J1 VSSQ4 J2 LDMJ3 LDQSJ7 VSSQ2 J8 DQ7 J9 VDDQ3 K1 DQ1 K2 VDDQ4 K3 VDDQ5 K7 DQ0 K8 VDDQ6 K9 DQ4 L1 VSSQ7 L2 DQ3 L3 DQ2 L7 VSSQ6 L8 DQ5 L9 VDDL M1 VREF M2 VSS5 M3 VSSDL M7 CKM8 VDD1 M9 CKEN2 WE#N3 RAS#N7 CK#N8 ODTN9 BA2P1 BA0P2 BA1P3 CAS#P7 CS#P8 A10R2 A1R3 A2R7 A0R8 VDD3 R9 VSS2 T1 A3T2 A5T3 A6T7 A4T8 A7U2 A9U3 A11U7 A8U8 VSS1 U9 VDD5 V1 A12V2 RFU1V3 RFU2V7 NC6V8 NC4AA1 NC3AA2 NC2AA8 NC1AA9 C157 560pF C155 560pF C153 0.1uF R21 0 C145 0.1uF DSPA_TAE0 DSPA_TAE1 DSPA_TAE2 DSPA_TAE3 DSPA_TAE4 DSPA_TAE5 DSPA_TAE6 DSPA_TAE7 DSPA_TAE16 DSPA_TAE17 DSPA_TAE18 DSPA_TAE19 DSPA_TAE8 DSPA_TAE9 DSPA_TAE10 DSPA_TAE11 DSPA_TAE12 DSPA_TAE13 DSPA_TAE14 DSPA_TAE15 ABE0n ABE1n ABE2n ABE3n DSPA_TAAWEz DSPA_TABE3z DSPA_TABE2z DSPA_TABE1z DSPA_TABE0z DSPA_TAAOEz DSPA_ARNW DSPA_AECLKOUT DSPA_TAED2 DSPA_TAED3 DSPA_TAED0 DSPA_TAED1 DSPA_TAED5 DSPA_TAED4 DSPA_TAED7 DSPA_TAED6 DSPA_TAED8 DSPA_TAED12 DSPA_TAED11 DSPA_TAED10 DSPA_TAED9 DSPA_TAED14 DSPA_TAED13 DSPA_TAED15 DSPA_TAED16 DSPA_TAED18 DSPA_TAED17 DSPA_TAED21 DSPA_TAED19 DSPA_TAED22 DSPA_TAED23 DSPA_TAED20 DSPA_TAED24 DSPA_TAED29 DSPA_TAED26 DSPA_TAED27 DSPA_TAED28 DSPA_TAED25 DSPA_TAED30 DSPA_TAED31 DSPA_AED0 DSPA_AED1 DSPA_AED2 DSPA_AED3 DSPA_AED4 DSPA_AED5 DSPA_AED6 DSPA_AED7 DSPA_AED8 DSPA_AED9 DSPA_AED10 DSPA_AED11 DSPA_AED12 DSPA_AED13 DSPA_AED14 DSPA_AED15 DSPA_AED16 DSPA_AED17 DSPA_AED18 DSPA_AED19 DSPA_AED20 DSPA_AED21 DSPA_AED22 DSPA_AED23 DSPA_AED24 DSPA_AED25 DSPA_AED26 DSPA_AED27 DSPA_AED28 DSPA_AED29 DSPA_AED30 DSPA_AED31 DSPA_EMIFA_CLK 3.3V DSPA_TAE[0:19] 7,8,9,15 DSPA_TAAOEz 8,9,15 DSPA_TAAWEz 8,9,15 DSPA_ARNW 8,15 DSPA_AECLKOUT 16 DSPA_TABA1 7,8,9 DSPA_TABA0 7,8,9 DSPA_TAED[0:31]8,9,15 DSPA_EMIFA_CLK3 DSPA_TABE3z 15 DSPA_TABE2z 15 DSPA_TABE1z 15 DSPA_TABE0z 15 DSPA_TACE5z 8,15 DSPA_TACE2z 8 DSPA_TACE4z 8,15 DSPA_TACE3z 8,9 DSPA_AARDYz15 Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: A SPECTRUM DIGITAL INCORPORATED 508552-0001 Wednesday, January 25, 2006 6 34 B TMS320C6455 DSK 6455 Emif A Interface R58 33 R425 10K RN33RPACK8-10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 U10Atmx320c6455ztz AED29AB29 AED28AC27 AED27AB28 AED26AC26 AED25AB27 AED24AC25 AED23AB26 AED22AD28 AED21AD29 AED20AJ28 ABA1/EMIFA_EN V25 AHOLD*R29 AR/W* W25 ASADS*/ASRE* R26 AAOE*/ASOE* Y28 AEA4/SYSCLKOUT_EN T28 ABE1* AA25 AEA6/PCI66 U27 ABE7* W29 ABA0/DDR2_EN V26 AED19AF29 AED18AH28 AED17AE29 AED16AG28 AED15AF28 AED14AH26 AED9AG27 AED13AE28 AED8AD27 AED12AE26 AED7AE25 AED11AD26 AEA14/HPI_WIDTH R25 AED6AJ27 AED10AF27 AED5AJ26 AED4AE27 AEA2/CFGGP2 T26 AED3AG25 AED2AH27 AED1AF25 AED0AD25 ABE0* AA26 AEA11 T25 AEA8/PCI_EEAI P25 ABE6* K26 AEA0/CFGGP0 U25 AEA18/BOOTMODE2 L26 AARDYK29 AECLKOUT V29 AED63F25 AED62A27 AED61C27 AED60C28 ABE5* L29 ACE5* V27 AEA5/MCBSP1_EN U28 AED59E27 AED58D28 AED57D27 AED56F27 AEA16/BOOTMODE0 P26 AED55G25 AED54G26 AED53A28 AED52F28 AED51B28 AED50G27 AEA10/MACSEL1 M25 AAWE*/ASWE* AB25 ABE4* L28 ACE4* V28 AED49B27 AED48G28 AED47H25 AEA7 N27 AED46J26 ABUSREQ L27 AED45H26 AED44J27 AEA15/AECLKIN_SEL P27 AED43H27 AEA3 T27 AED42J28 AED41C29 AED40J29 AEA19/BOOTMODE3 N25 AEA1/CFGGP1 U26 ABE3* AA29 ACE3* W26 AED39D29 AED38J25 AED37F29 AED36F26 AED35G29 AED34K28 AED33K25 AED32K27 AED31AA27 AHOLDA* N26 AED30AG29 AEA13/LENDIAN R27 AECLKIN*N29 AEA17/BOOTMODE1 L25 ABE2* AA28 AEA9/MACSEL0 M27 AEA12/UTOPIA_EN R28 ACE2* W27 RN40 RPACK8-101 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RN38 RPACK8-10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R102 33 R424 10K R62 33 R103 33 RN35RPACK8-10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RN41 RPACK4-221 2 3 45 6 7 8 R61 33 RN39 RPACK8-101 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RN37RPACK8-10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RN36 RPACK4-22 1 2 3 45 6 7 8 RN34 RPACK4-22 1 2 3 45 6 7 8 R423 33 DSPA_TAE17 DSPA.BOOT2 DSPA_TAE18 DSPA.BOOT3 DSPA_TAE19 DSPA_TAE13 DSPA_TAE13 DSPA_TAE0 DSPA_TAE5 DSPA_TAE11 DSPA_TAE7 DSPA_TAE14 DSPA_TAE12 DSPA_TAE19 DSPA_TAE1 DSPA_TAE9 DSPA_TAE15 DSPA_TAE10 DSPA_TAE4 DSPA_TAE6 DSPA_TAE2 DSPA.BOOT0 DSPA.BOOT1 DSPA_TAE16 DSPA.ENDIAN DSPA_TAE3 DSPA_TAE8 DSPA_TAE16 DSPA_TAE17 DSPA_TAE18 DGND DGND DGND 3.3V DGND DGND 3.3V DGND 3.3V DGND DGND 3.3V DGND 3.3V 3.3V 3.3V 3.3V 3.3V DGND DSPA_TAE[0:19]6,8,9,15 DSP_PLL_SELECT1 8 DSP_PLL_SELECT2 8 DSP_PLL_SELECT3 8 DSPA_TABA16,8,9 DSPA_TABA06,8,9 Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: B SPECTRUM DIGITAL INCORPORATED 508552-0001 Wednesday, January 25, 2006 7 34 B TMS320C6455 DSK Boot Options LIL_ENDIAN AECLKIN_SEL HPI_WIDTH PCI_EEAI UTOPIA_EN BOOT_MODE3 BOOT_MODE2 BOOT_MODE1 BOOT_MODE0 MAC_SEL1 MAC_SEL0 OFF - OPEN ON - CLOSED ENDIAN BOOT-X BOOT-X BOOT-X BOOT-X RESERVED1 RESERVED2 PCI FREQ MCBSP1 GPIO1 RESERVED3 CFGGP2 CFGGP1 CFGGP0 DDR ENABLED EMIFA ENABLED AE19AE18AE17AE16AE15AE14AE13AE12AE11AE10AE9AE8AE7AE6AE5AE4AE3AE2AE1ABA1ABA0 AE0 ABA0 ABA1 AE0 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE14 AE15 R452 1K R467 1K R42 1K R465 1K R444 NO-POP R447 2.2K R439 NO-POP R472 1K R435 NO-POP R454 NO-POP C36 0.1 R451 1K R434 1K R430 NO-POP R457 1K U39B 74LCBTLV125PWR 5 6 4 R460 1K R441 NO-POP U39A 74LCBTLV125PWR 2 3 1 1 4 7 R473 1K R433 1K R428 1K R437 NO-POP R440 1K R448 2.2K R438 NO-POP R462 NO-POP R471 1K R445 2.2K R432 1K R436 NO-POP R458 1K R429 NO-POP U40 SN74CBTLV1G125DCKR 3 4 5 2 1 R463 1K R427 1K R442 NO-POP R466 1K R46 1K R431 NO-POP R470 10K R469 10K SW3 SW DIP-8/SM 1 2 3 4 16 7 6 5 8 15 14 13 12 11 10 9 U39D 74LCBTLV125PWR 12 11 1 3 R450 NO-POP R43 1K R45 1K R459 1K R443 1K R456 NO-POP R461 1K R468 10K R44 1K R453 1K C37 0.1 R464 NO-POP R449 NO-POP R455 NO-POP U39C 74LCBTLV125PWR 9 8 1 0 R446 2.2K USB_DSP_RSTn DSPA.RESETz DC_EMIFA_OE# BRD_RST# USER_LED1 USER_LED0 USER_LED3 USER_LED2 ISR_TCK ISR_TMS ISR_TDI ISR_TDO PUSHB_RS DSPA_TAE2 DSP_RSn_LED DC_STAT0 DC_STAT1 DSPA_TAED2 DSPA_TAE0 DSPA_TAE1 PWB_REV2 PWB_REV1 DSPA_TAE3 PWB_REV0 DSPA_TAED3 DSPA_TAED5 DSPA_TAED7 DSPA_TAED1 DSPA_TAED4 DSPA_TAED6 DSPA_TAED5 DSPA_TAED1 DSPA_TAED7 DSPA_TAED3 DSPA_TAED6 DSPA_TAED4 DSPA_TAED2 DSPA_TAED0 DSPA_TAED0 DSPA_TAE3 DSPA_TAE2 USB_DSP_RSTn HURRICANE_RSTn ISR_TCK ISR_TDO ISR_TMS ISR_TDI ISR_TCK ISR_TMS ISR_TDO DSPA_TAE0 DSPA_TAE1 DSPA.RESETSTATn 3.3V DGND DGND 3.3V DGND DGND 3.3V 3.3V DGND HPI_RESET#12 DSPA_ARNW 6,15 DSPA_TAE[0:19]6,7,9,15 DC_STAT0 16 DC_STAT116 DC_CNTL016 DC_CNTL116 DC_EMIFA_OE# 15 DC_EMIFA_DIR15 DC_CNTL_OE#15,16 DC_RST#16 DC_DET 16 CPLD_MCBSP1_MUX11 BRD_RST#9 CODEC_CLK21 PUSHB_RS24 USER_SW0 2USER_SW12 USER_SW22 USER_SW32 DSPA_TAAWEz6,9,15 PWB_REV2 2 PWB_REV1 2 PWB_REV0 2 USER_LED2 2 USER_LED32 USER_LED12 USER_LED02 DSP_RSn_LED2 OPT_CLK1 2 DSPA_TAAOEz 6,9,15 DSPA_TAED[0:31]6,9,15 DSP_PLL_SELECT1 7 DSP_PLL_SELECT3 7 DSP_PLL_SELECT2 7 DSPA_TACE3z 6,9 DSPA_TACE2z 6 DSPA_TACE5z 6,15 DSPA_TACE4z 6,15 EMIF_PLL_CLK 3 CPU_PLL_S0 3 CPU_PLL_S1 3 CPU_PLL_CLK 3 MII_RESETz26 DSPA.RESETSTATn3 HURRICANE_RSTn 19 SVS_RSTn 32,34 USB_DSP_RSTn 32 DSPA.RESETz3 DSPA.PORz3 BD_PWR_ON_RSz 27 CPUB.PRESENTn 14,20 CPUB.RESETn 14 DSPA_TABA06,7,9 DSPA_TABA16,7,9 Size: Date: DWG NO Revision: Sheet o f Title: Page Contents: B SPECTRUM DIGITAL INCORPORATED 508552-0001 Wednesday, January 25, 2006 8 34 B TMS320C6455 DSK CPLD INTERFACE PULLUP/DOWN TO KEEP LOGIC IN RESET WHEN THE CPLD IS NOT PROGRAMMED. C69 0.1 C68 0.1 U12 EPM3128ATC100 PIN1 1 PIN2 2 V C C I O 1 3 TDI4 PIN5 5 PIN6 6 PIN7 7 PIN8 8 PIN9 9 PIN10 10 G N D I O 1 1 1 PIN12 12 PIN13 13 PIN14 14 TMS15 PIN16 16 PIN17 17 V C C I O 2 1 8 PIN19 19 PIN20 20 PIN21 21 PIN22 22 PIN23 23 PIN24 24 PIN25 25 G N D I O 2 2 6 PIN26 27 PIN28 28 PIN29 29 PIN30 30 PIN31 31 PIN32 32 G N D I O 3 3 3 V C C I O 3 3 4 PIN35 35 PIN36 36 PIN37 37 G N D I N T 1 3 8 V C C I N T 1 3 9 PIN40 40 PIN41 41 PIN42 42 G N D I O 4 4 3 PIN44 44 PIN45 45 PIN46 46 PIN47 47 PIN48 48 PIN49 49 PIN50 50 V C C I O 4 5 1 PIN5252 G N D I O 5 5 3 PIN5454 PIN5555 PIN5656 PIN5757 PIN5858 G N D I O 6 5 9 PIN6060 PIN6161 TCK62 PIN6363 PIN6464 G N D I O 7 6 5 V C C I O 5 6 6 PIN6767 PIN6868 PIN6969 PIN7070 PIN7171 PIN7272 TDO 73 G N D I O 8 7 4 PIN7575 PIN7676 PIN7777 G N D I O 9 7 8 PIN7979 PIN8080 PIN8181 V C C I O 6 8 2 PIN8383 PIN8484 PIN8585 G N D I N T 2 8 6 IN/GCLK187 IN/OE188 IN/GCLR89 IN/OE2/GCLK290 V C C I N T 2 9 1 PIN9292 PIN9393 PIN9494 G N D I O 1 0 9 5 PIN9696 PIN9