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uart_r1p5.pdf

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PrimeCell UART (PL011) Revision: r1p5 Technical Reference Manual Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G PrimeCell UART (PL011) Technical Reference Manual Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. Release Information The Change history table lists the changes made to this manual. Proprietary Notice Words and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Change history Date Issue Confidentiality Change 12 July 2000 A Open Access First release. 18 August 2000 B Open Access Change to signal names in Fig 2-1, changes to bits in Figs 4-1, 4-3. 9 February 2001 C Open Access Change to Figure 2-7. Note added to para 3.3.6. 15 February 2001 D Open Access Text change to pages 2-9, and 2-12. 14 December 2001 E Open Access Text changes to pages 3-13, 3-14, and 3-17. 01 November 2005 F Non-confidential Update to add Errata 01, history of product revision, fix for defect 326409. 18 December 2007 G Non-confidential Update for r1p5. Text changes to Clock signals on page 2-10 and UARTTXINTR on page 2-23. Buffer depth of the receive and transmit FIFOs increased. ii Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G Product Status The information in this document is final, that is for a developed product. Web Address http://www.arm.com ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. iii iv Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G Contents PrimeCell UART (PL011) Technical Reference Manual Preface About this manual ......................................................................................... xii Feedback ..................................................................................................... xvi Chapter 1 Introduction 1.1 About the UART .......................................................................................... 1-2 1.2 Product revisions ........................................................................................ 1-5 Chapter 2 Functional Overview 2.1 Overview ..................................................................................................... 2-2 ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. v 2.2 Functional description ................................................................................. 2-4 2.3 IrDA SIR ENDEC functional description ...................................................... 2-8 2.4 Operation .................................................................................................. 2-10 2.5 UART modem operation ........................................................................... 2-16 2.6 UART hardware flow control ..................................................................... 2-17 2.7 UART DMA interface ................................................................................. 2-19 2.8 Interrupts ................................................................................................... 2-22 Chapter 3 Programmers Model 3.1 About the programmers model .................................................................... 3-2 Contents 3.2 Summary of registers ................................................................................. 3-3 3.3 Register descriptions .................................................................................. 3-5 Chapter 4 Programmers Model for Test 4.1 Test harness overview ................................................................................ 4-2 4.2 Scan testing ................................................................................................ 4-3 4.3 Summary of test registers ........................................................................... 4-4 4.4 Test register descriptions ........................................................................... 4-5 4.5 Integration testing of block inputs ............................................................... 4-9 4.6 Integration testing of block outputs ........................................................... 4-11 4.7 Integration test summary .......................................................................... 4-14 Appendix A Signal Descriptions A.1 AMBA APB signals ..................................................................................... A-2 A.2 On-chip signals ........................................................................................... A-3 A.3 Signals to pads ........................................................................................... A-5 vi Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G List of Tables PrimeCell UART (PL011) Technical Reference Manual Change history .............................................................................................................. ii Table 2-1 Receive FIFO bit functions ...................................................................................... 2-13 Table 2-2 Function of the modem input/output signals in DTE and DCE modes .................... 2-16 Table 2-3 Control bits to enable and disable hardware flow control ........................................ 2-17 Table 2-4 DMA trigger points for the transmit and receive FIFOs ........................................... 2-21 Table 3-1 UART register summary ............................................................................................ 3-3 Table 3-2 UARTDR Register ..................................................................................................... 3-6 Table 3-3 UARTRSR/UARTECR Register ................................................................................ 3-7 Table 3-4 UARTFR Register ..................................................................................................... 3-8 Table 3-5 UARTILPR Register .................................................................................................. 3-9 Table 3-6 UARTIBRD Register ................................................................................................. 3-9 ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. vii Table 3-7 UARTFBRD Register .............................................................................................. 3-10 Table 3-8 Typical baud rates and integer divisors when UARTCLK=7.3728MHz .................. 3-11 Table 3-9 Integer and fractional divisors for typical baud rates when UARTCLK=4MHz ....... 3-12 Table 3-10 UARTLCR_H Register ............................................................................................ 3-13 Table 3-11 Parity truth table ...................................................................................................... 3-14 Table 3-12 UARTCR Register ................................................................................................... 3-15 Table 3-13 UARTIFLS Register ................................................................................................ 3-17 Table 3-14 UARTIMSC Register ............................................................................................... 3-18 Table 3-15 UARTRIS Register .................................................................................................. 3-19 Table 3-16 UARTMIS Register .................................................................................................. 3-20 List of Tables Table 3-17 UARTICR Register ................................................................................................. 3-21 Table 3-18 UARTDMACR Register .......................................................................................... 3-22 Table 3-19 UARTPeriphID0 Register ........................................................................................ 3-23 Table 3-20 UARTPeriphID1 Register ........................................................................................ 3-24 Table 3-21 UARTPeriphID2 Register ........................................................................................ 3-24 Table 3-22 UARTPeriphID3 Register ........................................................................................ 3-25 Table 3-23 UARTPCellID0 Register ......................................................................................... 3-26 Table 3-24 UARTPCellID1 Register ......................................................................................... 3-26 Table 3-25 UARTPCellID2 Register ......................................................................................... 3-26 Table 3-26 UARTPCellID3 Register ......................................................................................... 3-27 Table 4-1 Test registers summary ............................................................................................ 4-4 Table 4-2 UARTTCR register .................................................................................................... 4-5 Table 4-3 UARTITIP register .................................................................................................... 4-6 Table 4-4 UARTITOP register ................................................................................................... 4-7 Table 4-5 UARTTDR register .................................................................................................... 4-8 Table 4-6 Integration test strategy .......................................................................................... 4-14 Table A-1 APB slave interface signals ...................................................................................... A-2 Table A-2 On-chip signals ......................................................................................................... A-3 Table A-3 Pad signal descriptions ............................................................................................. A-5 viii Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G List of Figures PrimeCell UART (PL011) Technical Reference Manual Key to timing diagram conventions ............................................................................ xiv Figure 2-1 UART block diagram ................................................................................................. 2-4 Figure 2-2 IrDA SIR ENDEC block diagram ............................................................................... 2-8 Figure 2-3 Baud rate divisor ..................................................................................................... 2-11 Figure 2-4 UART character frame ............................................................................................ 2-15 Figure 2-5 IrDA data modulation (3/16) .................................................................................... 2-15 Figure 2-6 Hardware flow control between two similar devices ................................................ 2-17 Figure 2-7 DMA transfer waveforms ......................................................................................... 2-21 Figure 3-1 Peripheral Identification Register bit assignments .................................................. 3-23 Figure 3-2 PrimeCell Identification Register bit assignments ................................................... 3-25 Figure 4-1 Input integration test harness .................................................................................... 4-9 ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ix Figure 4-2 Output integration test harness, intra-chip outputs ................................................. 4-12 Figure 4-3 Output integration test harness, primary outputs .................................................... 4-13 List of Figures x Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G Preface This preface introduces the PrimeCell UART (PL011) Technical Reference Manual. It contains the following sections: • About this manual on page xii • Additional reading on page xv • Feedback on page xvi. ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. xi Preface About this manual This is the Technical Reference Manual (TRM) for the PrimeCell UART (PL011). Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: rn Identifies the major revision of the product. pn Identifies the minor revision or modification status of the product. Intended audience This manual has been written for hardware and software engineers implementing System-on-Chip designs. It provides information to enable designers to integrate the peripheral into a target system as quickly as possible. Using this manual This manual is organized into the following chapters: Chapter 1 Introduction Read this chapter for an introduction to the UART. Chapter 2 Functional Overview Read this chapter for a description of the major functional blocks of the UART. Chapter 3 Programmers Model Read this chapter for a description of the UART memory map and registers. Chapter 4 Programmers Model for Test Read this chapter for a description of the logic in the UART for integration testing. Appendix A Signal Descriptions Read this appendix for a description of the UART input and output signals. xii Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G Preface Conventions Conventions that this manual can use are described in: • Typographical • Timing diagrams • Signals on page xiv • Numbering on page xiv. Typographical The typographical conventions are: italic Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code. < and > Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> Timing diagrams The figure named Key to timing diagram conventions on page xiv explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. xiii Preface Key to timing diagram conventions Signals The signal conventions are: Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means: • HIGH for active-HIGH signals • LOW for active-LOW signals. Lower-case n At the start or end of a signal name denotes an active-LOW signal. Prefix H Denotes Advanced High-performance Bus (AHB) signals. Prefix P Denotes Advanced Peripheral Bus (APB) signals. Numbering The numbering convention is: <size in bits>'<base><number> This is a Verilog method of abbreviating constant numbers. For example: • 'h7B4 is an unsized hexadecimal value. • 'o7654 is an unsized octal value. • 8'd9 is an eight-bit wide decimal value of 9. • 8'h3F is an eight-bit wide hexadecimal value of 0x3F. This is equivalent to b00111111. • 8'b1111 is an eight-bit wide binary value of b00001111. &ORFN +,*+WR/2: 7UDQVLHQW +,*+/2:WR+,*+ %XVVWDEOH %XVWRKLJKLPSHGDQFH %XVFKDQJH +LJKLPSHGDQFHWRVWDEOHEXV xiv Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G Preface Additional reading This section lists publications by ARM and by third parties. You can access ARM documentation at: http://infocenter.arm.com/help/index.jsp ARM publications This manual contains information that is specific to the UART. See the following documents for other relevant information: • AMBA Specification (Rev 2.0) (ARM IHI 0011) • ARM PrimeCell UART (PL011) Design Manual (PL011 DDES 0000) • ARM PrimeCell UART (PL011) Integration Manual (PL011 INTM 0000). Other publications This section lists relevant documents published by third parties. • Infrared Data Association, IrDA Physical Layer Specification v1.1, obtainable at http://www.irda.org • Agilent Technologies, Agilent IrDA Data Link Design Guide (5988-9321E. March 2003), obtainable at http://www.agilent.com. ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. xv Preface Feedback ARM welcomes feedback on the PrimeCell UART (PL011) and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • the product name • a concise explanation. Feedback on this manual If you have any comments on this manual, send an email to errata@arm.com. Give: • the title • the number • the relevant page number(s) to which your comments apply • a concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements. xvi Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. ARM DDI 0183G Chapter 1 Introduction This chapter introduces the UART (PL011). It contains the following sections: • About the UART on page 1-2. • Product revisions on page 1-5. ARM DDI 0183G Copyright 2000, 2001, 2005, 2007 ARM Limited. All rights reserved. 1-1 Introduction 1.1 About the UART The UART is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM. The UART is an AMBA slave module that connects to the Advanced Peripheral Bus (APB). The UART includes an Infrared Data Association (IrDA) Serial InfraRed (SIR) protocol ENcoder/DECoder (ENDEC). The features of the UART a

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