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LC4064V-75T100I.pdf

LC4064V-75T100I.pdf

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简介:本文档为《LC4064V-75T100Ipdf》,可适用于IT/计算机领域,主题内容包含wwwlatticesemicomDSispMACHVBCZFamilyVVVInSystemProgrammableSuperFASTHighDe符等。

wwwlatticesemicomDSispMACHVBCZFamilyVVVInSystemProgrammableSuperFASTHighDensityPLDsNovemberDataSheetDSTMLatticeSemiconductorCorpAllLatticetrademarks,registeredtrademarks,patents,anddisclaimersareaslistedatwwwlatticesemicomlegalAllotherbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholdersThespecificationsandinformationhereinaresubjecttochangewithoutnoticeCoolestPowerCTMFeaturesHighPerformance•fMAX=MHzmaximumoperatingfrequency•tPD=nspropagationdelay•Uptofourglobalclockpinswithprogrammableclockpolaritycontrol•UptoPTsperoutputEaseofDesign•Enhancedmacrocellswithindividualclock,reset,presetandclockenablecontrols•UptofourglobalOEcontrols•IndividuallocalOEcontrolperIOpin•ExcellentFirstTimeFitTMandrefit•Fastpath,SpeedLockingTMPath,andwidePTpath•Wideinputgating(inputlogicblocks)forfastcounters,statemachinesandaddressdecodersZeroPower(ispMACHZ)andLowPower(ispMACHVBC)•TypicalstaticcurrentµA(Z)•TypicalstaticcurrentmA(C)•Vcorelowdynamicpower•ispMACHZoperationaldowntoVVCCBroadDeviceOffering•Multipletemperaturerangesupport–Commercial:toCjunction(Tj)–Industrial:toCjunction(Tj)–Extended:toCjunction(Tj)•ForAECQcompliantdevices,refertoLAispMACHVZAutomotiveDataSheetEasySystemIntegration•Superiorsolutionforpowersensitiveconsumerapplications•OperationwithV,VorVLVCMOSIO•OperationwithV(V),V(B)orV(CZ)supplies•VtolerantIOforLVCMOS,LVTTL,andPCIinterfaces•Hotsocketing•Opendraincapability•Inputpullup,pulldownorbuskeeper•Programmableoutputslewrate•VPCIcompatible•IEEEboundaryscantestable•VVVInSystemProgrammable(ISP)usingIEEEcompliantinterface•IOpinswithfastsetuppath•LeadfreepackageoptionsTableispMACHVBCFamilySelectionGuideispMACHVBCispMACHVBCispMACHVBCispMACHVBCispMACHVBCispMACHVBCMacrocellsIODedicatedInputstPD(ns)tS(ns)tCO(ns)fMAX(MHz)SupplyVoltages(V)VVVVVVPinsPackageTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPftBGAfpBGA,TQFPftBGAfpBGATQFPftBGAfpBGAV(V)onlyIOandIOconfigurationsUseftBGApackageforallnewdesignsRefertoPCN#AforfpBGApackagediscontinuanceLatticeSemiconductorispMACHVBCZFamilyDataSheetTableispMACHZFamilySelectionGuideispMACHIntroductionThehighperformanceispMACHfamilyfromLatticeoffersaSuperFASTCPLDsolutionThefamilyisablendofLattice’stwomostpopulararchitectures:theispLSIandispMACHARetainingthebestofbothfamilies,theispMACHarchitecturefocusesonsignificantinnovationstocombinethehighestperformancewithlowpowerinaflexibleCPLDfamilyTheispMACHcombineshighspeedandlowpowerwiththeflexibilityneededforeaseofdesignWithitsrobustGlobalRoutingPoolandOutputRoutingPool,thisfamilydeliversexcellentFirstTimeFit,timingpredictability,routing,pinoutretentionanddensitymigrationTheispMACHfamilyoffersdensitiesrangingfromtomacrocellsTherearemultipledensityIOcombinationsinThinQuadFlatPack(TQFP),ChipScaleBGA(csBGA)andFinePitchThinBGA(ftBGA)packagesrangingfromtopinsballsTableshowsthemacrocell,packageandIOoptions,alongwithotherkeyparametersTheispMACHfamilyhasenhancedsystemintegrationcapabilitiesItsupportsV(V),V(B)andV(CZ)supplyvoltagesandV,VandVinterfacevoltagesAdditionally,inputscanbesafelydrivenuptoVwhenanIObankisconfiguredforVoperation,makingthisfamilyVtolerantTheispMACHalsooffersenhancedIOfeaturessuchasslewratecontrol,PCIcompatibility,buskeeperlatches,pullupresistors,pulldownresistors,opendrainoutputsandhotsocketingTheispMACHfamilymembersareVVVinsystemprogrammablethroughtheIEEEStandardinterfaceIEEEStandardboundaryscantestingcapabilityalsoallowsproducttestingonautomatedtestequipmentTheinterfacesignalsTCK,TMS,TDIandTDOarereferencedtoVCC(logiccore)OverviewTheispMACHdevicesconsistofmultipleinput,macrocellGenericLogicBlocks(GLBs)interconnectedbyaGlobalRoutingPool(GRP)OutputRoutingPools(ORPs)connecttheGLBstotheIOBlocks(IOBs),whichcontainmultipleIOcellsThisarchitectureisshowninFigureispMACHZCispMACHZCispMACHZCispMACHZCMacrocellsIODedicatedInputstPD(ns)tS(ns)tCO(ns)fMAX(MHz)SupplyVoltage(V)MaxStandbyIcc(µA)PinsPackageTQFPcsBGATQFPcsBGATQFPcsBGATQFPcsBGATQFPcsBGATQFPLatticeSemiconductorispMACHVBCZFamilyDataSheetFigureFunctionalBlockDiagramTheIOsintheispMACHaresplitintotwobanksEachbankhasaseparateIOpowersupplyInputscansupportavarietyofstandardsindependentofthechiporbankpowersupplyOutputssupportthestandardscompatiblewiththepowersupplyprovidedtothebankSupportforavarietyofstandardshelpsdesignersimplementdesignsinmixedvoltageenvironmentsInaddition,VtolerantinputsarespecifiedwithinanIObankthatisconnectedtoVCCOofVtoVforLVCMOS,LVTTLandPCIinterfacesispMACHArchitectureThereareatotaloftwoGLBsintheispMACH,increasingtoGLBsintheispMACHEachGLBhasinputsAllGLBinputscomefromtheGRPandalloutputsfromtheGLBarebroughtbackintotheGRPtobeconnectedtotheinputsofanyotherGLBonthedeviceEveniffeedbacksignalsreturntothesameGLB,theystillmustgothroughtheGRPThismechanismensuresthatGLBscommunicatewitheachotherwithconsistentandpredictabledelaysTheoutputsfromtheGLBarealsosenttotheORPTheORPthensendsthemtotheassociatedIOcellsintheIOblockGenericLogicBlockTheispMACHGLBconsistsofaprogrammableANDarray,logicallocator,macrocellsandaGLBclockgeneratorMacrocellsaredecoupledfromtheproducttermsthroughthelogicallocatorandtheIOpinsaredecoupledfrommacrocellsthroughtheORPFigureillustratestheGLBIOBlockORPORPGOEGOEVCCGNDTCKTMSTDITDOGenericLogicBlockGenericLogicBlockIOBlockORPORPGenericLogicBlockGenericLogicBlockIOBlockIOBankIOBankIOBlockCLKICLKICLKICLKIGlobalRoutingPoolVCCOGNDVCCOGNDLatticeSemiconductorispMACHVBCZFamilyDataSheetFigureGenericLogicBlockANDArrayTheprogrammableANDArrayconsistsofinputsandoutputproducttermsTheinputsfromtheGRPareusedtoformlinesintheANDArray(trueandcomplementoftheinputs)EachlineinthearraycanbeconnectedtoanyoftheoutputproducttermsviaawiredANDEachofthelogicproducttermsfeedthelogicallocatorwiththeremainingthreecontrolproducttermsfeedingtheSharedPTClock,SharedPTInitializationandSharedPTOETheSharedPTClockandSharedPTInitializationsignalscanoptionallybeinvertedbeforebeingfedtothemacrocellsEverysetoffiveproducttermsfromthelogicproducttermsformsaproducttermclusterstartingwithPTThereisoneproducttermclusterforeverymacrocellintheGLBFigureisagraphicalrepresentationoftheANDArrayLogicAllocatorInputsfromGRPMacrocellsToORPToGRPToProductTermOutputEnableSharingOEMCFeedbackSignalsClockGeneratorOEOEOEOEOEOECLKCLKCLKCLKOEANDArrayInputs,ProductTermsLatticeSemiconductorispMACHVBCZFamilyDataSheetFigureANDArrayEnhancedLogicAllocatorWithinthelogicallocator,producttermsareallocatedtomacrocellsinproducttermclustersEachproducttermclusterisassociatedwithamacrocellTheclustersizefortheispMACHfamilyis(total)producttermsThesoftwareautomaticallyconsiderstheavailabilityanddistributionofproducttermclustersasitfitsthefunctionswithinaGLBThelogicallocatorisdesignedtoprovidethreespeedpaths:PTfastbypasspath,PTSpeedLockingpathandanuptoPTpathTheavailabilityofthesethreepathsletsdesignerstradetimingvariabilityforincreasedperformanceTheenhancedLogicAllocatoroftheispMACHfamilyconsistsofthefollowingblocks:•ProductTermAllocator•ClusterAllocator•WideSteeringLogicFigureshowsamacrocellsliceoftheLogicAllocatorTherearesuchslicesintheGLBFigureMacrocellSlicePTPTClusterPTPTPTInInInNote:IndicatesprogrammablefusePTPTPTSharedPTClockSharedPTInitializationSharedPTOEPTPTPTPTPTClustertontontonfromnfromnfromnfromnPTFromnPTsTonFastPTPathToXOR(MC)ClusterIndividualProductTermAllocatorClusterAllocatorSuperWIDESteeringLogicnLatticeSemiconductorispMACHVBCZFamilyDataSheetProductTermAllocatorTheproducttermallocatorassignsproducttermsfromaclustertoeitherlogicorcontrolapplicationsasrequiredbythedesignbeingimplementedProducttermsthatareusedaslogicaresteeredintoainputORgateassociatedwiththeclusterProducttermsthatusedforcontrolaresteeredeithertothemacrocellorIOcellassociatedwiththeclusterTableshowstheavailablefunctionsforeachofthefiveproducttermsintheclusterTheORgateoutputconnectstotheassociatedIOcell,providingafastpathfornarrowcombinatorialfunctions,andtothelogicallocatorTableIndividualPTSteeringClusterAllocatorTheclusterallocatorallowsclusterstobesteeredtoneighboringmacrocells,thusallowingthecreationoffunctionswithmoreproducttermsTableshowswhichclusterscanbesteeredtowhichmacrocellsUsedinthismanner,theclusterallocatorcanbeusedtoformfunctionsofuptoproducttermsAdditionally,theclusterallocatoracceptsinputsfromthewidesteeringlogicUsingtheseinputs,functionsuptoproducttermscanbecreatedTableAvailableClustersforEachMacrocellWideSteeringLogicThewidesteeringlogicallowstheoutputoftheclusterallocatorntobeconnectedtotheinputoftheclusterallocatornThus,clusterchainscanbeformedwithuptoproductterms,supportingwideproducttermfunctionsandallowingperformancetobeincreasedthroughasingleGLBimplementationTableshowstheproducttermchainsProductTermLogicControlPTnLogicPTSinglePTforXORORPTnLogicPTIndividualClock(PTClock)PTnLogicPTIndividualInitializationorIndividualClockEnable(PTInitializationCE)PTnLogicPTIndividualInitialization(PTInitialization)PTnLogicPTIndividualOE(PTOE)MacrocellAvailableClustersMCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCCMCCCMCCLatticeSemiconductorispMACHVBCZFamilyDataSheetTableProductTermExpansionCapabilityEverytimethesuperclusterallocatorisused,thereisanincrementaldelayoftEXPWhenthesuperclusterallocatorisused,alldestinationsotherthantheonebeingsteeredto,aregiventhevalueofground(ie,ifthesuperclusterissteeredtoM(n),thenM(n)isground)MacrocellThemacrocellsintheGLBaredrivenbytheoutputsfromthelogicallocatorEachmacrocellcontainsaprogrammableXORgate,aprogrammableregisterlatch,alongwithroutingforthelogicandcontrolfunctionsFigureshowsagraphicalrepresentationofthemacrocellThemacrocellsfeedtheORPandGRPAdirectinputfromtheIOcellallowsdesignerstousethemacrocelltoconstructhighspeedinputregistersAprogrammabledelayinthispathallowsdesignerstochoosebetweenthefastestpossiblesetuptimeandzeroholdtimeFigureMacrocellEnhancedClockMultiplexerTheclockinputtotheflipflopcanselectanyofthefourblockclocksalongwiththesharedPTclock,andtrueandcomplementformsoftheoptionalindividualtermclockAn:multiplexerstructureisusedtoselecttheclockTheeightsourcesfortheclockmultiplexerareasfollows:•BlockCLK•BlockCLKExpansionChainsMacrocellsAssociatedwithExpansionChain(withWrapAround)MaxPTMacrocellChainMMMMMChainMMMMMChainMMMMMChainMMMMMSinglePTBlockCLKBlockCLKBlockCLKBlockCLKPTClock(optional)SharedPTClockCEDTLQRPSharedPTInitializationPTInitializationCE(optional)PTInitialization(optional)FromLogicAllocatorPowerupInitializationToORPToGRPFromIOCellDelayLatticeSemiconductorispMACHVBCZFamilyDataSheet•BlockCLK•BlockCLK•PTClock•PTClockInverted•SharedPTClock•GroundClockEnableMultiplexerEachmacrocellhasa:clockenablemultiplexerThisallowstheclockenablesignaltobeselectedfromthefollowingfoursources:•PTInitializationCE•PTInitializationCEInverted•SharedPTClock•LogicHighInitializationControlTheispMACHfamilyarchitectureaccommodatesbothblocklevelandmacrocelllevelsetandresetcapabilityThereisoneblocklevelinitializationtermthatisdistributedtoallmacrocellregistersinaGLBAtthemacrocelllevel,twoproducttermscanbe“stolen”fromtheclusterassociatedwithamacrocelltobeusedforsetresetfunctionalityAresetpresetswappingfeatureineachmacrocellallowsforresetandpresettobeexchanged,providingflexibilityNotethattheresetpresetswappingselectionfeatureaffectspowerupresetaswellAllflipflopspoweruptoaknownstateforpredictablesysteminitializationIfamacrocellisconfiguredtoSETonasignalfromtheblocklevelinitialization,thenthatmacrocellwillbeSETduringdevicepowerupIfamacrocellisconfiguredtoRESETonasignalfromtheblocklevelinitializationorisnotconfiguredforsetreset,thenthatmacrocellwillRESETonpowerupToguaranteeinitializationvalues,theVCCrisemustbemonotonic,andtheclockmustbeinactiveuntiltheresetdelaytimehaselapsedGLBClockGeneratorEachispMACHdevicehasuptofourclockpinsthatarealsoroutedtotheGRPtobeusedasinputsThesepinsdriveaclockgeneratorineachGLB,asshowninFigureTheclockgeneratorprovidesfourclocksignalsthatcanbeusedanywhereintheGLBThesefourGLBclocksignalscanconsistofanumberofcombinationsofthetrueandcomplementedgesoftheglobalclocksignalsFigureGLBClockGeneratorCLKCLKCLKCLKBlockCLKBlockCLKBlockCLKBlockCLKLatticeSemiconductorispMACHVBCZFamilyDataSheetOutputRoutingPool(ORP)TheOutputRoutingPoolallowsmacrocelloutputstobeconnectedtoanyofseveralIOcellswithinanIOblockThisprovidesgreaterflexibilityindeterminingthepinoutandallowsdesignchangestooccurwithoutaffectingthepinoutTheoutputroutingpoolalsoprovidesaparallelcapabilityforroutingmacrocelllevelOEproducttermsThisallowstheOEproducttermtofollowthemacrocelloutputasitisswitchedbetweenIOcellsAdditionally,theoutputroutingpoolallowsthemacrocelloutputortrueandcomplementformsofthePTbypasssignaltobypasstheoutputroutingmultiplexersandfeedtheIOcelldirectlyTheenhancedORPoftheispMACHfamilyconsistsofthefollowingelements:•OutputRoutingMultiplexers•OERoutingMultiplexers•OutputRoutingPoolBypassMultiplexersFigureshowsthestructureoftheORPfromtheIOcellperspectiveThisisreferredtoasanORPsliceEachORPhasasmanyORPslicesasthereareIOcellsinthecorrespondingIOblockFigureORPSliceOutputRoutingMultiplexersThedetailsofconnectionsbetweenthemacrocellsandtheIOcellsvaryacrossdevicesandwithinadevicedependentonthemaximumnumberofIOsavailableTablesprovidetheconnectiondetailsTableORPCombinationsforIOBlockswithIOsIOCellAvailableMacrocellsIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MOutputRoutingMultiplexerOERoutingMultiplexerORPBypassMultiplexerFromMacrocellFromPTOEToIOCellToIOCellOutputOEPTFastPathLatticeSemiconductorispMACHVBCZFamilyDataSheetTableORPCombinationsforIOBlockswithIOsTableORPCombinationsforIOBlockswithIOsTableORPCombinationsforIOBlockswithIOsIOCellAvailableMacrocellsIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M,M,M,MIOM,M,M,M,M

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