RTL8196E_Design-Layout Guide_V100

RTL8196E Layout Guide Rev. V100 14 Jan. 2013 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211 Fax: +886-3-577-6047 www.realtek.com RTL8196E Layout Guide 2 Rev.V100 REVISION HISTORY Revision Release Date Summary V100 2013/01/14 Preliminary Release RTL8196E Layout Guide 3 Rev.V100 1. General Design and Layout Guide In order to achieve maximum performance with the RTL8196E, good design attention is required throughout the design and layout process. The following recommendations will help implement a high performance system. 1.1. General Guidelines · Provide a good power source, minimizing noise from switching power supply circuits (Power noise <100mV @3.3V, Power noise <50mV @1.0V). · Verify the critical components, such as clock source and transformer, to meet the application requirements. · Keep power and ground noise levels below 100mV @ 3.3V power plan. · Keep power and ground noise levels below 50mV @ 1.0 power plan. · Use bulk capacitors (4.7uF-10uF) between each power and ground plane. · Use 0.1uF decoupling capacitors to reduce high-frequency noise on the power and ground planes. · Keep decoupling capacitors as close as possible to the RTL8196E. · The RJ-45 phone jack should be placed as close as possible to the transformer. · Prevent right angles on all traces. · Fill in unused areas of component side and solder side with solid copper and attach them with via holes to ground plane. · MDIREF pin of RTL8196E must connect to GND via 2.49K +/- 1% Ohm resister. This resister must be put as close as possible to RTL8196E. 2. Clock Circuit · Place the crystal as close to the RTL8196E as possible. · Surround the clock with ground trace to minimize high-frequency emissions. · Keep clearance area under the crystal or OSC component. · Don’t let the clock trace pass over a gap in the ground plane. · Keep RTL8188ER/RTL8192ER clock trace on top layer as possible. RTL8196E Layout Guide 4 Rev.V100 3. Power Planes · When designing a 4-layer PCB layout, divide the power plane into 3.3V copper and 1.0V core power copper in layer 3, usually layer 2 to be ground copper. · Use 0.1μF decoupling capacitors and bulk capacitors between each power plane and ground plane. 4. Ground Planes · Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to the rest of the board. · Place a moat (gap) between the system ground and chassis ground. · RTL8196E ground pins follow ground via holes. 5. MDI Differential Signal Layout Guidelines · Ideally, keep inter-trace spacing with 3 times of trace width, to reduce crosstalk (for example, if the width of the signal trace is 6 mil, the inter-trace spacing should be 18 mil or more). · For traces longer than 5 inches, guard traces should be placed between signal traces. The guard traces should have many via holes to GND. · Avoid layer is changed in MDI interface if possible. · Please follow below diagram for reference RTL8196E Layout Guide 5 Rev.V100 6. PCI-E and Ethernet MDI Differential Signals Impedance · Both PCI-E and Ethernet MDI differential-pair impedance is 100ohm±10%. · All microstrip traces of a differential pair should be 5-mil width with a 7-mil width air gap spacing between the trace of the pair for 4-layer PCB layout. · All microstrip traces of a differential pair should be 7-mil width with a 5-mil width air gap spacing between the trace of the pair for 2-layer PCB layout. · Keep differential pairs as close as possible and route both traces as identically as possible, meaning width, length, and location. · Ideally, maintain a 30mil minimum gap as possible between two ports differential pairs. Port n MDI Pair Port (n+1) MDI Pair 5 mils5 mils 7 mils 5 mils5 mils 7 mils 30 mils Figure 1. Trace Width and Spacing Recommendation for 4-layer PCB Port n MDI Pair Port (n+1) MDI Pair 7 mils7 mils 5 mils 7 mils7 mils 5 mils 30 mils Figure 2. Trace Width and Spacing Recommendation for 2-layer PCB RTL8196E Layout Guide 6 Rev.V100 7. ESD Protection · Ideally, maintain an 80mil minimum gap between two differential pairs or signal at the transformer second side to improve ESD protection. · Ideally, maintain an 80mil minimum gap between signal trace and frame GND to improve ESD protection. · Ideally, maintain an 80mil minimum gap between system-GND and frame-GND to improve ESD protection. · Avoid layer is changed in MII interface if possible. 8. PCI-E · PCI-E differential Tx signals with 0.1uF coupling capacitors must be closed to chip’s PCI-E output pin as possible. · Please follow 100 ohms differential-pair impedance requirement, which follows figure 1 and figure2 diagram. · Avoid layer is changed in PCI-E interface if possible. · PCI-E Tx, Rx and clk differential pairs must keep on top layer, each pair is isolated by GND copper such as below figure. . RTL8196E Layout Guide 7 Rev.V100 9. RTL8196E internal 1.0V SWR · RTL8196E internal 1.0V SWR only can be used on RTL8196E core power (1.0V), which cannot use on any other application circuits. · RTL8196E Internal 1.0V SWR output capacitors cannot be over 20uF, inductor value is strongly suggested to 3.3uH for avoiding with SWR circuit oscillation. · For the main current paths, keep their traces short and wide · Put the input capacitors as close as possible to the 3.3V SWR input pin · Lx node is with high frequency voltage swing and should be kept small layout area. Keep analog components away from Lx node to prevent stray capacitive noise pick up. · Connect and close the SWR output capacitors grounds to the chip main ground. · Please follow below diagram for reference. 10. SDRAM · Route all the SDRAM signals on top layer if possible and shorten all traces distance between RTL8196E and SDRAM. · There should be a ground plane adjacent to the top layer where the clock traces are routed. · Please follow below diagram for reference. RTL8196E Layout Guide 8 Rev.V100 11. USB · The impedance is 90 ohms between the differential pair USB_DP and USB_DN to match the 90 ohms twisted pair cable impedance. · All microstrip traces of a differential pair should be 7-mil width with a 7-mil width air gap spacing between the trace of the pair for 4-layer PCB layout. · All microstrip traces of a differential pair should be 14-mil width with a 5-mil width air gap spacing between the trace of the pair for 2-layer PCB layout. · Before entry to the connector, use 0 ohms instead of ferrite beads on the USB_DN and USB_DP lines if pass USB characteristics. · Please follow below diagram for reference. RTL8196E Layout Guide 9 Rev.V100 Headquarters No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw