Xilinx Virtex-6 时钟资源介绍

nullBasic FPGA Architecture (Virtex-6)Basic FPGA Architecture (Virtex-6)Clocking ResourcesObjectivesObjectivesAfter completing this module, you will be able to: Detail the clocking resources available in the Virtex-6 FPGA Specify the resources available in the Clock Management Tile (CMT) Describe the basics of the PLL capabilities Virtex-6 Clock ManagementVirtex-6 Clock ManagementGlobal clock buffers High fanout clock distribution buffer Regional clock distribution (low-skew) I/O clock routing Clock regions Each clock region is 40 CLBs high and spans half the device Clock management tile (CMT) Two PLL-based Mixed-Mode Clock Managers (MMCMs) in each Clock Management Tile (CMT) Up to nine CMTs per device Performs frequency synthesis, clock de-skew, and jitter-filtering High input frequency range (10-800 MHz) Simple design creation through the Clocking WizardMMCM FeaturesMMCM Features8 independently programmable clock outputs (O0-O6 and CLKFBOUT) O0 to O3 and CLKFBOUT offer complementary outputs Additional MMCM_ADV features Clock input switching Phase shift port Dynamic Reconfiguration Port (DRP) LOCK circuit enhanced to eliminate possibility of false LOCK Both are easily customized with the Architecture Wizard MMCM able to implement both DCM and PLL functionalityEach MMCM can be invoked with either the MMCM_BASE or MMCM_ADV primitive. SW takes care of unused ports on MMCM_BASE.Die ViewDie ViewClock RegionsIO ColumnsClock Spine and ColumnMMCM TilesHROWsBUFIO (Single or Multi Region)BUFG in Center of DeviceBUFRBUFHClocks in “Leaf” RegionBUFH Mux AreasVirtex-6 FPGA Clock DistributionVirtex-6 FPGA Clock DistributionLarger clock region 40 CLBs high, 40 I/Os high Same size as I/O bank Half width of device 6-18 regions per device Resources per clock region 12 global clock networks Driven by BUFH 6 regional clock networks Driven by BUFR 8 I/O clock networks per I/O columnGlobal ClockingGlobal Clocking32 BUFGs reside in the center of the device Driven by 8 global clock pins There are also four clock-capable I/O pins per I/O bank Four differential or single-ended Global clock pins are not the only clock input resource BUFGs can be driven by Global clock inputs Clock-capable inputs (inner I/O columns only) MMCM outputs Other BUFG Interconnect BUFR GTX (recovered clock from GTX) BUFG outputs can drive the vertical global clock spine BUFGCTRL component implements Glitch-free clock switching between two sources Clock enable for disabling clocksHorizontal ClockingHorizontal Clocking12 BUFHs per clock region You should not have to instantiate this BUFH drives logic via horizontal global clock lines BUFHs on left and right of vertical spine can be driven by the same CCIO or MMCM output Driven by… MMCM in the same region BUFG via vertical clock spine Clock-capable inputs in same horizontal row Interconnect Provides control of clocks routed into regions Power saving by turning off or gating clocks to specific regions Isolating logic into regions may require an Area ConstraintBUFHIORegional ClockingRegional ClockingUp to 4 BUFRs per clock region (varies by density) 2 per I/O bank Driven by… Clock-capable inputs Interconnect GTX MMCM high-performance clocks Can drive… Logic IO logic MMCM BUFG For medium- and high-performance clocks driving 1-3 regions (one above, self, and one below) BUFR frequency can be divided by 1…8I/O ClockingI/O Clocking2 single-region BUFIOs and 2 multi-region BUFIOs in each I/O bank Driven by… Clock-capable inputs in the same I/O bank MMCM outputs via high-performance paths Can drive… I/O logic in the same and adjacent I/O banks BUFIO can drive logic resources only in the same I/O column Intended for clocking high-speed I/O logicSource-Synchronous InterfacesSource-Synchronous InterfacesI/O and regional clock networks combined with ISERDES/OSERDES provide powerful tools for creating source synchronous interfaces BUFR is set to ÷N if interface is SDR, or ÷(N/2) if DDR N can be 2 to 8 in SDR, and 2 to 10 in DDRClock-Capable I/O (CCIO)I/O Clock Buffer (BUFIO)Conventional I/O (IO)Regional Clock Buffer (BUFR)Performance Path RoutingPerformance Path Routing4 performance paths driving each inner/outer left/right IO column Driven by… MMCM outputs O0-O3 Can drive… BUFIO BUFR GTX Powered by a regulated supply within each MMCM This isolates the clocks from noise on Vccint Cleanest path from MMCM to I/O columns Lower jitter than any other routing Software automatically places critical signals onto performance path routing, so don’t worry about controlling this route Global Clocking FeaturesGlobal Clocking FeaturesI/O and Regional ClockingI/O and Regional ClockingVirtex-6 Clock Network SummaryVirtex-6 Clock Network SummaryMMCM FeaturesMMCM FeaturesUp to 9 CMTs per device 2 MMCMs per CMT Two software primitives MMCM_BASE has only the basic ports MMCM_ADV provides access to all ports 8 independently programmable clock outputs O0 to O6 plus CLKFBOUT O0 to O3 and CLKFBOUT true and complement outputs Additional MMCM_ADV features Clock input switching Phase shift port MMCM InternalsMMCM InternalsPhase / frequency detector compares CLKIN with CLKFB Accepts up to 650-MHz inputs Adjusts the charge pump output voltage higher or lower Charge pump controls the VCO frequency Many different output frequencies can be generated Fout = Fin * M / (D*O) One M and one D value per MMCM Each MMCM output can have its own O value M: 1…64; D: 1…80; O: 1…128 Extra MMCM FeaturesExtra MMCM FeaturesFractional counters Ability to configure O0 and CLKFBOUT as counters with 1/8th granularity (e.g. 2.125, 2.250, 2.375, etc.) O5 output is disabled when using this feature Enables many more frequencies to be synthesized Two methods of shifting phase Static phase shift using time-shifted VCO outputs Dynamic phase shift using the PS port to change the phase on the fly in increments of 1/56 of VCO periodAdditional MMCM SignalsAdditional MMCM SignalsComplement outputs O0-O3 of every MMCM have both true and complement outputs Provide 180 degree phase shift LOCKED Signal showing that the MMCM has locked on to the input frequency CLKINSTOPPED/FBSTOPPED Status signals indicating that the input or feedback clocks have stopped running PWRDWN (not shown) Disable / Enable signal to the regulated supply of each MMCM Unused MMCMs draw powerVCOLFCPPFDO0CLKFBCLKIN1CLKIN2RoutingClock SwitchDCLKINSTOPPEDLockCLKFBSTOPPEDStop DetectLock Detect9O1O2O3O4O5O6M CLKFBOUTHOLDMMCM ConnectivityMMCM ConnectivityMany possible inputs to each MMCM CCIO from inner I/O columns Global clock inputs BUFG GTX clocks MMCM outputs drive BUFG BUFH in same region Performance paths to BUFIO and BUFR (not shown)Clock DeskewClock DeskewUse a BUFG on CLKFBOUT if a precise phase relationship between input clock and output clock is required Most flexible solution but requires two global clock buffers Remove the BUFG on CLKFBOUT if there is no need for a precise phase relationship Frequency synthesis or jitter filtering only MMCM-to-MMCM ConnectionMMCM-to-MMCM ConnectionMMCMs in the same CMT can be connected without the need for a global clock buffer Output clock will not be aligned to input clock More clock frequencies can thus be generated MMCM-to-MMCM ConnectionMMCM-to-MMCM ConnectionMMCMs in the same CMT can be connected without the need for a global clock buffer Output of first MMCM connected to CLKIN of second MMCM BUFG inserted from CLKFBOUT to CLKFBIN of the first MMCM to align output clock with input clock CLKFBOUT of first MMCM can also drive logic Enables more phase-aligned clock frequencies to be generatedExampleExampleRequirement 33.3-MHz external oscillator controls 533-MHz data being generated by I/O logic (BUFIO) Large amount of logic at 66 MHz (BUFG) Small design at 54 MHz (BUFH) Phase relationship between input clock and output clock is irrelevant Solution MMCM values M=16, D=1, O0=9.875, O1=1, O2=8 Generates 54 MHz on clkout0 O0 set to 9.875 using fractional counter 533 MHz on clkout1 66 MHz on clkout2SummarySummaryClock regions = 40 CLBs, 40 IOBs in height One or two I/O columns per region 32 global clock buffers (differential) 8 global clock input pins (differential) 12 global clocks per region 4 BUFIOs per I/O bank (differential) 2 can drive adjacent I/O banks, others are local only 2 BUFRs per I/O bank 6 regional clock networks Can drive adjacent clock regions The Clock Management Tile (CMT) has two Mixed-Mode Clock Managers (MMCMs) Each MMCM includes a PLL Jitter filtering and frequency synthesis capabilitiesWhere Can I Learn More?Where Can I Learn More?User Guides Virtex-6 FPGA Clocking Resources User Guide Describes the complete clocking structures Xilinx Education Services courses www.xilinx.com/training Designing with the Virtex-6 and Spartan-6 Families course Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture, Basic HDL Coding Techniques, and other Free training videos! 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