Design and Implementation of Three-Level

2234 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Design and Implementation of Three-Level Space Vector PWM IP Core for FPGAs Haibing Hu, Wenxi Yao, and Zhengyu Lu, Senior Member, IEEE Abstract—This paper presents a novel circuit realization of the three-level space-vector pulse-width modulation (SVPWM) strategy. A simplified algorithm for the three-level SVPWM is proposed. Due to the geometrical symmetry of six sectors, there exist the close relationships in on time calculations and on time arrangement for switches between them. So it can complete the computation of the three-level SVPWM in one sector. Conse- quently, compared with the conventional algorithm, the proposed algorithm is more suitable to hardware implementation by greatly reducing computation amount. Based on the simplified algorithm, a three-level SVPWM intellectual property (IP) core has been developed using hardware description language (HDL). The designed IP core can serve as a coprocessor to relieve the DSP or MCU from the intensive computation task of the three-level SVPWM. Simulation and experimental results are given to verify the IP core in a field programmable gate array (FPGA). Index Terms—Field programmable gate array (FPGA), intellec- tual property (IP), three-level space-vector pulse-width modula- tion (SVPWM). I. INTRODUCTION RECENTLY, multilevel topologies caught great attentionin the field of high-power and high-voltage applications [1]–[4]. They improve output waveform quality of the voltage source inverter by increasing waveform steps and reduce the voltage stress across switches. Low voltage stress results in the low dv/dt, which causes less EMI problems. Among these topologies, the neutral-point clamped (NPC) three-level topolo- gies is recently showing great popularity for such applications. Researchers conducted intensive studies on this type converter, covering soft switching, neutral point voltage self-balancing and all kinds of modulations [5]–[12]. As one of most promising modulation technologies in three phase systems, space vector PWM (SVPWM) for three-level converter has an advantage over sinusoidal PWM in voltage utility, for modulation range of SVPWM is 15% higher than that of sinusoidal PWM [8]. Although three-level SVPWM technique is derived from two- level SVPWM, three-level SVPWM is considerably more com- plex than that of two-level converter because of large number of converter switches and the problem of neutral point voltage self- Manuscript received December 1, 2006; revised February 23, 2007. This work was supported by the National Natural Science Foundation of China (50237030ZD). Recommended for publication by Associate Editor A. Trzynadlowski. H. Hu is with the Aero-Power Sci-Tech Center, Nanjing Univer- sity of Aeronautics and Astronautics, Nanjing 210016, China (e-mail: huhaibing@163.com). W. Yao and Z. Lu are with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: ywxi@zju.edu.cn; eeluzy@cee. zju.edu.cn). Digital Object Identifier 10.1109/TPEL.2007.909296 balancing. Due to its complexity in computation, three-level SVPWM algorithm is almost implemented using software based on DSP or MCU according to reported literatures [5]–[11]. This method demonstrates high flexibility and adaptability to various applications, but it also suffers some disadvantages: 1) As a se- quence controller, these type processors interpret instructions line by line, which results in time delay and leads to deteriorate the performance of a control system. 2) With most computa- tion resources devoting to the periodic events such as sampling, control algorithm calculating and PWM gating signals gener- ating, limited resources are left to other functions. In order to resolve these problems, multi-DSP systems are often adopted in these applications, but hardware and software design for such multi-DSP systems will complicate the design process greatly and incur some reliability problems. An alternative to the problems is a new hardware-software partition, in which time-critical and periodic intensive computa- tion tasks can be undertaken by hardware featuring parallelism. Therefore, the processor can be relieved from the onerous pe- riodic computation tasks and gain more computation resources to cope with other tasks. Thanks to great advancement in micro-electronics technology and electronic design automation (EDA) technology [13], some researchers begin to incorporate the high density programmable logic device such as field programmable gate array (FPGA), complex programmable logic device (CPLD) and erasable programmable logic device (EPLD) into DSP-based digital controllers to make such parti- tions possible and practicable. With the programmable features of PLDs, users can migrate some software-based computation tasks into the application specific integrated circuit (ASIC) de- signed by their owns in the lab or field conveniently according to the specific functions. This design methodology has received great attention in recent years. Some forerunners began to develop some ASICs or IP (Intellectual Property) cores for power electronics, such as two-level SVPWM IC, PWM IP core, speed estimation IP core, etc. [14]–[17]. However, implementation of three-level SVPWM totally based on hardware technology has so far still not been reported in the literature. This paper adopts some measures such as simplified algorithm, data normalization and overflow processing to develop a novel digital IP core for the three-level SVPWM and the IP core is verified in a FPGA (EP1C6) from Altera, Inc. The designed three-level SVPWM IP core can be compiled, synthesized and then downloaded to the corresponding PLD. It can serve as a coprocessor to relieve the processor from time-consuming computation of the three-level SVPWM, but also make the DSP/FPGA-based control structure much flexible and expandable in controlling three-level con- verters. The rest of the paper is organized as follows: Section II briefly introduces the principle of the three-level SVPWM. 0885-8993/$25.00 © 2007 IEEE HU et al.: DESIGN AND IMPLEMENTATION OF THREE-LEVEL SPACE VECTOR PWM IP CORE FOR FPGAs 2235 Fig. 1. Three-level main circuit. TABLE I SWITCHING STATES AND THEIR REPRESENTATION Section III explains the simplified algorithm of the three-level SVPWM suitable to hardware implementation. Section IV dis- cusses the detailed design and implementation of this IP core. Experimental results are given in Section V. Some conclusions are drawn in Section VI. II. PRINCIPLE OF THE THREE-LEVEL SVPWM Various PWM techniques for the three-level converter have been intensively studied since Nabae proposed the topology named neutral point clamped (NPC) converter [18]. In various PWM techniques, the three-level SVPWM is one of most promising and widely applied PWM techniques in three phase systems. It is a naturally accepted view that three-level SVPWM is an extension of the conventional two-level SVPWM. A. Basic Principle Fig. 1 shows the main circuit of the three-level converter. Each bridge, composed of four switches, has three kinds of switching states, which can be represented by P, O, N listed in Table I. So 27 switching states exist in three-phase three-level converter, each of which can be represented in vector form using following expression (1) 27 vectors can construct the space-vector diagram of a three- level converter, shown as Fig. 2. There are 24 active vectors including 12 short vectors, 6 medium vectors and 6 long vectors, and the remaining three are zero vectors (PPP, OOO, NNN), which lie at the center of the hexagon. The area of the hexagon can be divided into six sectors (A to F), each of which has four regions (1 to 4), with 24 regions of operation in total. By using sector A as an example, the calculation flow of the three-level SVPWM algorithm can be clearly demonstrated. Fig. 2. Space-vector diagram of the three-level converter. Fig. 3. Vector combination in sector A. Considering the reference voltage vector staying in the re- gion 2, it can be composed of by voltage vectors , and as illustrated in Fig. 3. During a sampling period , the average output voltage combined by three consecutive voltage vectors should match with the reference voltage. Therefore, the equa- tions for on time of the voltage vectors can be given as (2) From above expressions, the on time of voltage vectors can be calculated out as follows: (3) where . Using the same procedure, the dwelling time in other regions in sector A can be obtained as shown in Table II. B. Switching Sequence Arrangement If the on times are calculated out, the switching sequence has to be determined. However the converter has some redundant switching states, so there are several options to determine the switching sequence. Switching sequence can be arranged 2236 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 TABLE II ON TIMES IN SECTOR A Fig. 4. Switching sequence arranged in a symmetrical pattern. according to certain optimal objective, for example, minimum switching loss or minimum total harmonic distortion (THD). In this paper, in order to achieve low THD, all relevant switching states are arranged to form the switching sequence. The switching sequences in the regions of sector A are arranged as follows: Region 1: PPO-POO-OOO-OON-ONN and return Region 2: PPO-POO-PON-OON-ONN and return Region 3: PPO-PPN-PON-OON and return Region 4: POO-PON-PNN-ONN and return C. Symmetrical PWM Generating The PWM signals can be generated using PWM generator to fire the switches. For example, the switching sequence in region 2 can be arranged as illustrated in Fig. 4, so the sym- metrical PWM signals can be easily generated. As indicated in the name of the topology, each phase has three voltage levels, which require two PWM generators to produce. Taking phase B in Fig. 4 as an example, the waveform can be decomposed into two two-level waveforms, which can be produced easily using two PWM generators as shown in Fig. 5. According to switching sequences arranged in symmetrical pattern, the PWM firing time setting for each switch in sector A can be achieved as given in Table III. Fig. 5. Firing time settings for four switches using two PWM generators in phase B. TABLE III PWM FIRING TIME SETTING FOR EACH SWITCH OF UPPER ARMS IN SECTOR A D. Calculation Flow Above realization procedures in sector A can be applied to other sectors and will obtain similar results. Calculation flow for the three-level SVPWM is illustrated in Fig. 6. Calculation flow is totally same for any reference vector that stays in any one of 24 regions, however the voltage vectors and switching sequences are totally different in each region. So 24 routines (one routine for each region) are required to carry out the three- level SVPWM calculation. For sequence controllers like DSP or MCU, such calculation flow has no effect on computation effi- ciency due to the reason that only one routine is called to execute once in each switching period to calculate the corresponding reference vector. While using FPGA or ASIC to implement such calculation in parallel, such calculation flow would lead to a great demanding requirements on hardware resources, be- cause it needs the capacity of hardware resources to realize computation resources of all 24 regions. Therefore, the conven- tional algorithm should be optimized in adaptation to hardware realization. HU et al.: DESIGN AND IMPLEMENTATION OF THREE-LEVEL SPACE VECTOR PWM IP CORE FOR FPGAs 2237 Fig. 6. Conventional calculation flow for the three-level SVPWM. Fig. 7. Two vectors with 60 shifting in the sector A and B. III. SIMPLIFIED ALGORITHM The main idea for simplified algorithm comes from the fact that the shape of 6 sectors is identically same as seen from Fig. 2. So there should exist some close relationships in on time calculations and arrangement for switches in each phase be- tween them. If the relationships between them can be clearly deduced, we can calculate the on times for switches in certain sector and then map the on times in specific sector into the cor- responding on times in other sectors through the relationships between them. In fact, some relationships exist. The following is the explanation of the relationships between them. A. The Relationship of on Times Between Them Suppose reference vector A stays in region 2 of sector A, while reference vector B is obtained by rotating vector A coun- terclockwise by 60 as demonstrated in Fig. 7. Therefore, vector A and vector B with the same length lie in the region 2 of sector A and B respectively. As explained in the Section II, the refer- ence vector can be composed of by vector , and , TABLE IV RELATIONSHIPS OF PHASE VOLTAGES CONSTRUCTING THE REFERENCE VECTORS IN SIX SECTORS Fig. 8. Phase voltage reversing by mirroring PWM signals. TABLE V RELATIONSHIP OF ON TIMES OF s AND s BEFORE AND AFTER MIRRORING Fig. 9. Simplified calculation flow for the three-level SVPWM. whose on times can be calculated using expression (2). While the reference vector can be composed by vector , and , whose on times can also be given as (4) 2238 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Fig. 10. Functional blocks of the IP core. The expression (4) can be transformed into expression (2) by multiplying the rotating factor at both sides of the equation as illustrated as follows: It is clearly shown that the on times of the corresponding voltage vectors are totally same. This relationship in other re- gions of any other sectors is also validated. Therefore, when the reference vector in other sectors is rotated to sector A by ( , 2, 3, 4, 5), the on times calculated out in sector A equal to those in other sectors. B. Relationship of Switching Sequences Between Them If the relationship between the switching sequences in sector A and those in other sectors can be found out, the switching se- quences can be arranged in sector A and then mapped to the other sectors through the corresponding relationship. By this means, all the calculation procedures can be carried out in sector A, which will definitely reduce computation resources in hard- ware implementation. Considering that the reference vector is expressed as a combination of phase voltage , , and in vector form as (5) So the reference vector can be expressed in the fol- lowing form. (6) Equation (6) indicates that vector also can be com- bined using phase voltage , , and by shifting and re- versing phase voltages. Using the same way, the corresponding reference vector in other sectors can be constructed as given in Table IV. Phase voltage shifting is pretty easy to be accomplished by exchanging the PWM signals between two corresponding phases. While phase voltage reversing can be achieved by mirroring the PWM signals of switches of upper arm with those of lower arm as illustrated in Fig. 8. Suppose the switching state is P, which means the switches and are on and switches and are off. By mirroring the PWM signals, the switches and are off and switches and are on, and the switching state is N. So is the same when the switching state is N. When the switching state is O, the switching state is still O by mirroring. In doing so, the phase voltage reversing can be obtained. The relationship of on times of and before and after mirroring can be easily deduced as given in Table V. Through the simplified algorithm, the calculation flow for six sectors can be mapped into sector A, as demonstrated in Fig. 9. Compared with the conventional calculation flow introduced in Section II, the simplified calculation flow can significantly re- duce the hardware requirements for hardware implementation. IV. DESIGN FOR THE THREE-LEVEL SVPWM IP CORE According to the simplified calculation flow given in Section III, the three-level SVPWM IP core can be partitioned into several functional blocks as illustrated in Fig. 10. The IP core consists of four registers for setting two vector compo- nents and , the switching frequency of the PWM and the dead-time for the switches. To simplify the interface with DSP or MCU, commands to these registers are routed through a decoder and interface circuit. The control parameters can be fed by externally interfaced MCU or DSP. The internal functional blocks consist of sector judging, vector rotating, region judging, on time calculating and arranging, on time mapping, on time converting and PWM generating. The input clock acting as a base time for PWM generator can operate under 100 MHz. The overflow flag from PWM generators indicates the value of PWM counter reaches the summit, which can be used to trig events for MCU or DSP. In the design of the IP core, many other factors need con- sidering, such as computation accuracy, simplicity and flexi- HU et al.: DESIGN AND IMPLEMENTATION OF THREE-LEVEL SPACE VECTOR PWM IP CORE FOR FPGAs 2239 Fig. 11. Three methods for implementing multiplication. (a) IP-based method; (b) parameterized IP method; and (c) addition/subtraction method. Fig. 12. Realization of multiplication based on addition/subtraction. bility. The IP core involves some computational intensive tasks marked by inner line, such as vector rotating, on time calculating and so on. Therefore, computation efficiency and data manip- ulating method are important factors in designing the IP core. In this paper, some key design measures for improving compu- tation accuracy and simplifying hardware design are taken, and 16-b fix-point arithmetic has been adopted for implementing the calculations. A. Measure 1: Data Normalization When using a fix-point mode, it is necessary to reduce the amplitude of the variables in order to get a fractional part with a maximum precision through data normalization, whose pur- pose is to convert all data into normalized data with the same range. So the same computation accuracy can be achieved in the whole calculation, and in practical applications, the IP core in normalized data format can be easily adapted to various appli- cations with unnecessary considerations of the actual voltages, frequencies and duty ratios. In this paper, besides the normal- ization of the two orthogonal components and , the PWM firing times are also normalized, and the base values for above variables are given as (7) (8) where stands for bus voltage, and is switching period. Using above base values, the normalized vector components and normalized PWM firing times can be calculated by following expressions: u � � = u u u � � = u u t � x = t t : (9) Therefore all the calculations in the IP core can be expressed in the normalized forms. Considering the overmodulation and TABLE VI HARDWARE RESOURCES USED IN THREE METHODS Fig. 13. Addition/subtraction IP core with overflow flag. TABLE VII TRUE TABLE FOR PROCESSING OVERFLOW X means don’t care the value. Fig. 14. Two ROMs used to generate vector components. the range of coefficients in the IP core, the computation values are kept in the range of ( 2,2), and thus the suited numerical format chosen is Q14 for the design, where the Q14 representa- tion of 1 is 4000 h. B. Measure 2: Simplified Multiplication In the design, the multiplication calculation is widely involved in sector judging, vector rotating and on time cal- culating. In this design, all these multiplications have a fixed multiplicator . There are three methods to implement this multiplication as shown in Fig. 11. One is to call the fixed-point multiplication IP core offered by the design environment. The next one can be achieved by setting the multiplicator as fixed number through IP configuration. The last one uses the addition/subtraction to realize the arithmetic operation of expression . In this paper, the last method is adopted to reduce the hardware resources in implementing multiplication. An in