！顶星915主板电路图

5 5 4 4 3 3 2 2 1 1 D D C C B B A A Revision 1.1 SHEET TITLE COMPONENT SIDE GND SIDE (1 oz. Copper) (1 oz. Copper) (1 oz. Copper) (1 oz. Copper) VCC SIDE SOLDER SIDE 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 SHEET TITLE 23 24 25 26 27 28 29 30 31 BOM & PCB MODIFY HISTORY COVER SHEET P4_LGA775_A P4_LGA775_B P4_LGA775_C GMCH-GRANTSDALE_HOST GMCH-GARNTSDALE_DDR DDR CHANNEL B DDR TERMINATION ICH6 PCI, USB, DMI, LAN ICH6 IDE, GPIO, SATA, CTRL ICH6 VCC, GND FWH CK410M CLOCK. PCI SLOT 1, 2 ITE8712HX IDE KB_PS2 COM_LPT CPU_FAN & SYS_FAN32 33 34 HWMO BLOCK DIAGRAM GMCH-GRANTSDALE_PWR VCORE POWER 35 36 POLY S/W FRONT PANEL 37 38 REAR USB 39 ONBOARD LAN & IR USBFRONT CONNECTOR CONNECTOR PCI EXPRESS*1 SLOT 1,2,3 PCI EXPRESS*16 SLOT RESERVED Model Name: H915G 40 41 42 43 44 RESERVED ALL POWER ATX POWER CONN. AZALIA CODEC ALC880 AUDIO JACK ALC880 / ALC658 DDR CHANNEL A GMCH-GRANTSDALE_GND GMCH-GRANTSDALE_INT VGA GMCH-GRANTSDALE_PCI E, DMI P4_LGA775_D GDDR1 1.1 Cover Sheet Custom 1 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A BLOCK DIAGRAM PAGE 4, 5, 6VCC3 INTEL Pentium4LGA775 VCORE = 1.75V / SLEEP : 1.3V PAGE 7 ,8 ,9,10 VCORE = 1.75V / SLEEP : 1.3V GMCH GRANTSDALE 2_5VSTR = 2.5V(MEMORY) VDDQ = 1.5V (AGP POWER 4X, HUBLINK) PAGE 32,33,34 PWM/OTHER POWER VCORE = 1.75V (650-1100MHZ) / SLEEP : 1.3V VID0~4 2_5VSTR = 2.5V(MEMORY,SUSPEND POWER) PAGE 12 DDR SDRAM DIMM X 2 VTT_DDR = 1.25V MAA0~14 MDD0~63 -DQSD0~7 DM0~7 +12V = 12V VDDQ = 1.5V (AGP POWER 4X) PAGE 143VDUAL = 3.3V VCC3 = 3.3V VCC = 5V GAD0~31 AGPUSB+ / - SBA0~7 GCBE0~3- ST0~2 ADSTB0,ADSTB0- ADSTB1,ADSTB1- SBSTB,SBSTB- HL0~10 5VSB,-12V,+12V,VCC,VCC3,3VDUAL VTT_DDR,2_5VSTR PAGE 19 CLOCK GENERATOR CKVDD = 3.3V CONTROL BUS HUB LINK VCC3 = 3.3V 5VUSB = 5V AVDD = 5V VCC = 5V 5VSB = 5V RTCVDD = 3.3V PAGE 25, 26 -12 = -12V VCC = 5VVCC3 = 3.3V COMB PAGE 29 VCC = 5V COMA IR FRONT AUDIO VCC3 = 3V LPTTELE VBAT = 3V MIC 3VDUAL = 3.3V(SUSPEND POWER) LIN_ OUT 5VSB = 5V +12 = 12V AC97 LINK CD_IN PCI BUS AMRUSB+ / - AUX_IN LPC BUS VCC = 5V PAGE 22 ICH6 USB PORTS 0~7 +12V = 12V PS2 PAGE 20, 21 LINE_IN PAGE 15,16,17 PAGE 27 AUDIO PORTS : 3VDUAL = 3V LPC ITE8712HX I/O PORTS : PAGE 30, 31 FDD VCC25 = 2.5V(I/O,MEMORY/I,VLINK/I) PVCC = 5V PAGE 28 FRONT PANEL /CPU FAN +12 = 12V 5VSB = 5V VCC = 5V PCI SLOT 1,2,3 PCI EXPRESS MAA_CPC1~5 MAB_CPC1~5 2_5VSTR = 2.5V(MEMORY,SUSPEND POWER) PAGE 11 DDR SDRAM DIMM X 2 VTT_DDR = 1.25V CHANNEL A CHANNEL B IDE Primary PAGE 24VCC = 5V SERIAL ATA PAGE 16VCC = 5V PAGE 18, 23 FWH/HWMO VCC = 5V VCC3 = 3V PAGE 35 KINNERTH-R/NORTHWAYAC97/Azalia ALC880 BY 16 PORTS PCI EXPRESS BY 1SLOT GDDR1 1.1 BOM & PCB MODIFY HISTORY TOPSTAR DEVELOPER Custom 2 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTA R and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for w hich it w as obtained w ithout the expressed w ritten consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Version: 1.1 Component value changehistory Circuit or PCB layout changefor next version PAGE Change Item Reason Data Change Item Reason Model Name: H915G CHANGE CLOCK SOLUTION CHANGE AUDIO TO AC97 change TESHI0 pull up change LG775 PIN H29 NET "GTL_DET" change GMCH "MCH_GTLREF" config correct “-FPE” net GDDR1 1.1 BOM & PCB MODIFY HISTORY TOPSTAR DEVELOPER Custom 3 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Closed to Pin-H1 * GDDR1 1.1 P4_LGA775-A TOPSTAR DEVELOPER Custom 4 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd -HTRDY HA5 -HREQ3 HA7 -HLOCK -HINIT -CPURST -DEFER HA4 HA8 HA12 HA13 HA15 -HITM -BR0 -BNR HA3 HA[3..16] HA6 -RS0 -DBSY HA9 HA11 -HADS HA10 HA14 -HREQ2 HA16 -HADSTB1 -DRDY -HREQ0 -HREQ4 -IERR TESTHI10 TESTHI8 TESTHI9 -HREQ1 -HADSTB0 HA22 HA17 HA19 HA30 HA26 HA23 HA18 HA25 HA21 HA27 HA29 HA28 HA20 HA31 HA[17..31] HA24 -BPRI -RS1 -RS2 -HIT -EDRDY -HPCREQ TESTHI9 TESTHI10 TESTHI8 -IERR -BR0 GTLREF GTLREF -CPURST HA[3..16]9 -HADSTB19 -HTRDY 9 -CPURST 9 -HINIT 20 -DRDY 9 -DEFER 9 -DBSY 9 -BNR 9 -HADS 9 -HREQ49 -HREQ39 -HREQ29 -HREQ09 -RS0 9 -HLOCK 9 -BR0 9 -HREQ19 -HADSTB09 HA[17..31]9 -BPRI 9 -RS2 9 -RS1 9 -HIT 9 -HITM 9 -EDRDY 9 -HPCREQ9 VCORE VCORE VCORE VCORE VCORE VCORE VCORE VTT_GMCH VTT_OL VTT_OL VTT_OL VTT_OR R6 62 C1 220PF BC3 10UF/X5R/6.3V BC2 10UF/X5R/6.3V BC1 10UF/X5R/6.3V BC4 10UF/X5R/6.3V R7 62 C3 1UF/Y5V/10V BC13 10UF/X5R/6.3V BC14 10UF/X5R/6.3V BC15 10UF/X5R/6.3V BC12 10UF/X5R/6.3V C4 20PF BC17 10UF/X5R/6.3V BC30 10UF/X5R/6.3V BC20 10UF/X5R/6.3V BC19 10UF/X5R/6.3V R8 62 BC18 10UF/X5R/6.3V C2 33PF BC7 10UF/X5R/6.3V U1A LGA775 L5 P6 M5 L4 M4 R4 T5 U6 T4 U5 U4 V5 V4 W5 N4 P5 K4 J5 M6 K6 J6 R6 G5 AB6 W6 Y6 Y4 AA4 AD6 AA5 AB5 AC5 AB4 AF5 AF4 AG6 AG4 AG5 AH4 AH5 AJ5 AJ6 AC4 AE4 AD5 D2 C2 D4 H4 G8 E4 B2 C1 AB2 P3 C3 E3 AD3 G7 AB3 F2 U2 U3 F3 G3 G4 H5 J16 H15 H16 J17 H1 G23 B3 F5 A3 A03# A04# A05# A06# A07# A08# A09# A10# A11# A12# A13# A14# A15# A16# RSVDA1 RSVDA2 REQ0# REQ1# REQ2# REQ3# REQ4# ADSTB0# PCREQ# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# RSVDA3 RSVDA4 ADSTB1# ADS# BNR# HIT# RSP# BPRI# HITM# DBSY# DRDY# IERR# INIT# LOCK# TRDY# BINIT# DEFER# MCERR# EDRDY# AP0# AP1# BR0# TESTHI08 TESTHI09 TESTHI10 DP0# DP1# DP2# DP3# GTLREF RESET# RS0# RS1# RS2# BC10 10UF/X5R/6.3V BC5 10UF/X5R/6.3V BC8 10UF/X5R/6.3V BC6 10UF/X5R/6.3V BC31 10UF/X5R/6.3V BC16 10UF/X5R/6.3V BC23 10UF/X5R/6.3V BC22 10UF/X5R/6.3V BC25 10UF/X5R/6.3V NS BC27 10UF/X5R/6.3V BC21 10UF/X5R/6.3V BC28 10UF/X5R/6.3V BC9 10UF/X5R/6.3V BC26 10UF/X5R/6.3V NS BC24 10UF/X5R/6.3V BC29 10UF/X5R/6.3V R1 49.9,1% R2 100,1% BC11 0.01UF/X7R R3 62 R5 62 R4 62 PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Note: VCCA & VCOREPLL define doesn't same as old P4 design kit As close as possible to CPU socket Trace width doesn't less than 12 Mil Place outside of CPU socket Locate at ICH6 Side Intel SCH update GDDR1 1.1 P4_LGA775-B TOPSTAR DEVELOPER Custom 5 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd TESTHI11 -STPCLK -A20M COMP1 TDO VCCA NMI -TRST -SMI -BPM5 COMP0 -BPM4 VSSA INTR -BPM3 -BPM2 -BPM1 -BPM0 TCK TESTHI12 -THRMTRIP VID5 TMS VCCA -BPM2 -BPM1 -BPM0 TDO -BPM3 -BPM4 -BPM5 TDI VSSA -TRST TMS -FERR VCOREPLL VCOREPLL -IGNNE -CPUCLK CPUCLK VID1 VID3 VID2 VID4 VID0 VID[0..5] BOOTSEL COMP2 COMP3 CPUPWROK -PROCHOT -CPUSLP TESTHI12 TESTHI11 TESTHI1 TESTHI0 TESTHI1 LL_ID0 RSVD_AK6 RSVD_AK6 BOOTSEL RSVD_G6 TDO TDI TMS -BPM3 -BPM2 -BPM1 -BPM0 -BPM4 -BPM5 -ITP_RST BSEL0 BSEL1 BSEL2 -H_ITPCLK H_ITPCLK TDI TCK TESTHI2_7 -THRMTRIP TESTHI2_7 -CPUSLP -H_ITPCLK -ITP_RST H_ITPCLK -SYS_RST COMP2 COMP3 COMP1 COMP0 -FERR FSBSEL2 FSBSEL0 VID0 VID5 FSBSEL2 FSBSEL0 FSBSEL1 VID2 FSBSEL1 VID4 VID1 VID3 -TRST TCK CPUPWROK FSBSEL0 BSEL0 FSBSEL1 BSEL1 FSBSEL2 BSEL2 RSVD_G6 -PROCHOT -ITP_CLKN TESTHI0 ITP_CLKP -PROCHOT 32 -THRMTRIP 20 -STPCLK20 -A20M20 INTR20 NMI20 -SMI20 CPU_TEMP26,27 THERMDC26 -FERR20 -IGNNE20 CPUCLK23 -CPUCLK23 VID[0..5]8 -CPUSLP 20 VTT_PWRGD 37 XDP_4 12 XDP_18 12 XDP_28 12 MTYPE 12 EXP_SLR 12 XDP_36 12 XDP_6 12 -CPURST4,9 ITPCLK23 -ITPCLK23 -SYS_RST20,39 CPUPWROK 20 BSEL0 12 BSEL1 12 BSEL2 12 FSBSEL023 FSBSEL123 FSBSEL223 SMBDATA15,16,18,20,23,24,25,41 SMBCLK15,16,18,20,23,24,25,41 LL_ID0 8 VCC_SENSE8 VSS_SENSE8 GTL_DET[7,9] VTT_GMCH VTT_GMCH VCC3 VTT_OL VTT_OR VTT_OL VTT_OR VTT_GMCH VTT_OR VTT_OR VTT_OL VCC3 VCC3 R29 62 R31 0 U1C LGA775 P2 K3 R3 K1 L1 N2 M3 A23 B23 D23 C23 AM2 AL5 AM3 AL6 AK4 AL4 AM5 F28 G28 AE8 AL1 AK1 AN3 AN4 AN5 AN6 F29 F26 W3 P1 W2 F25 G25 G27 G26 G24 F24 L2 AH2 N1 AL2 M2 A13 T1 G2 R1 N5 AE6 C9 G10 D16 A20 E23 E24 F23 H2 J2 J3 Y1 V2 AA2 AK6 G6 SMI# A20M# FERR#/PBE# LINT0 LINT1 IGNNE# STPCLK# VCCA VSSA RSVDC1 VCCIOPLL VID0 VID1 VID2 VID3 VID4 VID5 RSVDC2 BCLK0 BCLK1 SKTOCC# THERMDA THERMDC VCC_SENSE VSS_SENSE RSVDC3 RSVDC4 VTT_PKGSENSE TESTHI00 TESTHI01 TESTHI11 TESTHI12 TESTHI02 TESTHI03 TESTHI04 TESTHI05 TESTHII06 TESTHI07 SLP# RSVDC7 PWRGOOD PROCHOT# THERMTRIP# COMP0 COMP1 COMP2 COMP3 RSVDC8 RSVDC9 RSVDC10 RSVDC11 RSVDC12 RSVDC13 N/CC1 N/CC2 N/CC3 N/CC4 N/CC5 N/CC6 BOOTSELECT LL_ID0 LL_ID1 RSVDC5 RSVDC6 R50 0 R25 62 R32 0 R51 0 R28 62 R30 100 R37 62 NS R53 10K R35 120 NS U1D LGA775 AE1 AD1 AF1 AC1 AG1 AJ2 AJ1 AD2 AG2 AF2 AG3 AC2 G29 H30 G30 AK3 AJ3 A29 B25 B29 B30 C29 A26 B27 C28 A25 A28 A27 C30 A30 C25 C26 C27 B26 D27 D28 D25 D26 B28 D29 D30 AM6 AA1 J1 F27 TCK TDI TDO TMS TRST# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# DBR# BSEL0 BSEL1 BSEL2 ITPCLK0 ITPCLK1 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTTPWRGD VTT_OUT1 VTT_OUT2 VTT_SEL R54 10K + EC5 100UF R55 10K R52 1K NS BC33 10UF/X5R/6.3V NS R42 51 C305 0.1UF/Y5V/50V R41 51 R40 51 R43 51 R20 470 R19 470 R17 0 R36 62 NS C5 0.1UF/Y5V/50V R22 62 C304 0.1UF/Y5V/50V R24 62 R48 51 C6 1UF/Y5V/10V R680 110,1% L1 10UH/8/S 0.1UF C3751 2 R681 61.9,1% C8 1000PF L2 10UH/8/S C9 1000PF R14 60.4,1% R15 60.4,1% R827 249,1% R39 51 RN1 680/8P4R 1 2 3 4 5 6 7 8 R34 680 R33 680 R38 51 C10 33PF 0.1UFC374 1 2 C7 1UF/Y5V/10V R44 51 BC34 1000PF R21 470 R49 51 R45 51 R26 62 NS R46 51 R10 100,1% R11 100,1% R27 62Q86 2N7002 3 1 2 PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A GDDR1 1.1 P4_LGA775-C TOPSTAR DEVELOPER Custom 6 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd HD0 HD26 HD28 HD31 HD24 HD27 HD29 HD25 HD30 HD18 HD20 HD23 HD16 HD19 HD21 HD17 HD22 -DBI0 STBP0 STBN0 -DBI1 STBP1 STBN1 HD42 HD44 HD47 HD40 HD43 HD45 HD41 HD46 HD34 HD36 HD39 HD32 HD35 HD37 HD33 HD38 HD62 -DBI2 HD60 HD63 STBP2 HD61 STBN2 HD54 HD56 HD59 HD52 HD55 HD57 HD53 HD58 STBN3 HD48 HD51 -DBI3 HD49 STBP3 HD50 HD[16..31] HD15 HD7 HD5 HD9 HD6 HD11 HD1 HD14 HD13 HD8 HD12 HD4 HD10 HD[0..15] HD2 HD3 HD[0..15]9 HD[16..31]9 -DBI09 STBN09 STBP09 -DBI19 STBP19 STBN19 -DBI3 9 STBN3 9 STBP3 9 -DBI2 9 STBN2 9 STBP2 9 HD[48..63] 9 HD[32..47] 9 U1B LGA775 B4 C5 A4 C6 A5 B6 B7 A7 A10 A11 B10 C11 D8 B12 C12 D11 G9 F8 F9 E9 D7 E10 D10 F11 F12 D13 E13 G13 F14 G14 F15 G15 G16 E15 E16 G18 G17 F17 F18 E18 E19 F20 E21 F21 G21 E22 D22 G22 D20 D17 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B19 A19 A22 B22 A8 C8 B9 G11 G12 E12 D19 G20 G19 C20 A16 C17 D00# D01# D02# D03# D04# D05# D06# D07# D08# D09# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBI0# DSTBN0# DSTBP0 DBI1# DSTBN1# DSTBP1 DBI2# DSTBN2# DSTBP2 DBI3# DSTBN3# DSTBP3 PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A GDDR1 1.1 P4_LGA775-D TOPSTAR DEVELOPER Custom 7 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd GTL_DET[5,9] VCORE VCORE VCORE VCORE U1E LGA775 AA8 AB8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD8 AE11 AE12 AE14 AE15 AE18 AE19 AE21 AE22 AE23 AE9 AF11 AF12 AF14 AF15 AF18 AF19 AF21 AF22 AF8 AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30 AG8 AG9 AH11 AH12 AH14 AH15 AH18 AH19 AH21 AH22 AH25 AH26 AH27 AH28 AH29 AH30 AH8 AH9 AJ11 AJ12 AJ14 AJ15 AJ18 AJ19 AJ21 AJ22 AJ25 AJ26 AJ8 AJ9 AK11 AK12 AK14 AK15 AK18 AK19 AK21 AK22 AK25 AK26 AK8 AK9 AL11 AL12 AL14 AL15 AL18 AL19 AL21 AL22 AL25 AL26 AL29 AL30 AL8 AL9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U1F LGA775 AM11 AM12 AM14 AM15 AM18 AM19 AM21 AM22 AM25 AM26 AM29 AM30 AM8 AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN29 AN30 AN8 AN9 J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J8 J9 K23 K24 K25 K26 K27 K28 K29 K30 K8 L8 M23 M24 M25 M26 M27 M28 M29 M30 M8 N23 N24 N25 N26 N27 N28 N29 N30 N8 P8 R8 T23 T24 T25 T26 T27 T28 T29 T30 T8 U23 U24 U25 U26 U27 U28 U29 U30 U8 V8 W23 W24 W25 W26 W27 W28 W29 W30 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y8 W8 AE3 B13 D1 D14 E5 E6 E7 F6 T2 V1 W1 Y3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC EMPAE3 EMPTB13 EMPTD1 EMPTD14 EMPTE5 EMPTE6 EMPTE7 EMPTF6 EMPTT2 EMPTV1 EMPTW1 EMPTY3 U1G LGA775 A12 A15 A18 A2 A21 A24 A6 A9 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB7 AC3 AC6 AC7 AD4 AD7 AE10 AE13 AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE5 AE7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AF7 AG10 AG13 AG16 AG17 AG20 AG23 AG24 AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AH7 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28 AJ29 AJ30 AJ4 AJ7 AK13 AK16 AK17 AK2 AK20 AK23 AK24 AK27 AK28 AK29 AK30 AK5 AK7 AL10 AL13 AL16 AL17 AL20 AL23 AL24 AL27 AL28 AL3 AL7 AM1 AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28 AM4 AM7 AK10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U1H LGA775 AN1 AN10 AN13 AN16 AN17 AN2 AN20 AN23 AN24 AN27 AN28 AN7 B1 B11 B14 B17 B20 B24 B5 B8 C10 C13 C16 C19 C22 C24 C4 C7 D12 D15 D18 D21 D24 D3 D5 D6 D9 E11 E14 E17 E2 E20 E25 E26 E27 E28 E29 E8 F10 F13 F16 F19 F22 F4 F7 G1 H10 H11 H12 H13 H14 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H3 H6 H7 H8 H9 J4 J7 K2 K5 K7 L23 L24 L25 L26 L27 L28 L29 L3 L30 L6 L7 M1 M7 N3 N6 N7 P23 P24 P25 P26 P27 P28 P29 P30 P4 P7 R2 R23 R24 R25 R26 R27 R28 R29 R30 R5 R7 T3 T7 U1 U7 V23 V24 V25 V26 V27 V28 V29 V3 V30 V6 V7 W4 W7 Y2 Y5 Y7 T6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A GDDR1 1.1 VRD 10.1 TOPSTAR DEVELOPER C 8 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd PDF created with pdfFactory trial version www.pdffactory.com 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CPU INTERFACE GDDR1 1.1 GMCH-HOST TOPSTAR DEVELOPER Custom 9 43Tuesday, December 28, 2004 Page Name Size Project Name Rev Date: Sheet of PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR ShenZhen Topstar Inductor Co.,Ltd HA[3..31] HD43 HD15 HD0 HD58 HD53 HD46 HD38 HD33 HD31 HD13 HA31 HA11 HD52 HD3 HA15 HSWNGHD28 MCH_GTLREF HD32 HD23 HA14 HA6 HD47 HD21 HD17 HD9 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