FM25V02_001-84494

This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-84494 Rev. *B Revised June 30, 2013 FM25V02 256Kb Serial 3V F-RAM Memory Features 256K bit Ferroelectric Nonvolatile RAM Organized as 32,768 x 8 bits High Endurance 100 Trillion (1014) Read/Writes 10 Year Data Retention NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI Up to 40 MHz Frequency Direct Hardware Replacement for Serial Flash SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme Hardware Protection Software Protection Device ID Device ID reads out Manufacturer ID & Part ID Low Voltage, Low Power Low Voltage Operation 2.0V – 3.6V 90 A Standby Current (typ.) 5 A Sleep Mode Current (typ.) Industry Standard Configurations Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC Package 8-pin “Green”/RoHS TDFN Package Description The FM25V02 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories. Unlike Serial Flash, the FM25V02 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been transferred to the device. The next bus cycle may commence without the need for data polling. The product offers very high write endurance, orders of magnitude more endurance than Serial Flash. Also, F-RAM exhibits lower power consumption than Serial Flash. These capabilities make the FM25V02 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of Serial Flash can cause data loss. The FM25V02 provides substantial benefits to users of Serial Flash as a hardware drop-in replacement. The devices use the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. Both devices incorporate a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The devices are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration S Q W VSS VDD HOLD C D 1 2 3 4 8 7 6 5 Pin Name Function /S Chip Select /W Write Protect /HOLD Hold C Serial Clock D Serial Data Input Q Serial Data Output VDD Supply Voltage VSS Ground /S Q /W VSS VDD /HOLD C D 8 7 6 5 1 2 3 4 Top View FM25V02 - 256Kb SPI FRAM Document Number: 001-84494 Rev. *B Page 2 of 19 Instruction Decode Clock Generator Control Logic Write Protect Instruction Register Address Register Counter 4096 x 64 FRAM Array 15 Data I/O Register 8 Nonvolatile Status Register 3 W S C QD HOLD Figure 1. Block Diagram Pin Descriptions Pin Name I/O Description /S Input Chip Select: This active-low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the C signal. A falling edge on /S must occur prior to every op-code. C Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 40 MHz and may be interrupted at any time. /HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on C or /S. All transitions on /HOLD must occur while C is low. This pin has a weak internal pull-up (see RIN spec, pg 11). However, if it is not used, the /HOLD pin should be tied to VDD. /W Input Write Protect: This active-low pin prevents write operations to the Status Register only. A complete explanation of write protection is provided on pages 6 and 7. If not used, the /W pin should be tied to VDD. D Input Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of C and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * D may be connected to Q for a single pin data interface. Q Output Serial Output: This is the data output pin. It is driven during a read and remains tri- stated at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * Q may be connected to D for a single pin data interface. VDD Supply Power Supply VSS Supply Ground FM25V02 - 256Kb SPI FRAM Document Number: 001-84494 Rev. *B Page 3 of 19 Overview The FM25V02 is a serial F-RAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is similar to Serial Flash. The major differences between the FM25V02 and a Serial Flash with the same pinout are the F-RAM‟s superior write performance, very high endurance, and lower power consumption. Memory Architecture When accessing the FM25V02, the user addresses 32K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two- byte address. The complete address of 15-bits specifies each byte address uniquely. Most functions of the FM25V02 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike Serial Flash, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25V02 due to its fast write cycle and high endurance as compared to Serial Flash. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than Serial Flash since it is completed quickly. By contrast, Serial Flash requiring milliseconds to write is vulnerable to noise during much of the cycle. Serial Peripheral Interface – SPI Bus The FM25V02 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 40MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25V02 operates in SPI Mode 0 and 3. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25V02 will begin monitoring the clock and data lines. The relationship between the falling edge of /S, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25V02 supports only modes 0 and 3. Figure 2 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25V02 on the rising edge of C and data is expected on the first rising edge after /S goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /S is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Certain op-codes are commands with no subsequent data transfer. The /S must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select. SPI Mode 0: CPOL=0, CPHA=0 S C D MSB LSB 7 6 5 4 3 2 1 0 SPI Mode 3: CPOL=1, CPHA=1 S C D MSB LSB 7 6 5 4 3 2 1 0 Figure 2. SPI Modes 0 & 3 FM25V02 - 256Kb SPI FRAM Document Number: 001-84494 Rev. *B Page 4 of 19 System Hookup The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25V02 devices with a microcontroller that has a dedicated SPI port, as Figure 3 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25V02 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 4 shows a configuration that uses only three pins. SPI Microcontroller FM25V02 Q D C S HOLD FM25V02 Q D C S HOLD SCK MOSI MISO SS1 SS2 HOLD1 HOLD2 MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select Figure 3. System Configuration with SPI port Microcontroller FM25V02 Q D C S HOLD P1.0 P1.1 P1.2 Vdd Figure 4. System Configuration without SPI port FM25V02 - 256Kb SPI FRAM Document Number: 001-84494 Rev. *B Page 5 of 19 Power Up to First Access The FM25V02 is not accessible for a period of time (tPU) after power up. Users must comply with the timing parameter tPU, which is the minimum time from VDD (min) to the first /S low. Data Transfer All data transfers to and from the FM25V02 occur in 8-bit groups. They are synchronized to the clock signal (C), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of C. Outputs are driven from the falling edge of clock C. Command Structure There are ten commands called op-codes that can be issued by the bus master to the FM25V02. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function, such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the Status Register. The third group includes commands for memory transactions followed by address and one or more bytes of data. Table 1. Op-code Commands Name Description Op-code WREN Set Write Enable Latch 0000 0110b WRDI Write Disable 0000 0100b RDSR Read Status Register 0000 0101b WRSR Write Status Register 0000 0001b READ Read Memory Data 0000 0011b FSTRD Fast Read Memory Data 0000 1011b WRITE Write Memory Data 0000 0010b SLEEP Enter Sleep Mode 1011 1001b RDID Read Device ID 1001 1111b SNR Read S/N 1100 0011b WREN – Set Write Enable Latch The FM25V02 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the Status Register (WRSR) and writing the memory (WRITE). Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the Status Register has no effect on the state of this bit. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 below illustrates the WREN command bus configuration. 0 0 0 0 0 1 1 0 S C D Q Hi-Z 0 1 2 3 4 5 6 7 Figure 5. WREN Bus Configuration WRDI – Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the Status Register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration. 0 0 0 0 0 1 0 0 S C D Q Hi-Z 0 1 2 3 4 5 6 7 Figure 6. WRDI Bus Configuration RDSR – Read Status Register The RDSR command allows the bus master to verify the contents of the Status Register. Reading Status provides information about the current state of the write protection features. Following the RDSR op-code, the FM25V02 will return one byte with the contents of the Status Register. The Status Register is described in detail in the section below. FM25V02 - 256Kb SPI FRAM Document Number: 001-84494 Rev. *B Page 6 of 19 WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status Register. Prior to issuing a WRSR command, the /W pin must be high or inactive. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. The bus configuration of RDSR and WRSR are shown below. Figure 7. RDSR Bus Configuration Figure 8. WRSR Bus Configuration Status Register & Write Protection The write protection features of the FM25V02 are multi-tiered. Taking the /W pin to a logic low state is the hardware write-protect function. Status Register write operations are blocked when /W is low. To write the memory with /W high, a WREN op-code must first be issued. Assuming that writes are enabled using WREN and by /W, writes to memory are controlled by the Status Register. As described above, writes to the Status Register are performed using the WRSR command and subject to the /W pin. The Status Register is organized as follows. Table 2. Status Register Bit 7 6 5 4 3 2 1 0 Name WPEN 0 0 0 BP1 BP0 WEL 0 Bits 0 and 4-6 are fixed at 0, and cannot can be modified. Note that bit 0 (“Ready” in Serial Flash) is unnecessary as the F-RAM writes in real-time and is never busy, so it reads out as a „0‟. There is an exception to this when the device is waking up from Sleep Mode, which is described on the following page. The BP1 and BP0 control software write protection features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the Status Register has no effect on its state. This bit is internally set and cleared via the WREN and WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write- protected as shown in the following table. Table 3. Block Memory Write Protection BP1 BP0 Protected Address Range 0 0 None 0 1 6000h to 7FFFh (upper ¼) 1 0 4000h to 7FFFh (upper ½) 1 1 0000h to 7FFFh (all) The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The WPEN bit controls the effect of the hardware /W pin. When WPEN is low, the /W pin is ignored. When WPEN is high, the /W pin controls write access to the Status Register. Thus the Status Register is write protected if WPEN=1 and /W=0. This scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. This occurs if the BP1 and BP0 bits are set to 1, the WPEN bit is set to 1, and S C D Q S C D Q FM25V02 - 256Kb SPI FRAM Document Number: 001-84494 Rev. *B Page 7 of 19 the /W pin is low. This occurs because the block protect bits prevent writing memory and the /W signal in hardware prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions. Table 4. Write Protection WEL WPEN /W Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected Memory Operation The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike Serial Flash, the FM25V02 can perform sequential writes at bus speed. No page buffer is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code is followed by a two-byte address value, which specifies the 15-bit address of the first data byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. A write operation is shown in Figure 9. Unlike Serial Flash, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). The rising edge of /S terminates a WRITE op-code operation. Asserting /W active in the middle of a write operation will have no effect until the next falling edge of /S. Read Operation After the falling edge of /S, the bus master can issue a READ op-code. Following this instruction is a two- byte address value (A14-A0), specifying the address of the first data byte of the read operation. After the op-code and address are complete, the D pin is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /S terminates a READ op- code operation and tri-states the Q pin. A read operation is shown in Figure 10. Fast Re