AD8307

Low Cost, DC to 500 MHz, 92 dB Logarithmic Amplifier AD8307 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1997–2008 Analog Devices, Inc. All rights reserved. FEATURES Complete multistage logarithmic amplifier 92 dB dynamic range: –75 dBm to +17 dBm to –90 dBm using matching network Single supply of 2.7 V minimum at 7.5 mA typical DC to 500 MHz operation, ±1 dB linearity Slope of 25 mV/dB, intercept of −84 dBm Highly stable scaling over temperature Fully differential dc-coupled signal path 100 ns power-up time, 150 μA sleep current APPLICATIONS Conversion of signal level to decibel form Transmitter antenna power measurement Receiver signal strength indication (RSSI) Low cost radar and sonar signal processing Network and spectrum analyzers (to 120 dB) Signal level determination down to 20 Hz True decibel ac mode for multimeters FUNCTIONAL BLOCK DIAGRAM BAND GAP REFERENCE AND BIASING SIX 14.3dB 900MHz AMPLIFIER STAGES MIRROR INPUT-OFFSET COMPENSATION LOOP COM INM INP ENBVPS INT OUT OFS AD8307 7.5mA 1.1kΩ 3 2 2µA /dB 12.5kΩ COM NINE DETECTOR CELLS SPACED 14.3dB –INP +INP 8 1 2 7 5 6 4 3 01 08 2- 00 1 Figure 1. GENERAL DESCRIPTION The AD8307 is the first logarithmic amplifier made available in an 8-lead (SOIC_N) package. It is a complete 500 MHz monolithic demodulating logarithmic amplifier based on the progressive compression (successive detection) technique, providing a dynamic range of 92 dB to ±3 dB law-conformance and 88 dB to a tight ±1 dB error bound at all frequencies up to 100 MHz. It is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 7.5 mA is needed, corresponding to an unprecedented power consumption of only 22.5 mW at 3 V. A fast acting CMOS- compatible control pin can disable the AD8307 to a standby current of less than 150 μA. Each of the cascaded amplifier/limiter cells has a small signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz. The input is fully differential and at a moderately high impedance (1.1 kΩ in parallel with about 1.4 pF). The AD8307 provides a basic dynamic range extending from approximately −75 dBm (where dBm refers to a 50 Ω source, that is, a sine amplitude of about ±56 μV) up to +17 dBm (a sine amplitude of ±2.2 V). A simple input matching network can lower this range to –88 dBm to +3 dBm. The logarithmic linearity is typically within ±0.3 dB up to 100 MHz over the central portion of this range, and degrades only slightly at 500 MHz. There is no minimum frequency limit. The AD8307 can be used at audio frequencies of 20 Hz or lower. The output is a voltage scaled 25 mV/dB, generated by a current of nominally 2 μA/dB through an internal 12.5 kΩ resistor. This voltage varies from 0.25 V at an input of −74 dBm (that is, the ac intercept is at −84 dBm, a 20 μV rms sine input), up to 2.5 V for an input of +16 dBm. This slope and intercept can be trimmed using external adjustments. Using a 2.7 V supply, the output scaling can be lowered, for example to 15 mV/dB, to permit utilization of the full dynamic range. The AD8307 exhibits excellent supply insensitivity and temperature stability of the scaling parameters. The unique combination of low cost, small size, low power consumption, high accuracy and stability, very high dynamic range, and a frequency range encompassing audio through IF to UHF makes this product useful in numerous applications requiring the reduction of a signal to its decibel equivalent. The AD8307 operates over the industrial temperature range of −40°C to +85°C, and is available in 8-lead SOIC and 8-lead PDIP packages. AD8307 Rev. D | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications ..................................................................................... 3  Absolute Maximum Ratings ............................................................ 4  ESD Caution .................................................................................. 4  Pin Configuration and Function Descriptions ............................. 5  Typical Performance Characteristics ............................................. 6  Log Amp Theory .............................................................................. 9  Progressive Compression .......................................................... 10  Demodulating Log Amps .......................................................... 11  Intercept Calibration .................................................................. 12  Offset Control ............................................................................. 12  Extension of Range ..................................................................... 13  Interfaces .......................................................................................... 14  Enable Interface .......................................................................... 14  Input Interface ............................................................................ 14  Offset Interface ........................................................................... 15  Output Interface ......................................................................... 15  Theory of Operation ...................................................................... 17  Basic Connections ...................................................................... 17  Input Matching ........................................................................... 18  Narrow-Band Matching ............................................................ 18  Slope and Intercept Adjustments ............................................. 19  Applications Information .............................................................. 20  Buffered Output .......................................................................... 20  Four-Pole Filter ........................................................................... 20  1 μW to 1 kW 50 Ω Power Meter ............................................. 21  Measurement System with 120 dB Dynamic Range .............. 21  Operation at Low Frequencies .................................................. 22  Outline Dimensions ....................................................................... 23  Ordering Guide .......................................................................... 24  REVISION HISTORY 7/08—Rev. C to Rev. D Deleted DC-Coupled Applications Section ................................ 22 Deleted Operation Above 500 MHz Section .............................. 23 Updated Outline Dimensions ....................................................... 23 10/06—Rev. B to Rev. C Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Changes to Offset Interface ........................................................... 15 Changes to Output Interface ......................................................... 15 Updated captions to Outline Dimensions ................................... 24 Changes to Ordering Guide .......................................................... 24 6/03—Rev. A to Rev. B Renumbered TPCs and Figures ........................................ Universal Changes to Ordering Guide ............................................................ 3 Changes to Figure 24 ...................................................................... 17 Deleted Evaluation Board Information ....................................... 18 Updated Outline Dimensions ....................................................... 19 AD8307 Rev. D | Page 3 of 24 SPECIFICATIONS VS = 5 V, TA = 25°C, RL ≥ 1 MΩ, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit GENERAL CHARACTERISTICS Input Range (±3 dB Error) From noise floor to maximum input 92 dB Input Range (±1 dB Error) From noise floor to maximum input 88 dB Logarithmic Conformance f ≤ 100 MHz, central 80 dB ±0.3 ±1 dB f = 500 MHz, central 75 dB ±0.5 dB Logarithmic Slope Unadjusted1 23 25 27 mV/dB vs. Temperature 23 27 mV/dB Logarithmic Intercept Sine amplitude, unadjusted2 20 μV Equivalent sine power in 50 Ω −87 −84 −77 dBm vs. Temperature −88 −76 dBm Input Noise Spectral Density Inputs shorted 1.5 nV/√Hz Operating Noise Floor RSOURCE = 50 Ω/2 −78 dBm Output Resistance Pin 4 to ground 10 12.5 15 kΩ Internal Load Capacitance 3.5 pF Response Time Small signal, 10% to 90%, 0 mV to 100 mV, CL = 2 pF 400 ns Large signal, 10% to 90%, 0 V to 2.4 V, CL = 2 pF 500 ns Upper Usable Frequency 500 MHz Lower Usable Frequency AC-coupled input 10 Hz AMPLIFIER CELL CHARACTERISTICS Cell Bandwidth −3 dB 900 MHz Cell Gain 14.3 dB INPUT CHARACTERISTICS DC Common-Mode Voltage AC-coupled input 3.2 V Common-Mode Range Either input (small signal) −0.3 +1.6 VS − 1 V DC Input Offset Voltage3 RSOURCE ≤ 50 Ω 50 500 μV Drift 0.8 μV/°C Incremental Input Resistance Differential 1.1 kΩ Input Capacitance Either pin to ground 1.4 pF Bias Current Either input 10 25 μA POWER INTERFACES Supply Voltage 2.7 5.5 V Supply Current VENB ≥ 2 V 8 10 mA Disabled VENB ≤ 1 V 150 750 μA 1 This can be adjusted downward by adding a shunt resistor from the output to ground. A 50 kΩ resistor reduces the nominal slope to 20 mV/dB. 2 This can be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V. 3 Normally nulled automatically by internal offset correction loop and can be manually nulled by a voltage applied between Pin 3 and ground; see the Applications Information section. AD8307 Rev. D | Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Ratings Supply 7.5 V Input Voltage (Pin 1 and Pin 8) VSUPPLY Storage Temperature Range (N, R) −65°C to +125°C Ambient Temperature Range, Rated Performance Industrial, AD8307AN, AD8307AR −40°C to +85°C Lead Temperature Range (Soldering, 10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings can cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability. ESD CAUTION AD8307 Rev. D | Page 5 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INP VPS ENB INT COM OFS OUT INM AD8307 TOP VIEW (Not to Scale) 1 2 3 4 8 7 6 5 01 08 2- 00 2 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 INM Signal Input Minus Polarity. Normally at VPOS/2. 2 COM Common Pin (Usually Grounded). 3 OFS Offset Adjustment. External capacitor connection. 4 OUT Logarithmic (RSSI) Output Voltage. ROUT = 12.5 kΩ. 5 INT Intercept Adjustment, ±3 dB. (See the Slope and Intercept Adjustments section.) 6 ENB CMOS-Compatible Chip Enable. Active when high. 7 VPS Positive Supply: 2.7 V to 5.5 V. 8 INP Signal Input Plus Polarity. Normally at VPOS/2. Due to the symmetrical nature of the response, there is no special significance to the sign of the two input pins. DC resistance from INP to INM = 1.1 kΩ. AD8307 Rev. D | Page 6 of 24 TYPICAL PERFORMANCE CHARACTERISTICS 8 3 0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 7 4 2 1 6 5 1.8 1.9 2.0 01 08 2- 00 3 SU PP LY C U R R EN T (m A ) VENB (V) Figure 3. Supply Current vs. VENB (5 V) 8 3 0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 7 4 2 1 6 5 1.8 1.9 2.0 01 08 2- 00 4 SU PP LY C U R R EN T (m A ) VENB (V) Figure 4. Supply Current vs. VENB (3 V) 3 2 –3 200–20–40–60–80 1 0 –1 –2 INPUT FREQUENCY = 100MHz INPUT FREQUENCY = 300MHz 01 08 2- 00 5 ER R O R (d B ) INPUT LEVEL (dBm) Figure 5. Log Conformance vs. Input Level (dBm), 100 MHz and 300 MHz 3 2 –3 200–20–40–60–80 1 0 –1 –2 01 08 2- 00 6 ER R O R (d B ) INPUT LEVEL (dBm) TEMPERATURE ERROR @ –40°C TEMPERATURE ERROR @ +25°C TEMPERATURE ERROR @ +85°C Figure 6. Log Conformance vs. Input Level (dBm) at −40°C, +25°C, and +85°C INPUT FREQUENCY 10MHz INPUT FREQUENCY 100MHz INPUT FREQUENCY 300MHz INPUT FREQUENCY 500MHz 3 0 200–20–40–60–80 2 1 01 08 2- 00 7 V O U T (V ) INPUT LEVEL (dBm) Figure 7. VOUT vs. Input Level (dBm) at Various Frequencies CFO VALUE = 0.01µF CFO VALUE = 1µF CFO VALUE = 0.1µF 1.5 1.0 –1.5 200–20–40–60–80 0.5 0 –0.5 –1.0 01 08 2- 00 8 ER R O R (d B ) INPUT LEVEL (dBm) Figure 8. Log Conformance vs. CFO Values at 1 kHz Input Frequency AD8307 Rev. D | Page 7 of 24 3.0 0 0.5 200–20 –10 10–40–60–80 –70 –50 –30 2.0 1.0 2.5 1.5 01 08 2- 00 9 V O U T (V ) INPUT LEVEL (dBm) INT PIN = 3.0V 10MHz, INT = –96.52dBm INT PIN = 4.0V 10MHz, INT = –87.71dBm NO CONNECT ON INT 10MHz, INT = –82.90dBm Figure 9. VOUT vs. Input Level at 5 V Supply; Showing Intercept Adjustment 3.0 0 0.5 0–20 –10 10–40–60–80 –70 –50 –30 2.0 1.0 2.5 1.5 01 08 2- 01 0 V O U T (V ) INPUT LEVEL (dBm) INT VOLTAGE INT = 1.0V, INT = –86dBm INT VOLTAGE INT NO CONNECT, INT = –71dBm INT VOLTAGE INT = 2.0V, INT = –78dBm Figure 10. VOUT vs. Input Level at 3 V Supply Using AD820 as Buffer, Gain = +2; Showing Intercept Adjustment 2.5 0 200–20–40–60–80 2.0 1.0 1.5 0.5 01 08 2- 01 1 V O U T (V ) INPUT LEVEL (dBm) 100MHz @ –40°C 100MHz @ +85°C 100MHz @ +25°C Figure 11. VOUT vs. Input Level at Three Temperatures (−40°C, +25°C, +85°C) –INPUT +INPUT 100MHz 3 2 –3 200–20–40–60–80 1 0 –1 –2 ER R O R (d B ) INPUT LEVEL (dBm) 01 08 2- 01 2 Figure 12. Log Conformance vs. Input Level at 100 MHz Showing Response to Alternative Inputs 3 2 –3 10–10–30–50–70–90 1 0 –1 –2 ER R O R (d B ) INPUT LEVEL (dBm) 01 08 2- 01 3 100MHz 500MHz Figure 13. Log Conformance vs. Input Level at 100 MHz and 500 MHz; Input Driven Differentially Using Transformer 3 2 –3 100–10–20 20–30–40–50–60–70 1 0 –1 –2 ER R O R (d B ) INPUT LEVEL (dBm) 01 08 2- 01 4 100MHz 500MHz 10MHz Figure 14. Log Conformance vs. Input Level at 3 V Supply Using AD820 as Buffer, Gain = +2 AD8307 Rev. D | Page 8 of 24 VENB CH 2 VOUT CH 1 GND 01 08 2- 01 5 500nsCH2 2.00V CH1 200mV Figure 15. Power-Up Response Time VENB CH 2 VOUT CH 1 GND 01 08 2- 01 6 500nsCH2 2.00V CH1 200mV Figure 16. Power-Down Response Time AD8307 0.1µF VPS = 5.0V 1nF 1nF 52.3Ω HP8648B SIGNAL GENERATOR RF OUT OUT HP8112A PULSE GENERATOR TEK P6139A 10x PROBE SYNCH OUT TRIG NC INP VPS ENB INT INM COM OFS OUT NC NC = NO CONNECT 8 7 6 5 2 3 41 TEK744A SCOPE 01 08 2- 01 7 Figure 17. Test Setup for Power-Up/Power-Down Response Time INPUT SIGNAL CH2 CH1 GND 2V VOUT CH1 CH2 GND 01 08 2- 01 8 200nsCH2 1.00V CH1 500mV Figure 18. VOUT Rise Time INPUT SIGNAL CH2 2.5V CH1 GND VOUT CH1 CH2 GND 01 08 2- 01 9 200nsCH2 1.00V CH1 500mV Figure 19. Large Signal Response Time PULSE MODE IN 10MHz REF CLK OUT EXT TRIG AD8307 0.1µF VPS = 5.0V 1nF 1nF 52.3Ω HP8648B SIGNAL GENERATOR PULSE MODULATION MODE RF OUT HP8112A PULSE GENERATOR TEK P6204 FET PROBE TRIG OUT TRIG NC INP VPS ENB INT INM COM OFS OUT NC NC = NO CONNECT 8 7 6 5 2 3 41 TEK744A SCOPE 01 08 2- 02 0 Figure 20. Test Setup for VOUT Pulse Response AD8307 Rev. D | Page 9 of 24 LOG AMP THEORY Logarithmic amplifiers perform a more complex operation than that of classical linear amplifiers, and their circuitry is significantly different. A good grasp of what log amps do and how they work can prevent many pitfalls in their application. The essential purpose of a log amp is not to amplify, though amplification is utilized to achieve the function. Rather, it is to compress a signal of wide dynamic range to its decibel equivalent. It is thus a measurement device. A better term may be logarithmic converter, because its basic function is the conversion of a signal from one domain of representation to another via a precise nonlinear transformation. Logarithmic compression leads to situations that can be confusing or paradoxical. For example, a voltage offset added to the output of a log amp is equivalent to a gain increase ahead of its input. In the usual case where all the variables are voltages, and regardless of the particular structure, the relationship between the variables can be expressed as )/(log XINYOUT VVVV = (1) where: VOUT is the output voltage. VY is the slope voltage; the logarithm is usually taken to base 10 (in which case VY is also the volts per decade). VIN is the input voltage. VX is the intercept voltage. All log amps implicitly require two references, in this example, VX and VY, which determine the scaling of the circuit. The abso- lute accuracy of a log amp cannot be any better than the accuracy of its scaling references. Equation 1 is mathematically incomplete in representing the behavior of a demodulating log amp, such as the AD8307, where VIN has an alternating sign. However, the basic principles are unaffected, and this can be safely used as the starting point in the analyses of log amp scaling. VOUT 5VY 4VY 3VY 2VY –2VY VY VOUT = 0 VSHIFT LOWER INTERCEPT VIN = VX 0dBc VIN = 102VX +40dBc VIN = 104VX +80dBc LOG VIN 01 08 2- 02 1 VIN = 10–2VX –40dBc Figure 21. Ideal Log Amp Function Figure 21 shows the input/output relationship of an ideal log amp, conforming to Equation 1. The horizontal scale is logarithmic and spans a wide dynamic range, shown in Figure 21 as over 120 dB, or six decades. The output passes through zero (the log intercept) at the unique value VIN = VX and ideally becomes negative for inputs below the intercept. In the ideal case, the straight line describing VOUT for all values of VIN continues indefinitely in both directions. The dotted line shows that the effect of adding an offset voltage, VSHIFT, to the output is to lower the effective intercept voltage, VX. Exactly the same alteration can be achieved by raising the gain (or signal level) ahead of the log amp by the factor, VSHIFT/VY. For example, if VY is 500 mV per decade (25 mV/dB), an offset of 150 mV added to the output appears to lower the intercept by two