Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture

800 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 of layers. For example, for three-layer routing, the circuit s38584 would need about (496=2) � 3 = 744MB. V. CONCLUSION We have proposed a novel multilevel routing frameworkMR consid- ering both routability and performance. Unlike the previous multilevel routing, MR integrates global routing, detailed routing, and resource estimation together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facil- itating the solution refinement during uncoarsening. The exact routing information at each level makes our frameworkmore flexible in dealing with various routing objectives (such as crosstalk, power, etc.). Exper- imental results have shown that MR is very promising. Future work lies in the development of a timing-drivenmultilevel router considering signal integrity. ACKNOWLEDGMENT The authors would like to thank the authors of [5], Prof. J. Cong, J. Fang, and Y. Zhang, for providing the benchmark circuits. Special thanks go to Y. Zhang for her prompt explanations of their data and very helpful discussions. They also thank the anonymous reviewers for their very constructive comments. REFERENCES [1] C. Albrecht, “Global routing by new approximation algorithms for mul- ticommodity flow,” IEEE Trans. Computer-Aided Design, vol. 20, pp. 622–632, May 2001. [2] C. J. Alpert, J.-H. Huang, and A. B. Kahng, “Multilevel circuit parti- tioning,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 655–667, Aug. 1998. [3] Y.-W. Chang, K. Zhu, and D. F. Wong, “Timing-driven routing for sym- metrical-array-based FPGAs,” ACM Trans. Design Automation Elec- tron. Syst., vol. 5, no. 3, pp. 433–450, 2000. [4] T. Chan, J. Cong, T. Kong, and J. Shinnerl, “Multilevel optimization for large-scale circuit placement,” in Proc. IEEE/ACM Int. Conf. Computer- Aided Design, Nov. 2000, pp. 171–176. [5] J. Cong, J. Fang, andY. Zhang, “Multilevel approach to full-chip gridless routing,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2001, pp. 396–403. [6] J. Cong, J. Fang, and K. Khoo, “DUNE: A multi-layer gridless routing system with wire planning,” in Proc. ACM Int. Symp. Physical Design, 2000, pp. 12–18. [7] J. Cong, A. Kahng, and K. Leung, “Efficient algorithms for the min- imum shortest path steiner arborescence problem with applications to VLSI physical design,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 24–39, Jan. 1998. [8] J. Cong, S. Lim, and C. Wu, “Performance driven multilevel and mul- tiway partitioning with retiming,” in Proc. ACM/IEEE Design Automa- tion Conf., June 2000, pp. 274–279. [9] J. Cong and P. H. Madden, “Performance driven global routing for stan- dard cell design,” in Proc. ACM Int. Symp. Physical Design, Apr. 1997, pp. 73–80. [10] J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, “Provably good performance driven global routing,” IEEE Trans. Com- puter-Aided Design, vol. 11, pp. 739–752, June 1992. [11] T. Deguchi, T. Koide, and S. Wakabayashi, “Timing-driven hierarchical global routingwithwire-sizing and buffer-insertion for VLSIwithmulti- routing-layer,” in Proc. Asia South Pacific Design Automation Conf., June 2000, pp. 99–104. [12] M. Hayashi and S. Tsukiyama, “A hybrid hierarchical global router for multi-layer VLSI’s,” IEICE Trans. Fundamentals, vol. E78-A, no. 3, pp. 337–344, 1995. [13] J. Heisterman and T. Lengauer, “The efficient solutions of integer pro- grams for hierarchical global routing,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 748–753, June 1991. [14] D. Hightower, “A solution to line routing problems on the continuous plane,” in Proc. Design Automation Workshop, 1969, pp. 1–24. [15] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, “Multilevel hy- pergraph partitioning: application in VLSI domain,” IEEE Trans. VLSI Syst., vol. 7, pp. 69–79, Mar. 1999. [16] R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Predictable routing,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2000, pp. 110–114. [17] C.-Y. Lee, “An algorithm for path connection and its application,” IRE Trans. Comput., vol. EC-10, pp. 346–365, Sept. 1961. [18] Y.-L. Lin, Y.-C. Hsu, and F.-S. Tsai, “Hybrid routing,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 151–157, Feb. 1990. [19] J. Lillis, C.-K. Cheng, T.-T. Y. Lin, and C.-Y. Ho, “New performance driven routing techniques with explicit area/delay tradeoff and simulta- neous wiresizing,” in Proc. Design Automation Conf., June 1996, pp. 395–400. [20] H.-C. Lee, Y.-W. Chang, J.-M. Hsu, and H. Yang, “Multilevel floor- planning/placement for large-scale modules using B -trees,” in Proc. ACM/IEEE Design Automation Conf., Anaheim, CA, June 2003, pp. 812–817. [21] S.-P. Lin and Y.-W. Chang, “Novel framework for multilevel routing considering routability and performance,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 2002, pp. 44–50. [22] M. Marek-Sadowska, “Router planner for custom chip design,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1986, pp. 246–249. [23] G. Meixner and U. Lauther, “A new global router based on a flow model and linear assignment,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1990, pp. 44–47. [24] J. Soukup, “Fast maze router,” in Proc. ACM/IEEE Design Automation Conf., June 1978, pp. 100–102. [25] D. Wang and E. Kuh, “A new timing-driven multilayer MCM/IC routing algorithm,” in Proc. Multi-Chip Module Conf., Feb. 1997, pp. 89–94. Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture Mohammad H. Tehranipour, Nisar Ahmed, and Mehrdad Nourani Abstract—As technology shrinks and working frequency reaches the multigigahertz range, designing and testing interconnects are no longer trivial issues. In this paper, we propose an enhanced boundary-scan archi- tecture to test high-speed interconnects for signal integrity. This architec- ture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations. To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode. Index Terms—Boundary-scan test, integrity loss, interconnect testing, Joint Test ActionGroup (JTAG) Standard, signal integrity, system-on-chip. I. INTRODUCTION A. Motivation The number of cores in a system-on-chip (SoC) is rapidly growing, which leads to a significant increase in the number of interconnects. With fine miniaturization of the very large scale integrated (VLSI) cir- cuits, existence of long interconnects in SoCs and rapid increase in the working frequency (currently in the gigahertz range), signal integrity Manuscript received June 23, 2003. This work was supported in part by the National Science Foundation under CAREER Award #CCR-0130513. This paper was recommended by Associate Editor K. Chakrabarty. The authors are with the Center for Integrated Circuits and Systems, The University of Texas at Dallas, Richardson, TX 75083-0688 USA (e-mail: mht021000@utdallas.edu; nxa018600@utdallas.edu; nourani@utdallas.edu). Digital Object Identifier 10.1109/TCAD.2004.826540 0278-0070/04$20.00 © 2004 IEEE IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 801 has become a major concern for design and test engineers. Use of nanometer technology in SoCsmagnifies cross-coupling effects among the interconnects. The coupling capacitance and mutual inductance af- fect the integrity of a signal by adding noise and delay. The noise effect can appear as overshoot and ringing. The former is known to shorten transistor lifetime and the latter to cause intermittent functional errors. Slowdown and performance degradation are often the result of excessive delay. Various parasitic factors such as parasitic capaci- tances, inductances, and their cross-coupling effects on the intercon- nects, are difficult to control during fabrication. These parasitic factors play a significant role in the ultimate functionality and performance of high-speed SoCs. Signal integrity is the ability of a signal to generate correct responses in a circuit. It generally includes all effects that cause the design to mal- function due to distortion of the signal waveform. According to this in- formal definition, a signal with good integrity has: 1) voltage values at required levels and 2) level transitions at required times. If signal-in- tegrity losses (i.e., noise and delay) on an interconnect are within the defined safe margin, they are acceptable, since they do no harm. Oth- erwise, they may cause intermittent logic-error, performance degrada- tion, shorter life time, and reliability concern. For example, an input signal to a flip-flop with good signal integrity arrives early enough to guarantee the setup and hold time requirements and it does not have spikes causing undesired logic transition (ringing). The impact of process variation on circuit operation is an important issue in deep submicron (DSM). Process variation and manufacturing defects both may lead to unacceptable levels of noise and delay. The goal of design for DSM is to minimize noise and delay. However, it is impossible to check and fix all possible signal-integrity problems during DSM design by only design rule checking (DRC), validation, and analysis. Process variations and manufacturing defects may lead to unexpected changes in coupling capacitances and mutual inductances between interconnects.They in turn result in loss of signal integrity (e.g., glitches and excessive delay), which may eventually cause logic error and failure of the chip. The impact of spot defects and process variations on the magnitude of inductance induced noise are reported in [1]. The authors reported that the maximum crosstalk pulse considering process variation is almost twice the value for the nominal set of parameters. Since it is impossible to predict the occurrence of defects that cause noise and delay, signal-integrity testing is essential to ensure error-free operation of the chip and must be addressed in manufacturing testing. In recent years, various methodologies to test signal noise and skew on interconnects, due to different sources, are reported in literature. Regardless of the method used to detect integrity loss, we also need a mechanism to coordinate activities in an integrity test session. We believe that one of the best choices is the boundary scan test method- ology that includes the capability of accessing interconnects. Boundary scan test methodologywas initially introduced to facilitate testing com- plex printed circuit boards (PCBs). The IEEE 1149.1 Boundary Scan Test [5], also known as the Joint Test Action Group (JTAG) Standard, has been widely accepted and practiced in the testing community. The standard provides excellent testing features with low complexity, but it was not intended to address high-speed testing and signal-integrity loss. The standard, nevertheless, provides a mechanism to test core logic and the interconnects among them. Interconnects can be tested for stuck-at, open, and short faults [6]. In this paper, the standard boundary-scan ar- chitecture is extended to test interconnects for noise and skew violation. While we focus on interconnects, any nonmodeled fault (inside or out- side cores) that manifests itself as integrity loss on interconnects will also be detected by our method. B. Prior Work 1) Signal Integrity Modeling and Analysis: Maximum aggressor (MA) fault model [7] is one of the fault models proposed for crosstalk. Various approaches to analyze the crosstalk are described in [8]–[10]. Interconnect design for multigigahertz integrated circuits is discussed in [11]. The author observed that chips failed, when a specific test pat- tern (not included in theMAmodel) is applied to the interconnects, due to the overall effect of coupling capacitances and mutual inductances. Similarly, according to [12], the worst case switching pattern to handle inductive effects for multiple signal lines may not be included in the MA fault model. Several researchers have worked on test pattern gen- eration for crosstalk noise/delay and signal integrity [13]–[15]. 2) Test Methodologies: There is a long list of possible design and fabrication solutions to reduce signal-integrity problems on the inter- connect. None guarantees to resolve the issue perfectly. A double sam- pling data checking (DSDC) technique is used to capture noise-induced logic failures in on-chip buses [16]. At-speed testing of crosstalk in chip interconnects and testing interconnect-crosstalk defects using an on-chip processor are reported in [3], respectively. A built-in self-test (BIST)-based architecture to test long interconnects for signal integrity [4], and the use of boundary scan and I DDT for testing buses [17] are other proposed methods. Even short interconnects, especially those lo- cated near long interconnects, are also susceptible to integrity prob- lems. Therefore, in the near future, methodologies are required for testing both short and long high-speed interconnects [18]. 3) Integrity Loss Sensor Cell: Due to increasing concerns about signal-integrity loss in gigahertz chips and the fact that their occurrence must be captured on the chip, researchers presented various on-chip in- tegrity loss sensors (ILS). A BIST structure using D flip-flops has been proposed to detect deviation of propagation delay in operational ampli- fiers [19]. In [17], a built-in sensor is integrated within the system. This sensor is an on-chip current mirror converting dissipated charges into associated test time. Reference [20] presented a more expensive but more accurate circuit to measure jitter and skew in the range of a few picoseconds. The authors in [21] presented a sample-and-hold circuit that probes the voltage directly within the interconnects. The work pre- sented in [4] proposed two cells called noise detector (ND) and skew detector (SD) cells based on a modified cross-coupled PMOS differen- tial sense amplifier. To detect delay violation, an integrity-loss sensor (ILS) has been designed in [22], which is flexible and tunable for var- ious delay thresholds and technologies. A double sampling technique is applied by online-error detector circuit to test multiple-source noise-in- duced errors on the interconnects and buses [16]. 4) Modified Boundary Scan and IEEE Standards: BIST-based test pattern generators for board-level interconnect and delay testing are proposed in [23] and [24], respectively. A test methodology targeting defects on bus structures using I DDT and boundary scan has been pre- sented in [17]. P1500 proposes standardization of a core test wrapper and core test language (CTL) [25]. This method is similar to boundary scan in terms of serial data transfer and therefore, the extended serial interface layer (SIL) architecture can be used for various test applica- tions at the system level in general, and in integrity test in particular. IEEE 1149.4 mixed-signal test bus standard [26] was proposed to allow access to the analog pins of a mixed-signal device. In addition to the ability to test interconnects using digital patterns, IEEE 1149.4 in- cludes the ability to measure actual passive components, such as resis- tors and capacitors. This standard cannot support high-frequency phe- nomena such as crosstalk on the interconnects. Reference [27] proposes a method to simplify the development of a mixed-signal test standard by adding the analog interconnect test to IEEE 1149.1. IEEE 1149.6 provides a solution for testing ac-coupled interconnects between inte- grated circuits on printed circuit boards and systems [28]. Our approach is similar to this standard draft in strategy of enhancing the JTAG stan- dard and its instructions for testing high-frequency behaviors. How- ever, there are fundamental differences. Contrary to our approach, the standard is not intended to consider coupling effects among the inter- 802 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 Fig. 1. Signal integrity fault model. connect lines. Also, 1149.6 adds a dc-blocking capacitor to each in- terconnect under test to disallow the dc signals. Thus, IEEE 1149.6 cannot test integrity loss due to low-speed, but very sharp-edge signals that are known to cause overshoots and noise. The sensors in our ar- chitecture, sitting in the observation boundary-scan cells (BSCs), can detect such scenarios. Finally, using differential drivers in the modified cells in IEEE 1149.6 makes the cells more expensive and less flexible in adopting other types of noise detectors/sensors. Various issues on the extended JTAG architecture to test SoC interconnects for signal in- tegrity are reported in [22], [29], and [30], using the MA and multiple transition (MT) fault models, respectively. C. Contribution and Paper Organization Our main contribution is an on-chip mechanism to extend the JTAG standard to include testing interconnects for signal integrity. The mod- ified driving-end pattern generation BSCs (called PGBSCs) receive a few seeds and generate MT patterns at-speed to stimulate integrity vi- olations. The MT pattern set is a superset of the MA set and is much more capable of testing the capacitive and inductive coupling among interconnects. Themodified receiving-end BSCs (called OBSC) record the occurrence of signals entering the vulnerable region over a period of operation. Using two new instructions in JTAG architecture, the in- tegrity test information is sent out for a final test analysis, reliability judgment, and diagnosis. The rest of this paper is organized as follows. Section II describes the MT fault model and its corresponding test patterns. The enhanced BSCs are detailed in Section III. Section IV explains the test architec- ture to send test patterns and capture and read out the signal integrity information. The experimental results including implementation and simulation of our own ILS are discussed in Section V. Finally, con- cluding remarks are in Section VI. II. MT-FAULT MODEL The MA fault model [7] is a simplified model used by many re- searchers mainly for crosstalk analysis and testing. This model, shown in Fig. 1, assumes the signal traveling on a victim line V may be af- fected by signals/transitions on other aggressor line(s) A in its neigh- borhood. The coupling can be represented by a generic coupling com- ponent Z . In general, the result could be noise (causing ringing and functional error) and delay (causing performance degradation). How- ever, there is controversy as to what patterns trigger maximal integrity loss. Specifically, in the traditional MA model that takes only cou- pling C into account, all aggressors make the same simultaneous tran- sition in the same direction, while the victim line is kept quiescent (for maximal ringing) or makes an opposite transition (for maximal delay). Fig. 2 shows the test patterns for detecting faults according to MA model. When mutual inductance comes into play, some researchers have shown that the MA model may not reflect the worst case, and presented other ways (pseudorandom, weighted pseudorandom, or de- terministic) to generate test patterns to create maximal integrity loss [13]–[15]. Fig. 2. MA fault model and test patterns. Fig. 3. Comparison between the MT and MA models. As reported in [11], a chip fails when the nearest aggressor lines change in one direction and the other aggressors in the opposite direc- tion. This and many similar carefully chosen scenarios are not covered by the MA fault model. Exhaustive testing covers all situations, but it is very time consuming because of the huge number of test p