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tps28225同步整流.pdf

tps28225同步整流.pdf

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简介:本文档为《tps28225同步整流pdf》,可适用于硬件技术领域,主题内容包含TPSTPSwwwticomSLUSC–MAY–REVISEDAPRILHighFrequencyASinkSynchronousMOSFETDri符等。

TPS28225 TPS28226 www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010 High-Frequency 4-A Sink Synchronous MOSFET Drivers Check for Samples: TPS28225, TPS28226 1FEATURES DESCRIPTION• Drives Two N-Channel MOSFETs with 14-ns Adaptive Dead Time The TPS28225 and TPS28226 are high-speed drivers for N-channel complimentary driven power• Wide Gate Drive Voltage: 4.5 V Up to 8.8 V MOSFETs with adaptive dead-time control. TheseWith Best Efficiency at 7 V to 8 V drivers are optimized for use in variety of high-current • Wide Power System Train Input Voltage: 3 V one and multi-phase dc-to-dc converters. TheUp to 27 V TPS28225/6 is a solution that provides highly • Wide Input PWM Signals: 2.0 V up to 13.2-V efficient, small size low EMI emmissions. Amplitude The performance is achieved by up to 8.8-V gate • Capable Drive MOSFETs with 40-A Current drive voltage, 14-ns adaptive dead-time control, 14-ns per Phase propagation delays and high-current 2-A source and 4-A sink drive capability. The 0.4-Ω impedance for• High Frequency Operation: 14-ns Propagation the lower gate driver holds the gate of powerDelay and 10-ns Rise/Fall Time Allow FSW - 2 MOSFET below its threshold and ensures noMHz shoot-through current at high dV/dt phase node • Capable Propagate <30-ns Input PWM Pulses transitions. The bootstrap capacitor charged by an • Low-Side Driver Sink On-Resistance (0.4 Ω) internal diode allows use of N-channel MOSFETs in half-bridge configuration.Prevents dV/dT Related Shoot-Through Current The TPS28225/6 features a 3-state PWM input • 3-State PWM Input for Power Stage Shutdown compatible with all multi-phase controllers employing 3-state output feature. As long as the input stays• Space Saving Enable (input) and Power Good within 3-state window for the 250-ns hold-off time, the(output) Signals on Same Pin driver switches both outputs low. This shutdown • Thermal Shutdown mode prevents a load from the reversed- • UVLO Protection output-voltage. • Internal Bootstrap Diode The other features include under voltage lockout, • Economical SOIC-8 and Thermally Enhanced thermal shutdown and two-way enable/power good signal. Systems without 3-state featured controllers3-mm x 3-mm DFN-8 Packages can use enable/power good input/output to hold both • High Performance Replacement for Popular outputs low during shutting down.3-State Input Drivers The TPS28225/6 is offered in an economical SOIC-8 and thermally enhanced low-size Dual Flat No-LeadAPPLICATIONS (DFN-8) packages. The driver is specified in the • Multi-Phase DC-to-DC Converters with Analog extended temperature range of –40C to 125C withor Digital Control the absolute maximum junction temperature 150C. • Desktop and Server VRMs and EVRDs The TPS28226 operates in the same manner as the • Portable/Notebook Regulators TPS28225/6 other than the input under voltage lock • Synchronous Rectification for Isolated Power out. Unless otherwise stated all references to the Supplies TPS28225 apply to the TPS28226 also. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains Copyright 2006–2010, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 6 13K 2VDD EN/PG BOOT UGATE PHASE LGATE GND 7 1 8 5 4 VDD 27K 3-STATE INPUT CIRCUITPWM 3 SHOOT- THROUGH PROTECTION THERMAL SD HLD-OFF TIME UVLO 3 3 2BOOT UGATE PHASE LGATE GND 1 8 5 4 6 VDD ENBL7 PWM3 OUT FB 3 GND 3 TPS28225 VDD (4.5Vto8V) VIN (3Vto32V VDD) VOUTVCC TPS40200 TPS28225 TPS28226 SLUS710C –MAY 2006–REVISED APRIL 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM TYPICAL APPLICATIONS One-Phase POL Regulator 2 Submit Documentation Feedback Copyright 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS28225 TPS28226 PWM CONTROLLER ISOLATION AND FEEDBACK C O N T R O L DRIVE LO DRIVE HI HI LI HB HO HS LO 2BOOT UGATE PHASE LGATE GND 1 8 5 4 3 VDD EN/PG7 PWM 6 LINEAR REG. VDD (4.5Vto8V) VOUT =3.3V 35Vto75V 12V PrimaryHighSide VDD HighVoltageDriver VSS TPS28255 TPS28225 TPS28226 www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010 TYPICAL APPLICATIONS (continued) Driver for Synchronous Rectification with Complementary Driven MOSFETs Copyright 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TPS28225 TPS28226 5 4 7 3 8 1 2 2BOOT UGATE PHASE LGATE GND 1 8 5 4 6 VDD EN/PG7 PWM3 2BOOT UGATE PHASE LGATE GND 1 8 5 4 6 VDD EN/PG7 PWM3 VIN PWM 4 GND VOUT PWM1 8PWM3 Enable PWM2 ToDriver ToDriver GNDS ToController CSCNCS 4 ToController CS 1 VDD (4.5Vto8V) VIN (3Vto32V VDD) TPS28225 TPS28225 TP S4 00 9x o r an y ot he ra na lo g o r di gi ta lc on tro lle r VOUT TPS28225 TPS28226 SLUS710C –MAY 2006–REVISED APRIL 2010 www.ti.com TYPICAL APPLICATIONS (continued) Multi-Phase Synchronous Buck Converter ORDERING INFORMATION (1) (2) (3) PART NUMBERTAPE AND REELTEMPERATURE RANGE, TA = TJ PACKAGE QTY. TPS28225 TPS28226 Plastic 8-pin SOIC (D) 250 TPS28225DT TPS28226DT Plastic 8-pin SOIC (D) 2500 TPS28225DR TPS28226DR Plastic 8-pin DFN -40C to 125C 250 TPS28225DRBT TPS28226DRBT(DRB) Plastic 8-pin DFN 3000 TPS28225DRBR TPS28226DRBR(DRB) (1) SOIC-8 (D) and DFN-8 (DRB) packages are available taped and reeled. Add T suffix to device type (e.g. TPS28225DT) to order taped devices and suffix R to device type to order reeled devices. (2) The SOIC-8 (D) and DFN-8 (DRB) package uses in Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255C to 260C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. (3) In the DFN package, the pad underneath the center of the device is a thermal substrate. The PCB “thermal land” design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential. This pad should be either grounded for best noise immunity, and it should not be connected to other nodes. 4 Submit Documentation Feedback Copyright 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS28225 TPS28226 TPS28225 TPS28226 www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) TPS28225/6 VALUE UNIT Input supply voltage range, VDD (3) –0.3 to 8.8 Boot voltage, VBOOT –0.3 to 33 DC –2 to 32 or VBOOT + 0.3 – VDD whichever is lessPhase voltage, VPHASE Pulse < 400 ns, E = 20 mJ –7 to 33.1 or VBOOT + 0.3 – VDD whichever is less Input voltage range, VPWM, VEN/PG –0.3 to 13.2 VPHASE – 0.3 to VBOOT + 0.3, (VBOOT – VPHASE < 8.8) VOutput voltage range, VUGATE Pulse < 100 ns, E = 2 mJ VPHASE – 2 to VBOOT + 0.3, (VBOOT – VPHASE < 8.8) –0.3 to VDD + 0.3Output voltage range, VLGATE Pulse < 100 ns, E = 2 mJ –2 to VDD + 0.3 ESD rating, HBM 2 k ESD rating, HBM ESD rating, CDM 500 Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, TJ –40 to 150 Operating ambient temperature range, TA –40 to 125 C Storage temperature, Tstg –65 to 150 Lead temperature (soldering, 10 sec.) 300 (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures. (3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Data book for thermal limitations and considerations of packages. DISSIPATION RATINGS (1) DERATING FACTOR TA < 25C TA =70C TA = 85CBOARD PACKAGE RqJC RqJA ABOVE TA = 25C POWER RATING POWER RATING POWER RATING High-K (2) D 39.4C/W 100C/W 10 mW/C 1.25 W 0.8 W 0.65 W High-K (3) DRB 1.4C/W 48.5C/W 20.6 mW/C 2.58 W 1.65 W 1.34 W (1) These thermal data are taken at standard JEDEC test conditions and are useful for the thermal performance comparison of different packages. The cooling condition and thermal impedance RqJA of practical design is specific.(2) The JEDEC test board JESD51-7, 3-inch x 3-inch, 4-layer with 1-oz internal power and ground planes and 2-oz top and bottom trace layers. (3) The JEDEC test board JESD51-5 with direct thermal pad attach, 3-inch x 3-inch, 4-layer with 1-oz internal power and ground planes and 2-oz top and bottom trace layers. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT Input supply voltage (TPS28225) 4.5 7.2 8 VDD Input supply voltage (TPS28226) 6.8 7.2 8 V VIN Power input voltage for the TPS28225 3 32 V–VDD TJ Operating junction temperature range –40 125 C Copyright 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS28225 TPS28226 TPS28225 TPS28226 SLUS710C –MAY 2006–REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (1) VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UNDER VOLTAGE LOCKOUT Rising threshold (TPS28225) 3.2 3.5 3.8 Rising threshold (TPS28226) 6.35 6.70 VPWM = 0 VFalling threshold (TPS28225) 2.7 3.0 V Falling threshold (TPS28226) 4.7 5.0 Hysteresis (TPS28225) 0.5 Hysteresis (TPS28226) 1.00 1.35 BIAS CURRENTS IDD(off) Bias supply current VEN/PG = low, PWM pin floating 350 mA IDD Bias supply current VEN/PG = high, PWM pin floating 500 INPUT (PWM) VPWM = 5 V 185IPWM Input current mAVPWM = 0 V –200 PWM 3-state rising threshold (2) 1.0 V PWM 3-state falling threshold VPWM PEAK = 5 V 3.4 3.8 4.0 tHLD_R 3-state shutdown Hold-off time 250 ns TMIN PWM minimum pulse to force UGATE pulse CL = 3 nF at UGATE , VPWM = 5 V 30 ENABLE/POWER GOOD (EN/PG) Enable high rising threshold PG FET OFF 1.7 2.1 Enable low falling threshold PG FET OFF 0.8 1.0 V Hysteresis 0.35 0.70 Power good output VDD = 2.5 V 0.2 UPPER GATE DRIVER OUTPUT (UGATE) Source resistance 500 mA source current 1.0 2.0 Ω Source current (2) VUGATE-PHASE = 2.5 V 2.0 A tRU Rise time CL = 3 nF 10 ns Sink resistance 500 mA sink current 1.0 2.0 Ω Sink current (2) VUGATE-PHASE = 2.5 V 2.0 A tFU Fall time CL = 3 nF 10 ns (1) Typical values for TA = 25C(2) Not tested in production 6 Submit Documentation Feedback Copyright 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS28225 TPS28226 TPS28225 TPS28226 www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS (1) (continued) VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOWER GATE DRIVER OUTPUT (LGATE) Source resistance 500 mA source current 1.0 2.0 Ω Source current (3) VLGATE = 2.5 V 2.0 A tRL Rise time (3) CL = 3 nF 10 ns Sink resistance 500 mA sink current 0.4 1.0 Ω Sink current (3) VLGATE = 2.5 V 4.0 A Fall time (3) CL = 3 nF 5 ns SWITCHING TIME tDLU UGATE turn-off propagation Delay CL = 3 nF 14 tDLL LGATE turn-off propagation Delay CL = 3 nF 14 ns tDTU Dead time LGATE turn-off to UGATE turn-on CL = 3 nF 14 tDTL Dead time UGATE turn-off to LGATE turn-on CL = 3 nF 14 BOOTSTRAP DIODE VF Forward voltage Forward bias current 100 mA 1.0 V THERMAL SHUTDOWN Rising threshold (3) 150 160 170 Falling threshold (3) 130 140 150 C Hysteresis 20 (3) Not tested in production Copyright 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TPS28225 TPS28226 1 2 3 4 8 7 6 5 UGATE BOOT PWM GND PHASE EN/PG VDD LGATE 5 3 7 6 81 2BOOT PWM VDD EN/PG LG AT EGND U G ATE PHASE 4 Exposed Thermal Die Pad 6 13K 2VDD EN/PG BOOT UGATE PHASE LGATE GND 7 1 8 5 4 VDD 27K 3-STATE INPUT CIRCUITPWM 3 SHOOT- THROUGH PROTECTION THERMAL SD HLD-OFF TIME UVLO TPS28225 TPS28226 SLUS710C –MAY 2006–REVISED APRIL 2010 www.ti.com DEVICE INFORMATION SOIC-8 Package (top view) DRB-8 Package (top view) BLOCK DIAGRAM A. For the TPS28225DRB device the thermal PAD on the bottom side of package must be soldered and connected to the GND pin and to the GND plane of the PCB in the shortest possible way. See Recommended Land Pattern in the Application section. 8 Submit Documentation Feedback Copyright 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS28225 TPS28226 TPS28225 TPS28226 www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION SOIC-8 DRB-8 NAME 1 1 UGATE O Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET. Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between 2 2 BOOT I/O this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. The PWM signal is the control input for the driver. The PWM signal can enter three distinct states 3 3 PWM I during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further details. Connect this pin to the PWM output of the controller. 4 4 GND — Ground pin. All signals are referenced to this node. Exposed Thermal — Connect directly to the GND for better thermal performance and EMIdie pad pad Lower gate drive sink/source output. Connect to the gate of the low-side power N-Channel5 5 LGATE O MOSFET. 6 6 VDD I Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND. Enable/Power Good input/output pin with 1MΩ impedance. Connect this pin to HIGH to enable and LOW to disable the device. When disabled, the device draws less than 350mA bias current. If the7 7 EN/PG I/O VDD is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled low. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin8 8 PHASE I provides a return path for the upper gate driver. TRUTH TABLE VDD FALLING > 3 V AND TJ < 150C VDD RISING < 3.5 V EN/PG FALLING > 1.0 VPIN EN/PG RISINGOR TJ > 160C PWM > 1.5 V AND PWM SIGNAL SOURCE IMPEDANCE< 1.7 V PWM < 1 V TRISE/TFALL < 200 ns >40 kΩ FOR > 250ns (3-State) (1) LGATE Low Low High Low Low UGATE Low Low Low High Low EN/PG Low (1) To exit the 3-state condition, the PWM signal should go low. One Low PWM input signal followed by one High PWM input signal is required before re-entering the 3-state condition. Copyright 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS28225 TPS28226 Normal switching PWM LGATE UGATE 3-State window 90% 10% tDLL 50% t FL 50% t PWM_MIN t DTU 90% 10% t RU 90% 10% t DLU t FU t DTL 90% 10% tRL tHLD_R 90% 10% 90% 90% t HLD_F Enter into 3-State at PWM rise Exit 3-State Enter into 3-State at PWM fall UGATE exits 3-State after PWM goes Low and then High Normal switching PWM LGATE UGATE 3-State window 90% 10% tDLL 50% tFL 50% t PWM_MIN t DTU 90% 10% t RU 90% 10% t DLU t FU t DTL 90% 10% tRL tHLD_R 90% 10% 90% 90% t HLD_F Enter into 3-State at PWM rise Exit 3-State Enter into 3-State at PWM fall LGATE exits 3-State after PWM goes High and then Low TPS28225 TPS28226 SLUS710C –MAY 2006–REVISED APRIL 2010 www.ti.com TPS28225 TIMING DIAGRAM TPS28226 TIMING DIAGRAM 10 Submit Documentation Feedback Copyright 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS28225 TPS28226 40 125 300 340 380 420 460 500 25 320 360 400 440 480 TJ Temperature C I D D( o ff) Bi as S up pl y m A 2.00 3.50 4.50 6.00 2.50 3.00 4.00 5.00 5.50 UV LO U nd er V o lta ge L oc ko ut V 40 125 TJ Temperature C 25 6.50 8.00 7.00 7.50 TPS28226 Falling TPS28226 Rising TPS28225 Falling TPS28225 Rising 0.0 PW M P W M 3 S ta te T hr es ho ld V 40 12525 2.0 3.0 5.0 0.5 1.0 2.5 2.5 4.5 1.5 4.0 Falling Rising TJ Temperature C 40 12525 0.00 0.75 1.25 2.00 0.25 0.50 1.00 1.50 1.75 Falling Rising TJ Temperature C EN /P G E na bl e/ Po w er G oo d V TPS28225 TPS28226 www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010 TYPICAL CHARACTERISTICS BIAS SUPPLY CURRENT vs UNDER VOLTAGE LOCKOUT THRESHOLD TEMPERATURE vs (VEN/PG = Low, PWM Input Floating, VDD = 7.2V) TEMPERATURE Figure 1. Figure 2. ENABLE/POWER GOOD THRESHOLD PWM 3-STATE THRESHOLDS, (5-V Input Pulses) vs vs TEMPERATURE (VDD = 7.2 V) TEMPERATURE, (VDD = 7.2 V) Figure 3. Figure 4. Copyright 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TPS28225 TPS28226 0 40 12525 0.75 1.25 2.00 0.25 0.50 1.00 1.50 1.75 RSINK RSOURCE TJ Temperature C R O UT O ut pu t I m pe da nc e W 0 40 12525 0.75 1.25 2.00 0.25 0.50 1.00 1.50 1.75 RSINK RSOURCE TJ Temperature C R O UT O ut pu t I m pe da nc e W 40 12525 4 6 10 12 14 5 7 9 11 13 8 Falling Rising TJ Temperature C t R L/ t F L Ri se a nd F al l T im e ns 6 8 11 13 15 7 9 10 12 14 40 12525 Falling Rising TJ Temperature C t R U/ t F U Ri se a nd F al l T im e ns TPS28225 TPS28226 SLUS710C –MAY 2006–REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) UGATE DC OUTPUT IMPEDANCE LGATE DC OUTPUT IMPEDANCE vs vs TEMPERATURE, (VDD = 7.2 V) TEMPERATURE (VDD = 7.2 V) Figure 5. Figure 6. UGATE RISE AND FALL TIME LGATE RISE AND FALL TIME vs vs TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF) TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF) Figure 7. Figure 8. 12 Submit Documentation Feedback Copyright 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS28225 TPS28226 40 12525 0.0 12.5 17.5 20.0 2.5 7.5 10.0 5.0 15.0 LGATE UGATE TJ Temperature C t D TU /t D TL U G AT E an d L G AT E n s 0 20 25 30 5 10 15 40 12525 LGATE UGATE TJ Temperature C t D LU /t D LL U G AT E an d L G AT E n s 0.5 0.8 1.0 1.3 0.6 0.7 0.9 1.1 1.2 40 12525 TJ Temperature C V F Fo rw ar d Vo lta ge V 0 5 25 30 10 15 20 40 12525 TJ Temperature C T M IN M in im um S ho rt Pu ls e ns TPS28225 TPS28226 www.ti.com SLUS710C –MAY 2006–REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) UGATE AND LGATE (Turning OFF Propagation Delays) UGATE AND LGATE (Dead Time) vs vs TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF) TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF) Figure 9. Figure 10. UGATE MINIMUM SHORT PULSE BOOTSTRAP DIODE FORWARD VOLTAGE vs vs TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF) TEMPERATURE (VDD = 7.2 V, IF = 100 mA) Figure 11. Figure 12. Copyright 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): TPS28225 TPS28226 0 200 1000 1200 400 600 800 100 300 500 700 1500 1700900 1100 19001300 UG = 50 nC L

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