TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
� 12-Bit Voltage Output DAC
� Programmable Settling Time vs Power
Consumption
3 µs in Fast Mode
9 µs in Slow Mode
� Ultra Low Power Consumption:
900 µW Typ in Slow Mode at 3 V
2.1 mW Typ in Fast Mode at 3 V
� Differential Nonlinearity . . . <0.5 LSB Typ
� Compatible With TMS320 and SPI Serial
Ports
� Power-Down Mode (10 nA)
� Buffered High-Impedance Reference Input
� Voltage Output Range . . . 2 Times the
Reference Input Voltage
� Monotonic Over Temperature
� Available in MSOP Package
applications
� Digital Servo Control Loops
� Digital Offset and Gain Adjustment
� Industrial Process Control
� Machine and Motion Control Devices
� Mass Storage Devices
description
The TLV5616 is a 12-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows glueless interface to TMS320, SPI, QSPI,
and Microwire serial ports. The TLV5616 is
programmed with a 16-bit serial string containing
4 control and 12 data bits. Developed for a wide
range of supply voltages, the TLV5616 can
operate from 2.7 V to 5.5 V.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.
Implemented with a CMOS process, the TLV5616 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TLV5616C is characterized for operation from 0°C
to 70°C. The TLV5616I is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA SMALL OUTLINE†
(D)
MSOP
(DGK)
PLASTIC DIP
(P)
0°C to 70°C TLV5616CD TLV5616CDGK TLV5616CP
–40°C to 85°C TLV5616ID TLV5616IDGK TLV5616IP
† Available in tape and reel as the TLV5616CDR and the TLV5616IDR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
8
7
6
5
DIN
SCLK
CS
FS
VDD
OUT
REFIN
AGND
D, DGK, OR P PACKAGE
(TOP VIEW)
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Serial Input
Register
16 Cycle
Timer
REFIN
CS
SCLK
FS
OUT
_
+
Power-On
Reset
DIN 12-Bit
Data
Latch
Speed/Power-Down
Logic
2
12
Update
6
1
2
3
4
7
x2
14
12
Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
I/O DESCRIPTION
AGND 5 Analog ground
CS 3 I Chip select. Digital input used to enable and disable inputs, active low.
DIN 1 I Serial digital data input
FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
OUT 7 O DAC analog output
REFIN 6 I Reference analog input voltage
SCLK 2 I Serial digital clock input
VDD 8 Positive power supply
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5616C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5616I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage VDD
VDD = 5 V 4.5 5 5.5 VSupply voltage, VDD VDD = 3 V 2.7 3 3.3 V
High level digital input voltage VIH
DVDD = 2.7 V 2 VHigh-level digital input voltage, VIH DVDD = 5.5 V 2.4 V
Low level digital input voltage VIL
DVDD = 2.7 V 0.6 VLow-level digital input voltage, VIL DVDD = 5.5 V 1 V
Reference voltage, Vref to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V
Reference voltage, Vref to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V
Load resistance, RL 2 10 kΩ
Load capacitance, CL 100 pF
Clock frequency, fCLK 20 MHz
Operating free air temperature TA
TLV5616C 0 70 °C
Operating free-air temperature, TA TLV5616I –40 85 °C
NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 5 V, VREF = 2.048 V,
No load,
Fast 0.9 1.35 mA
IDD Power supply current
All inputs = AGND or VDD,
DAC latch = 0x800 Slow 0.4 0.6 mA
IDD Power supply current VDD = 3 V, VREF = 1.024 V
No load,
Fast 0.7 1.1 mA
All inputs = AGND or VDD,
DAC latch = 0x800 Slow 0.3 0.45 mA
Power down supply current (see Figure 12) 10 nA
PSRR Power supply rejection ratio Zero scale See Note 2 –80 dBPSRR Power supply rejection ratio
Full scale See Note 3 –80
dB
Power on threshold voltage, POR 2 V
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
static DAC specifications RL = 10 kΩ, CL = 100 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 12 bits
INL Integral nonlinearity See Note 4 ± 1.9 ±4 LSB
DNL Differential nonlinearity See Note 5 ± 0.5 ± 1 LSB
EZS Zero-scale error (offset error at zero scale) See Note 6 ±10 mV
Zero-scale-error temperature coefficient See Note 7 10 ppm/°C
EG Gain error See Note 8 ±0.6
% of
FS
voltage
Gain-error temperature coefficient See Note 9 10 ppm/°C
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Voltage output range RL = 10 kΩ 0 AVDD–0.1 V
Output load regulation accuracy RL = 2 kΩ, vs 10 kΩ 0.1 ±0.25
% of FS
voltage
reference input (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI Input voltage range 0 VDD–1.5 V
RI Input resistance 10 MΩ
CI Input capacitance 5 pF
Reference input bandwidth REFIN = 0 2 V + 1 024 V dc
Slow 525 kHz
Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc Fast 1.3 MHz
Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc(see Note 10) –75 dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High-level digital input current VI = VDD ±1 µA
IIL Low-level digital input current VI = 0 V ±1 µA
CI Input capacitance 3 pF
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t (FS) Output settling time full scale RL = 10 kΩ,
CL = 100 pF, Fast 3 5.5 µsts(FS) Output settling time, full scale L ,See Note 11 Slow 9 20 µs
t (CC) Output settling time code to code RL = 10 kΩ,
CL = 100 pF, Fast 1 µsts(CC) Output settling time, code to code L ,See Note 12 Slow 2 µs
SR Slew rate RL = 10 kΩ, CL = 100 pF,
Fast 3.6
V/µsSR Slew rate L ,See Note 13
L ,
Slow 0.9
V/µs
Glitch energy Code transition from 0x7FF to 0x800 10 nV–s
S/N Signal to noise 74 dB
S/(N+D) Signal to noise + distortion fs = 400 KSPS fout = 1.1 kHz,
RL 10 kΩ CL 100 pF
66 dB
THD Total harmonic distortion
RL = 10 kΩ, CL = 100 pF,
BW = 20 kHz –68 dB
Spurious free dynamic range
BW = 20 kHz
70 dB
NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN NOM MAX UNIT
tsu(CS–FS) Setup time, CS low before FS↓ 10 ns
tsu(FS–CK) Setup time, FS low before first negative SCLK edge 8 ns
tsu(C16–FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before risingedge of FS 10 ns
tsu(C16–CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10 ns
twH Pulse duration, SCLK high 25 ns
twL Pulse duration, SCLK low 25 ns
tsu(D) Setup time, data ready before SCLK falling edge 8 ns
th(D) Hold time, data held valid after SCLK falling edge 5 ns
twH(FS) Pulse duration, FS high 20 ns
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
1 2 3 4 5 15 16
D15 D14 D13 D12 D1 D0
tsu(FS-CK)
tsu(CS-FS)
twH(FS)
th(D)tsu(D)
twHtwL
tsu(C16-CS)
tsu(C16-FS)
SCLK
DIN
CS
FS
Figure 1. Timing Diagram
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
1.998
1.996
1.994
1.990
0 0.01 0.02 0.05 0.1 0.2 0.5
–
O
ut
pu
t V
o
lta
ge
–
V 2
2.002
Load Current – mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.004
1 4
3 V Slow Mode, SOURCE
3 V Fast Mode, SOURCE
1.992
V O
VDD = 3 V,
Vref = 1 V,
Full Scale
2
Figure 3
3.995
3.99
3.985
3.975
0 0.02 0.04 0.1 0.2 0.4 1
4
4.005
OUTPUT VOLTAGE
vs
LOAD CURRENT
4.01
2 4
3.98
–
O
ut
pu
t V
o
lta
ge
–
V
Load Current – mA
5 V Slow Mode, SOURCE
5 V Fast Mode, SOURCE
V O
VDD = 5 V,
Vref = 2 V,
Full Scale
Figure 4
0.1
0.08
0.04
0
0 0.01 0.02 0.05 0.1 0.2 0.5
0.16
0.18
OUTPUT VOLTAGE
vs
LOAD CURRENT
0.2
1 2
0.14
0.12
0.06
0.02
–
O
ut
pu
t V
o
lta
ge
–
V
Load Current – mA
3 V Slow Mode, SINK
3 V Fast Mode, SINK
V O
VDD = 3 V,
Vref = 1 V,
Zero Code
Figure 5
0.2
0.15
0.1
0
0 0.02 0.04 0.1 0.2 0.4 1
0.25
0.3
OUTPUT VOLTAGE
vs
LOAD CURRENT
0.35
2 4
0.05
–
O
ut
pu
t V
o
lta
ge
–
V
Load Current – mA
5 V Slow Mode, SINK
5 V Fast Mode, SINK
V O
VDD = 5 V,
Vref = 2 V,
Zero Code
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
0.6
0.4
0.2
–55 –40 –25 0 25 40 70
–
Su
pp
ly
C
ur
re
nt
–
m
A 0.8
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1
85 125
I D
D
VDD = 3 V,
Vref = 1 V,
Full Scale
TA – Free-Air Temperature – C°
Fast Mode
Slow Mode
Figure 7
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.6
0.4
0.2
–55 –40 –25 0 25 40 70
–
Su
pp
ly
C
ur
re
nt
–
m
A 0.8
1
85 125
I D
D
VDD = 5 V,
Vref = 2 V,
Full Scale
TA – Free-Air Temperature – C°
Fast Mode
Slow Mode
Figure 8
––40
–50
–70
–80
0 5 10 20
TH
D
–
To
ta
l H
ar
m
on
ic
D
is
to
rti
on
–
dB
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 9
––40
–50
–70
–80
0 5 10 20
TH
D
–
To
ta
l H
ar
m
on
ic
D
is
to
rti
on
–
dB
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Slow Mode
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
––40
–50
–70
–80
0 5 10 20
TH
D
–
To
ta
l H
ar
m
on
ic
D
is
to
rti
on
A
nd
N
oi
se
–
dB
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 11
––40
–50
–70
–80
0 5 10 20
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
TH
D
–
To
ta
l H
ar
m
on
ic
D
is
to
rti
on
A
nd
N
oi
se
–
dB
Slow Mode
Figure 12
400
300
100
0
0 100 200 300 400 500 600
–
Su
pp
ly
C
ur
re
nt
– 600
800
T – Time – ns
SUPPLY CURRENT
vs
TIME (WHEN ENTERING POWER-DOWN MODE)
900
700 800 900 1000
700
500
200I
D
D
µ
A
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–2
–3.5
0 256 768 1280 1536 1792 2304
–1
0.5
INTEGRAL NONLINEARITY ERROR
2
2816 3328 3584
1.5
1
0
–0.5
–1.5
–2.5
–3
Digital CodeI
N
L
–
In
te
gr
al
N
on
lin
ea
rit
y
Er
ro
r –
LS
B
515 1024 2048 2560 3072 3840
Figure 13
0 256 512 768 1536 2048 2304
D
N
L
–
D
iff
er
en
tia
l N
on
lin
ea
rit
y
Er
ro
r –
LS
B
0.1
Digital Code
DIFFERENTIAL NONLINEARITY ERROR
0.3
2560 3328 3584 3840
0.25
0.2
0.15
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
–0.3
–0.35
–0.4
–0.45
–0.5
1024 1280 1792 2816 3072
Figure 14
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5616 is a 12-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
2 REF CODE
2n
[V]
where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n–1, where
n = 12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS
starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which
updates the voltage output to the new level.
The serial interface of the TLV5616 can be used in two basic modes:
� Four wire (with chip select)
� Three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows
an example with two TLV5616s connected directly to a TMS320 DSP.
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
TLV5616
CS FS DIN SCLK
TLV5616
CS FS DIN SCLK
Figure 15. TMS320 Interface
TLV5616C, TLV5616I
2.7-V TO 5.5-V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152C – DECEMBER 1997 – REVISED NOVEMBER 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5616 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
FSX
DX
CLKX
TLV5616
FS
DIN
SCLK
CS
SPI
SS
MOSI
SCLK
TLV5616
FS
DIN
SCLK
CS
Microwire
I/O
SO
SK
TLV5616
FS
DIN
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5616. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
fSCLKmax�
1
twH(min)� twL(min)
� 20 MHz
The maximum upd
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