EDEW1306256(W47GA-A31S00-4600)基带芯片++Allwinner

创 维 集 团 有 限 公 司 SKYWORTH (GROUP) CO., LTD. ENGINEERING EVALUATION REPORT (COMPONENTS) REPORT NO. : EDEW1306256 SAMPLE IS : MODEL : A4X10 NEW PARTS DATE COMPLETED : 2013.6.20 1st SUBMISSION QTY SUBMITTED : 2nd SUBMISSION DESCRIPTIONS ： IC A31s Quad ALTERNATE SOURCE Cortex A7 CPU 18*18*1.2 FBGA-460 Allwinner OTHER REMARKS ROHS SPECIFICATION ATTACHED YES NO REMARKS : SUPPLIER’S PART NO. : OUR PARTS NO. W47GA-A31S00-4600 SUPPLIER : MANUFACTURER : Allwinner TEST RESULT : APPROVED REJECTED CONDITIONALLY APPROVED : SEE ITEMS LISTED BELOW COMMENTS 1. 所有坏料包退换 2. 如有因元件质量问 题 快递公司问题件快递公司问题件货款处理关于圆的周长面积重点题型关于解方程组的题及答案关于南海问题 而引起的损失，元件生产厂家需负全责。　 3. 请在内/外包装箱上打印我公司物料编号：W47GA-A31S00-4600 4. 请在内外包装箱上贴上 ROHS 标示 5. 流水号：W_ASP_201306036 IF CONDITIONALLY APPROVED : (a) SUPPLIER IS REQUESTED TO SUBMIT _________ PIECES SAMPLES AGAIN. (b) FOR PURCHASING TO BUY _________ PIECES FOR PILOT PRODUCTION. TESTED BY ENGINEER (S) APPROVED BY ENGINEERING MANAGER ELECTRICAL 宋盼盼 Rm. 1601-04 Westlands Centre, 20 Westlands Road, Quarry Bay, H.K. Tel: 2856 3138 SKYWO HX Fax:2586 3590 A31s Datasheet Revision 1.0 January 30, 2013 ? ? ? ? ? ? ? ? SDT03981 矩形 A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 2 Declaration Declaration THIS A31s DATASHEET IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY (“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER. THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF ALLWINNER. THIS DATASHEET NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS FOR ANY PARTICULAR APPLICATION. THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE. ? ? ? ? ? ? ? ? A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 3 Revision History Revision History Version Date Author Description 1.0 2013.01.30 Initial Version ? ? ? ? ? ? ? ? A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 4 Table of Contents Table of Contents Declaration ........................................................................................................................................................ 2 Revision History ............................................................................................................................................... 3 Table of Contents ............................................................................................................................................. 4 1 OVERVIEW ................................................................................................................................................. 5 2 FEATURES ................................................................................................................................................. 6 3 BLOCK DIAGRAM ................................................................................................................................... 10 4 PIN DESCRIPTION ................................................................................................................................... 11 4.1. Pin Characteristics ............................................................................................................................. 11 4.2. GPIO Multiplexing Functions ............................................................................................................. 18 4.3. Detailed Pin/Signal Description ......................................................................................................... 22 4.4. Power/GND Signal Description ......................................................................................................... 27 5 ELECTRICAL CHARACTERISTICS ........................................................................................................ 29 5.1. Absolute Maximum Ratings ............................................................................................................... 29 5.2. Recommended Operating Conditions ............................................................................................... 29 5.3. DC Electrical Characteristics ............................................................................................................. 30 5.4. Oscillator Electrical Characteristics ................................................................................................... 30 5.5. Power up AND Power Down Sequence ............................................................................................ 32 6 PIN ASSIGNMENT ................................................................................................................................... 33 6.1. Ball map ............................................................................................................................................. 33 6.2. Pin Dimension .................................................................................................................................... 34 ? ? ? ? ? ? ? ? A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 5 OVERVIEW 1 OVERVIEW The Allwinner A31s processor is a quad-core phablet processor designed for the phablet market. The phablet is a product category that combines the functionalities of a smartphone with that of a tablet, and its size usually falls somewhere in between a smartphone and a tablet. The A31s processor is based on quad-core Cortex-A7 CPU, which is the most power efficient processor developed by ARM. It also comes with SGX544MP2 GPU with eight logic core to enable powerful 3D computing capability as well as excellent UI experience, especially when it comes to the smoothness of screens with large size. More importantly, A31s processor integrates a robust Audio Codec that includes two sets of I2S/PCM interface for Baseband and Bluetooth, two integrated differential analog MIC for headset and phone, as well as a digital MIC. It is capable of 3G, 2G, LTE, WiFi, Bluetooth, FM, GPS, AGPS, NFC and other voice and data wireless transmission technology with a minimum of external components. Additionally, A31s processor provides a wide range of peripheral interfaces. For example, it integrates display interfaces such as HDMI, RGB LCD and LVDS, image input interfaces such as CSI, and data interfaces such as USB OTG, USB EHCI/OHCI, SDC, SPI, UART, etc. When it comes to power efficiency, AXP221s is specially designed for the power optimization of A31s. A31s processor also supports a smart Power Consumption Management System to dynamically adjust CPU frequency and voltage, supports DRAM Dynamic Frequency Scaling technology to dynamically adjust DRAM frequency based on bandwidth requirements, and also supports Super Standby Mode to lower the system power consumption during system standby. ? ? ? ? ? ? ? ? SDT03981 矩形 A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 6 FEATURES 2 FEATURES QUAD-CORE CPU  Quad Cortex-A7 - ARMv7 ISA standard ARM instruction set plus Thumb2, Jazeller RCT - NEON SIMD coprocessor and VFPv4 for each CPU - TrustZone security technology - Hardware virtualization - Large Physical Address Extensions(LPAE) - Debug and trace features - One general timer for an individual CPU - 32KB instruction and 32KB data L1 cache for an individual CPU - Shared 1MB L2 cache GRAPHIC ENGINE  3D - PowerVR SGX544MP2 GPU - Support OpenGL ES 2.0, OpenVG 1.1, OpenCL 1.1, and DX 9.3 standards  2D - Support BLT and ROP2/3/4, scaling function with 4x4 taps and 32 phases - Support 90/180/270 degree rotation - Support mirror/alpha (plane and pixel alpha)/ color key - Format conversion: ARGB 8888/4444/1555, RGB565, Mono 1/2/4/8 bpp, Palette 1/2/4/8 bpp (input only), YUV 444/422/420 - Support command queue SYSTEM RESOURCES  Timer - 6 timers: clock source can be switched over 24M/32K for all timers, and external signals can function as clock source for timer4/5 - 33-bit AVS counter - 4 watchdogs to generate reset signal or interrupts  GIC - Support 16 SGIs, 16 PPIs, and 128 SPIs - Support ARM architecture security extensions - Support ARM architecture virtualization extensions - Support uniprocessor and multiprocessor environments  HS-Timer - 4 channels - Clock source fixed to AHB, and pre-scale ranges from 1 to 16 - 56-bit counter that can be separated to 24-bit high register and 32-bit low register  DMA - 16 channels - Support data width of 8/16/32 bits - Support linear and IO address modes - DMA channels can be paused during data transfer if necessary  RTC - Real time registers for second, minute, hour, day, month and year - Two alarms based on seconds and weeks - 16 general purpose registers  CCU - programmable PLLs MEMORY SUBSYSTEM  Internal Boot ROM - Support system boot from 8-bit NAND Flash, SPI Nor Flash (SPI0) and SD/TF/8-bit eMMC (SDC0/2) - Support system code download via USB OTG (USB0)  DRAM - Support DDR3/DDR3L/LPDDR2 - Support 32-bit bus width ? ? ? ? ? ? ? ? A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 7 FEATURES  NAND FLASH - Comply to ONFI 2.3 and toggle 1.0 - Support 64-bit ECC per 512 bytes or 1024 bytes - Support 8-bit data bus width - Support 1.8/3.3V signal voltage - Support up to 4 CE and 2 RB - Support system boot from NAND flash - Support SLC/MLC/TLC NAND and EF-NAND - Support SDR/DDR NAND interface  SD/MMC - Comply to eMMC standard specification v4.5 - Comply to SD physical layer specification v3.0 - Comply to SDIO card specification v2.0 - Support 1/4/8-bit bus width - Support HS/DS/SDR12/SDR25/SDR50 /HS200/ DDR50 bus mode - Support 1.8/3.3V adjustable power for signals - Support eMMC mandatory and alternative boot operations - Support transmit clock up to100MHz - Support four independent SD/MMC/SDIO controllers - Support SDSC/SDHC/SDXC/UHS-I/MMC/ RS-MMC Card - Support eMMC/iNand Flash - Support 1GB/2GB/4GB/8GB/16GB/32GB/ 64GB /128GB SD/MMC card - Support SDIO interrupt detection - Support build-in 64-byte FIFO for buffered read or write operations - Support descriptor-based internal DMA controller for efficient scatter and gather operations IMAGE SIGNAL PROCESSOR  Support image mirror flip and rotation  Support thumb image generation  Support two channels output  Support valid picture size up to 4096x4096  Support speed up to 250M pixel/s  ISP for YCbCr input - YCbCr gain and offset control - DRC(dynamic range compression) - Anti-flick detection statistics - Histogram statistics  ISP for RAW RGB input - Black clamp with horizontal/vertical offset compensation - Window capture - Static/dynamic defect pixel correction - Super lens shading correction - Super lens flare correction - Color dependent gain and offset control - Anisotropic non-linear bayer interpolation with false color suppression - Programmable color correction - Programmable gamma correction - DRC(dynamic range compression) - RGB2YCbCr - Non-linear 2D sharpening - Advanced contrast enhancement - Advanced spatial (2D) de-noise filter - Zone-based AE/AF/AWB statistics - Anti-flick detection statistics - Histogram statistics VIDEO ENGINE  Decoder and encoder can work at the same time  Video decoding - Picture size up to 4096x2304 - Decoding speed up to 1920x1080@60fps - Support multiple video formats: Mpeg1/2, Mpeg4 SP/ASP GMC, H.263 including Sorenson Spark, H.264 BP/MP/HP, VP6/8, AVS jizun, JPEG/MJPEG - Support tiled/YUV/YUV output format  Video Encoding - H.264 HP: picture size up to 3840x2160 - H.264 HP: speed up to 1920x1080@30fps - H.264 HP: cyclic intra refresh - H.264 HP: ROI windows - JPEG baseline: picture size up to 8192x8192 - Alpha blending - Thumb generation - 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer ratio DISPLAY ENGINE  Support dual display paths - Each path supports 4 movable and size-adjustable layers - Layer size up to 8192x8192 pixels  Ultra-scaling Engine - 8 taps in horizontal and 4 taps in vertical - Source image size from 8x4 to 8192x8192 - Destination image size from 8x4 to 8192x8192  Support multiple image input formats - Mono 1/2/4/8 bpp - Palette 1/2/4/8 bpp - 16/24/32 bpp color - YUV444/420/422/411  Support alpha blending/color key/gamma/hardware cursor  Support video post processing - De-interlacing - Detail enhancement - Dynamic range control - Color management  3D input/output format conversion and display VIDEO OUTPUT  Support HDMI 1.4 1080p@60fps  LVDS/RGB/CPU LCD interface 1280x800 ? ? ? ? ? ? ? ? A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 8 FEATURES VIDEO INPUT  Support parallel 12-bit CSI ANALOG AUDIO INPUT  Support two audio ADC channels - 96dBA SNR for ADC recording - 8KHz~ 48KHz ADC sample rate  Analog low-power loop from line-in/mic-in/ phone-in to headphone/speaker/ earpiece outputs  Accessory button press detection  Four analog audio inputs - Two differential microphone inputs - Differential phone-in input - Stereo line-in input  Support low-noise digital MIC interface  Flexible digital audio process for ADC - High pass filter and low latency decimation filter for class voice - Automatic gain control (AGC) ANALOG AUDIO OUTPUT  Two-channel audio DAC  Stereo capless headphone drivers - Up to 100dBA SNR for DAC playback - 8KHz~192KHz DAC sample rate  Support analog/digital volume control  Two low-noise analog microphone bias  Dedicated headphone/speaker/earpiece outputs, single-ended or differential  Support differential phone-out  Support two mixers for different applications - Output mixer for LINEINL/R, PHONEP/N, MIC1P/N, MIC2P/N and stereo DAC output - ADC record mixer for LINEINL/R, PHONEP/N, MIC1P/N, MIC2P/N, stereo DAC output  Flexible digital audio process for DAC - Pop suppression control - Individual high pass filter/De-emphasis filter - Support EQ equalization - Soft volume control and soft mute CONNECTIVITY  USB2.0 OTG - Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) in Host mode - Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps) in Device mode - Support up to 10 user-configurable endpoints for bulk , isochronous, control and interrupt bi-directional transfers  USB EHCI/OHCI - Two EHCI/OHCI-compliant Hosts  LRADC - Support sample rate up to 250Hz - Support 6-bit resolution - Support 0V ~2V voltage input  Digital Audio Interface - Comply to industry standard I2S/PCM specification - Two sets I2S/PCM interfaces for baseband and Bluetooth - Support Master/Slave mode and full-duplex operation - Support 8KHz ~192KHz audio sample rate - Support MCLK output for CODEC chips - Support standard I2S, left-justified, right-justified, 8/16-bit linear sample, 8-bit u-law and a-law companded sample  PWM - 4 PWM outputs - Support cycle mode and pulse mode - The pre-scale ranges from 1 to 64  Transport Stream - Support both SPI and SSI - Support 64 channels PID filter - Support hardware PCR packet detection - Speed up to 150Mbps for both SPI and SSI interface  CIR - A flexible receiver for IR remote controller  UART - Comply to industry-standard 16450/16550 UART specification - Support 16-bit programmable baud rate and dynamic modification - Support 2-wire serial communication - Support 4-wire auto data flow communication - Support 8-wire modem(data carrier equipment, DCE) or data set - Support up to 6 UART controllers  SPI - Master/Slave configurable - Up to 4 independent SPI controllers, SPI0 with only one CS signal for system boot, and SPI1/2/3 with two CS signals - Support dual input and dual output operation  TWI - Up to 5 TWIs compliant with I2C protocol - Support SCCB protocol  P2WI (Push-Pull TWI) - Support speed up to 12MHz ? ? ? ? ? ? ? ? A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 9 FEATURES  One Wire Interface - Support both standard One Wire protocol and simple HDQ protocol SECURITY SYSTEM  Support AES, DES, 3DES, SHA-1, MD5  Support ECB, CBC, CNT modes for AES/DES/3DES 128-bit, 192-bit and 256-bit key size for AES  160-bit hardware PRNG with 192-bit seed  Security JTAG POWER MANAGEMENT  Flexible PLL clock generator and 32768Hz OSC  Flexible clock gate and module reset  Support DVFS for CPU frequency and voltage adjustment  Support dynamic frequency adjustment for external DRAM controller  Support standby mode PACKAGE  FBGA 460 balls, 0.8mm ball pitch, 18mm x18mm ? ? ? ? ? ? ? ? SDT03981 矩形 A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 10 BLOCK DIAGRAM 3 BLOCK DIAGRAM Figure 3-1. A31s Block Diagram ? ? ? ? ? ? ? ? A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 11 PIN DESCRIPTION 4 PIN DESCRIPTION 4.1. PIN CHARACTERISTICS Following table describes the A31s pin characteristics. Notes 1) Pin Name defines the names of pins. Note that a group of pins with similar meaning may be expressed in the form of [x:0]; 2) Default Function defines the default function of each pin; 3) Type defines the signal direction: I (Input), O (Output), I/O(Input / Output), A (Analog), P (Power), G (Ground); 4) Default IO State defines the default IO state of each pin: DIS means disable; 5) Default Pull Up/Down defines the presence of an internal pull up or pull down resister. Unless otherwise sp